2 * Intel SMP support routines.
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
7 * This code is released under the GNU General Public License version 2 or
11 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/spinlock.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/cache.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpu.h>
22 #include <linux/module.h>
25 #include <asm/tlbflush.h>
26 #include <mach_apic.h>
29 * Some notes on x86 processor bugs affecting SMP operation:
31 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
32 * The Linux implications for SMP are handled as follows:
34 * Pentium III / [Xeon]
35 * None of the E1AP-E3AP errata are visible to the user.
42 * None of the A1AP-A3AP errata are visible to the user.
49 * None of 1AP-9AP errata are visible to the normal user,
50 * except occasional delivery of 'spurious interrupt' as trap #15.
51 * This is very rare and a non-problem.
53 * 1AP. Linux maps APIC as non-cacheable
54 * 2AP. worked around in hardware
55 * 3AP. fixed in C0 and above steppings microcode update.
56 * Linux does not use excessive STARTUP_IPIs.
57 * 4AP. worked around in hardware
58 * 5AP. symmetric IO mode (normal Linux operation) not affected.
59 * 'noapic' mode has vector 0xf filled out properly.
60 * 6AP. 'noapic' mode might be affected - fixed in later steppings
61 * 7AP. We do not assume writes to the LVT deassering IRQs
62 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
63 * 9AP. We do not use mixed mode
66 * There is a marginal case where REP MOVS on 100MHz SMP
67 * machines with B stepping processors can fail. XXX should provide
68 * an L1cache=Writethrough or L1cache=off option.
70 * B stepping CPUs may hang. There are hardware work arounds
71 * for this. We warn about it in case your board doesn't have the work
72 * arounds. Basically thats so I can tell anyone with a B stepping
73 * CPU and SMP problems "tough".
75 * Specific items [From Pentium Processor Specification Update]
77 * 1AP. Linux doesn't use remote read
78 * 2AP. Linux doesn't trust APIC errors
79 * 3AP. We work around this
80 * 4AP. Linux never generated 3 interrupts of the same priority
81 * to cause a lost local interrupt.
82 * 5AP. Remote read is never used
83 * 6AP. not affected - worked around in hardware
84 * 7AP. not affected - worked around in hardware
85 * 8AP. worked around in hardware - we get explicit CS errors if not
86 * 9AP. only 'noapic' mode affected. Might generate spurious
87 * interrupts, we log only the first one and count the
89 * 10AP. not affected - worked around in hardware
90 * 11AP. Linux reads the APIC between writes to avoid this, as per
91 * the documentation. Make sure you preserve this as it affects
92 * the C stepping chips too.
93 * 12AP. not affected - worked around in hardware
94 * 13AP. not affected - worked around in hardware
95 * 14AP. we always deassert INIT during bootup
96 * 15AP. not affected - worked around in hardware
97 * 16AP. not affected - worked around in hardware
98 * 17AP. not affected - worked around in hardware
99 * 18AP. not affected - worked around in hardware
100 * 19AP. not affected - worked around in BIOS
102 * If this sounds worrying believe me these bugs are either ___RARE___,
103 * or are signal timing bugs worked around in hardware and there's
104 * about nothing of note with C stepping upwards.
107 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
110 * the following functions deal with sending IPIs between CPUs.
112 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
115 static inline int __prepare_ICR (unsigned int shortcut, int vector)
117 unsigned int icr = shortcut | APIC_DEST_LOGICAL;
121 icr |= APIC_DM_FIXED | vector;
130 static inline int __prepare_ICR2 (unsigned int mask)
132 return SET_APIC_DEST_FIELD(mask);
135 void __send_IPI_shortcut(unsigned int shortcut, int vector)
138 * Subtle. In the case of the 'never do double writes' workaround
139 * we have to lock out interrupts to be safe. As we don't care
140 * of the value read we use an atomic rmw access to avoid costly
141 * cli/sti. Otherwise we use an even cheaper single atomic write
149 apic_wait_icr_idle();
152 * No need to touch the target chip field
154 cfg = __prepare_ICR(shortcut, vector);
157 * Send the IPI. The write to APIC_ICR fires this off.
159 apic_write_around(APIC_ICR, cfg);
162 void fastcall send_IPI_self(int vector)
164 __send_IPI_shortcut(APIC_DEST_SELF, vector);
168 * This is used to send an IPI with no shorthand notation (the destination is
169 * specified in bits 56 to 63 of the ICR).
171 static inline void __send_IPI_dest_field(unsigned long mask, int vector)
178 if (unlikely(vector == NMI_VECTOR))
179 safe_apic_wait_icr_idle();
181 apic_wait_icr_idle();
184 * prepare target chip field
186 cfg = __prepare_ICR2(mask);
187 apic_write_around(APIC_ICR2, cfg);
192 cfg = __prepare_ICR(0, vector);
195 * Send the IPI. The write to APIC_ICR fires this off.
197 apic_write_around(APIC_ICR, cfg);
201 * This is only used on smaller machines.
203 void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
205 unsigned long mask = cpus_addr(cpumask)[0];
208 local_irq_save(flags);
209 WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
210 __send_IPI_dest_field(mask, vector);
211 local_irq_restore(flags);
214 void send_IPI_mask_sequence(cpumask_t mask, int vector)
217 unsigned int query_cpu;
220 * Hack. The clustered APIC addressing mode doesn't allow us to send
221 * to an arbitrary mask, so I do a unicasts to each CPU instead. This
222 * should be modified to do 1 message per cluster ID - mbligh
225 local_irq_save(flags);
226 for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {
227 if (cpu_isset(query_cpu, mask)) {
228 __send_IPI_dest_field(cpu_to_logical_apicid(query_cpu),
232 local_irq_restore(flags);
235 #include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
238 * Smarter SMP flushing macros.
239 * c/o Linus Torvalds.
241 * These mean you can really definitely utterly forget about
242 * writing to user space from interrupts. (Its not allowed anyway).
244 * Optimizations Manfred Spraul <manfred@colorfullife.com>
247 static cpumask_t flush_cpumask;
248 static struct mm_struct * flush_mm;
249 static unsigned long flush_va;
250 static DEFINE_SPINLOCK(tlbstate_lock);
253 * We cannot call mmdrop() because we are in interrupt context,
254 * instead update mm->cpu_vm_mask.
256 * We need to reload %cr3 since the page tables may be going
257 * away from under us..
259 static inline void leave_mm (unsigned long cpu)
261 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
263 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
264 load_cr3(swapper_pg_dir);
269 * The flush IPI assumes that a thread switch happens in this order:
270 * [cpu0: the cpu that switches]
271 * 1) switch_mm() either 1a) or 1b)
272 * 1a) thread switch to a different mm
273 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
274 * Stop ipi delivery for the old mm. This is not synchronized with
275 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
276 * for the wrong mm, and in the worst case we perform a superflous
278 * 1a2) set cpu_tlbstate to TLBSTATE_OK
279 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
280 * was in lazy tlb mode.
281 * 1a3) update cpu_tlbstate[].active_mm
282 * Now cpu0 accepts tlb flushes for the new mm.
283 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
284 * Now the other cpus will send tlb flush ipis.
286 * 1b) thread switch without mm change
287 * cpu_tlbstate[].active_mm is correct, cpu0 already handles
289 * 1b1) set cpu_tlbstate to TLBSTATE_OK
290 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
291 * Atomically set the bit [other cpus will start sending flush ipis],
293 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
294 * 2) switch %%esp, ie current
296 * The interrupt must handle 2 special cases:
297 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
298 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
299 * runs in kernel space, the cpu could load tlb entries for user space
302 * The good news is that cpu_tlbstate is local to each cpu, no
303 * write/read ordering problems.
309 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
310 * 2) Leave the mm if we are in the lazy tlb mode.
313 fastcall void smp_invalidate_interrupt(struct pt_regs *regs)
319 if (!cpu_isset(cpu, flush_cpumask))
322 * This was a BUG() but until someone can quote me the
323 * line from the intel manual that guarantees an IPI to
324 * multiple CPUs is retried _only_ on the erroring CPUs
325 * its staying as a return
330 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
331 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
332 if (flush_va == TLB_FLUSH_ALL)
335 __flush_tlb_one(flush_va);
340 smp_mb__before_clear_bit();
341 cpu_clear(cpu, flush_cpumask);
342 smp_mb__after_clear_bit();
344 put_cpu_no_resched();
347 void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm,
350 cpumask_t cpumask = *cpumaskp;
353 * A couple of (to be removed) sanity checks:
355 * - current CPU must not be in mask
356 * - mask must exist :)
358 BUG_ON(cpus_empty(cpumask));
359 BUG_ON(cpu_isset(smp_processor_id(), cpumask));
362 /* If a CPU which we ran on has gone down, OK. */
363 cpus_and(cpumask, cpumask, cpu_online_map);
364 if (cpus_empty(cpumask))
368 * i'm not happy about this global shared spinlock in the
369 * MM hot path, but we'll see how contended it is.
370 * AK: x86-64 has a faster method that could be ported.
372 spin_lock(&tlbstate_lock);
376 #if NR_CPUS <= BITS_PER_LONG
377 atomic_set_mask(cpumask, &flush_cpumask);
381 unsigned long *flush_mask = (unsigned long *)&flush_cpumask;
382 unsigned long *cpu_mask = (unsigned long *)&cpumask;
383 for (k = 0; k < BITS_TO_LONGS(NR_CPUS); ++k)
384 atomic_set_mask(cpu_mask[k], &flush_mask[k]);
388 * We have to send the IPI only to
391 send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
393 while (!cpus_empty(flush_cpumask))
394 /* nothing. lockup detection does not belong here */
399 spin_unlock(&tlbstate_lock);
402 void flush_tlb_current_task(void)
404 struct mm_struct *mm = current->mm;
408 cpu_mask = mm->cpu_vm_mask;
409 cpu_clear(smp_processor_id(), cpu_mask);
412 if (!cpus_empty(cpu_mask))
413 flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
417 void flush_tlb_mm (struct mm_struct * mm)
422 cpu_mask = mm->cpu_vm_mask;
423 cpu_clear(smp_processor_id(), cpu_mask);
425 if (current->active_mm == mm) {
429 leave_mm(smp_processor_id());
431 if (!cpus_empty(cpu_mask))
432 flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
437 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
439 struct mm_struct *mm = vma->vm_mm;
443 cpu_mask = mm->cpu_vm_mask;
444 cpu_clear(smp_processor_id(), cpu_mask);
446 if (current->active_mm == mm) {
450 leave_mm(smp_processor_id());
453 if (!cpus_empty(cpu_mask))
454 flush_tlb_others(cpu_mask, mm, va);
458 EXPORT_SYMBOL(flush_tlb_page);
460 static void do_flush_tlb_all(void* info)
462 unsigned long cpu = smp_processor_id();
465 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
469 void flush_tlb_all(void)
471 on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
475 * this function sends a 'reschedule' IPI to another CPU.
476 * it goes straight through and wastes no time serializing
477 * anything. Worst case is that we lose a reschedule ...
479 void native_smp_send_reschedule(int cpu)
481 WARN_ON(cpu_is_offline(cpu));
482 send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
486 * Structure and data for smp_call_function(). This is designed to minimise
487 * static memory requirements. It also looks cleaner.
489 static DEFINE_SPINLOCK(call_lock);
491 struct call_data_struct {
492 void (*func) (void *info);
499 void lock_ipi_call_lock(void)
501 spin_lock_irq(&call_lock);
504 void unlock_ipi_call_lock(void)
506 spin_unlock_irq(&call_lock);
509 static struct call_data_struct *call_data;
511 static void __smp_call_function(void (*func) (void *info), void *info,
512 int nonatomic, int wait)
514 struct call_data_struct data;
515 int cpus = num_online_cpus() - 1;
522 atomic_set(&data.started, 0);
525 atomic_set(&data.finished, 0);
530 /* Send a message to all other CPUs and wait for them to respond */
531 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
533 /* Wait for response */
534 while (atomic_read(&data.started) != cpus)
538 while (atomic_read(&data.finished) != cpus)
544 * smp_call_function_mask(): Run a function on a set of other CPUs.
545 * @mask: The set of cpus to run on. Must not include the current cpu.
546 * @func: The function to run. This must be fast and non-blocking.
547 * @info: An arbitrary pointer to pass to the function.
548 * @wait: If true, wait (atomically) until function has completed on other CPUs.
550 * Returns 0 on success, else a negative status code.
552 * If @wait is true, then returns once @func has returned; otherwise
553 * it returns just before the target cpu calls @func.
555 * You must not call this function with disabled interrupts or from a
556 * hardware interrupt handler or from a bottom half handler.
558 int native_smp_call_function_mask(cpumask_t mask,
559 void (*func)(void *), void *info,
562 struct call_data_struct data;
563 cpumask_t allbutself;
566 /* Can deadlock when called with interrupts disabled */
567 WARN_ON(irqs_disabled());
569 /* Holding any lock stops cpus from going down. */
570 spin_lock(&call_lock);
572 allbutself = cpu_online_map;
573 cpu_clear(smp_processor_id(), allbutself);
575 cpus_and(mask, mask, allbutself);
576 cpus = cpus_weight(mask);
579 spin_unlock(&call_lock);
585 atomic_set(&data.started, 0);
588 atomic_set(&data.finished, 0);
593 /* Send a message to other CPUs */
594 if (cpus_equal(mask, allbutself))
595 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
597 send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
599 /* Wait for response */
600 while (atomic_read(&data.started) != cpus)
604 while (atomic_read(&data.finished) != cpus)
606 spin_unlock(&call_lock);
612 * smp_call_function(): Run a function on all other CPUs.
613 * @func: The function to run. This must be fast and non-blocking.
614 * @info: An arbitrary pointer to pass to the function.
615 * @nonatomic: Unused.
616 * @wait: If true, wait (atomically) until function has completed on other CPUs.
618 * Returns 0 on success, else a negative status code.
620 * If @wait is true, then returns once @func has returned; otherwise
621 * it returns just before the target cpu calls @func.
623 * You must not call this function with disabled interrupts or from a
624 * hardware interrupt handler or from a bottom half handler.
626 int smp_call_function(void (*func) (void *info), void *info, int nonatomic,
629 return smp_call_function_mask(cpu_online_map, func, info, wait);
631 EXPORT_SYMBOL(smp_call_function);
634 * smp_call_function_single - Run a function on another CPU
635 * @cpu: The target CPU. Cannot be the calling CPU.
636 * @func: The function to run. This must be fast and non-blocking.
637 * @info: An arbitrary pointer to pass to the function.
638 * @nonatomic: Unused.
639 * @wait: If true, wait until function has completed on other CPUs.
641 * Returns 0 on success, else a negative status code.
643 * If @wait is true, then returns once @func has returned; otherwise
644 * it returns just before the target cpu calls @func.
646 int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
647 int nonatomic, int wait)
649 /* prevent preemption and reschedule on another processor */
658 ret = smp_call_function_mask(cpumask_of_cpu(cpu), func, info, wait);
663 EXPORT_SYMBOL(smp_call_function_single);
665 static void stop_this_cpu (void * dummy)
671 cpu_clear(smp_processor_id(), cpu_online_map);
672 disable_local_APIC();
673 if (cpu_data[smp_processor_id()].hlt_works_ok)
679 * this function calls the 'stop' function on all other CPUs in the system.
682 void native_smp_send_stop(void)
684 /* Don't deadlock on the call lock in panic */
685 int nolock = !spin_trylock(&call_lock);
688 local_irq_save(flags);
689 __smp_call_function(stop_this_cpu, NULL, 0, 0);
691 spin_unlock(&call_lock);
692 disable_local_APIC();
693 local_irq_restore(flags);
697 * Reschedule call back. Nothing to do,
698 * all the work is done automatically when
699 * we return from the interrupt.
701 fastcall void smp_reschedule_interrupt(struct pt_regs *regs)
706 fastcall void smp_call_function_interrupt(struct pt_regs *regs)
708 void (*func) (void *info) = call_data->func;
709 void *info = call_data->info;
710 int wait = call_data->wait;
714 * Notify initiating CPU that I've grabbed the data and am
715 * about to execute the function
718 atomic_inc(&call_data->started);
720 * At this point the info structure may be out of scope unless wait==1
728 atomic_inc(&call_data->finished);
732 static int convert_apicid_to_cpu(int apic_id)
736 for (i = 0; i < NR_CPUS; i++) {
737 if (x86_cpu_to_apicid[i] == apic_id)
743 int safe_smp_processor_id(void)
747 if (!boot_cpu_has(X86_FEATURE_APIC))
750 apicid = hard_smp_processor_id();
751 if (apicid == BAD_APICID)
754 cpuid = convert_apicid_to_cpu(apicid);
756 return cpuid >= 0 ? cpuid : 0;
759 struct smp_ops smp_ops = {
760 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
761 .smp_prepare_cpus = native_smp_prepare_cpus,
762 .cpu_up = native_cpu_up,
763 .smp_cpus_done = native_smp_cpus_done,
765 .smp_send_stop = native_smp_send_stop,
766 .smp_send_reschedule = native_smp_send_reschedule,
767 .smp_call_function_mask = native_smp_call_function_mask,