1 #include <linux/errno.h>
2 #include <linux/signal.h>
3 #include <linux/sched.h>
4 #include <linux/ioport.h>
5 #include <linux/interrupt.h>
6 #include <linux/slab.h>
7 #include <linux/random.h>
8 #include <linux/smp_lock.h>
9 #include <linux/init.h>
10 #include <linux/kernel_stat.h>
11 #include <linux/sysdev.h>
12 #include <linux/bitops.h>
14 #include <asm/8253pit.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
18 #include <asm/timer.h>
19 #include <asm/pgtable.h>
20 #include <asm/delay.h>
23 #include <asm/arch_hooks.h>
24 #include <asm/i8259.h>
29 * This is the 'legacy' 8259A Programmable Interrupt Controller,
30 * present in the majority of PC/AT boxes.
31 * plus some generic x86 specific things if generic specifics makes
33 * this file should become arch/i386/kernel/irq.c when the old irq.c
34 * moves to arch independent land
37 DEFINE_SPINLOCK(i8259A_lock);
39 static void end_8259A_irq (unsigned int irq)
41 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
43 enable_8259A_irq(irq);
46 #define shutdown_8259A_irq disable_8259A_irq
48 static int i8259A_auto_eoi;
50 static void mask_and_ack_8259A(unsigned int);
52 unsigned int startup_8259A_irq(unsigned int irq)
54 enable_8259A_irq(irq);
55 return 0; /* never anything pending */
58 static struct hw_interrupt_type i8259A_irq_type = {
60 .startup = startup_8259A_irq,
61 .shutdown = shutdown_8259A_irq,
62 .enable = enable_8259A_irq,
63 .disable = disable_8259A_irq,
64 .ack = mask_and_ack_8259A,
69 * 8259A PIC functions to handle ISA devices:
73 * This contains the irq mask for both 8259A irq controllers,
75 unsigned int cached_irq_mask = 0xffff;
78 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
79 * boards the timer interrupt is not really connected to any IO-APIC pin,
80 * it's fed to the master 8259A's IR0 line only.
82 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
83 * this 'mixed mode' IRQ handling costs nothing because it's only used
86 unsigned long io_apic_irqs;
88 void disable_8259A_irq(unsigned int irq)
90 unsigned int mask = 1 << irq;
93 spin_lock_irqsave(&i8259A_lock, flags);
94 cached_irq_mask |= mask;
96 outb(cached_slave_mask, PIC_SLAVE_IMR);
98 outb(cached_master_mask, PIC_MASTER_IMR);
99 spin_unlock_irqrestore(&i8259A_lock, flags);
102 void enable_8259A_irq(unsigned int irq)
104 unsigned int mask = ~(1 << irq);
107 spin_lock_irqsave(&i8259A_lock, flags);
108 cached_irq_mask &= mask;
110 outb(cached_slave_mask, PIC_SLAVE_IMR);
112 outb(cached_master_mask, PIC_MASTER_IMR);
113 spin_unlock_irqrestore(&i8259A_lock, flags);
116 int i8259A_irq_pending(unsigned int irq)
118 unsigned int mask = 1<<irq;
122 spin_lock_irqsave(&i8259A_lock, flags);
124 ret = inb(PIC_MASTER_CMD) & mask;
126 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
127 spin_unlock_irqrestore(&i8259A_lock, flags);
132 void make_8259A_irq(unsigned int irq)
134 disable_irq_nosync(irq);
135 io_apic_irqs &= ~(1<<irq);
136 irq_desc[irq].chip = &i8259A_irq_type;
141 * This function assumes to be called rarely. Switching between
142 * 8259A registers is slow.
143 * This has to be protected by the irq controller spinlock
144 * before being called.
146 static inline int i8259A_irq_real(unsigned int irq)
149 int irqmask = 1<<irq;
152 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
153 value = inb(PIC_MASTER_CMD) & irqmask;
154 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
157 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
158 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
159 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
164 * Careful! The 8259A is a fragile beast, it pretty
165 * much _has_ to be done exactly like this (mask it
166 * first, _then_ send the EOI, and the order of EOI
167 * to the two 8259s is important!
169 static void mask_and_ack_8259A(unsigned int irq)
171 unsigned int irqmask = 1 << irq;
174 spin_lock_irqsave(&i8259A_lock, flags);
176 * Lightweight spurious IRQ detection. We do not want
177 * to overdo spurious IRQ handling - it's usually a sign
178 * of hardware problems, so we only do the checks we can
179 * do without slowing down good hardware unnecessarily.
181 * Note that IRQ7 and IRQ15 (the two spurious IRQs
182 * usually resulting from the 8259A-1|2 PICs) occur
183 * even if the IRQ is masked in the 8259A. Thus we
184 * can check spurious 8259A IRQs without doing the
185 * quite slow i8259A_irq_real() call for every IRQ.
186 * This does not cover 100% of spurious interrupts,
187 * but should be enough to warn the user that there
188 * is something bad going on ...
190 if (cached_irq_mask & irqmask)
191 goto spurious_8259A_irq;
192 cached_irq_mask |= irqmask;
196 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
197 outb(cached_slave_mask, PIC_SLAVE_IMR);
198 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
199 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
201 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
202 outb(cached_master_mask, PIC_MASTER_IMR);
203 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
205 spin_unlock_irqrestore(&i8259A_lock, flags);
210 * this is the slow path - should happen rarely.
212 if (i8259A_irq_real(irq))
214 * oops, the IRQ _is_ in service according to the
215 * 8259A - not spurious, go handle it.
217 goto handle_real_irq;
220 static int spurious_irq_mask;
222 * At this point we can be sure the IRQ is spurious,
223 * lets ACK and report it. [once per IRQ]
225 if (!(spurious_irq_mask & irqmask)) {
226 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
227 spurious_irq_mask |= irqmask;
229 atomic_inc(&irq_err_count);
231 * Theoretically we do not have to handle this IRQ,
232 * but in Linux this does not cause problems and is
235 goto handle_real_irq;
239 static char irq_trigger[2];
241 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
243 static void restore_ELCR(char *trigger)
245 outb(trigger[0], 0x4d0);
246 outb(trigger[1], 0x4d1);
249 static void save_ELCR(char *trigger)
251 /* IRQ 0,1,2,8,13 are marked as reserved */
252 trigger[0] = inb(0x4d0) & 0xF8;
253 trigger[1] = inb(0x4d1) & 0xDE;
256 static int i8259A_resume(struct sys_device *dev)
258 init_8259A(i8259A_auto_eoi);
259 restore_ELCR(irq_trigger);
263 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
265 save_ELCR(irq_trigger);
269 static int i8259A_shutdown(struct sys_device *dev)
271 /* Put the i8259A into a quiescent state that
272 * the kernel initialization code can get it
275 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
276 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
280 static struct sysdev_class i8259_sysdev_class = {
281 set_kset_name("i8259"),
282 .suspend = i8259A_suspend,
283 .resume = i8259A_resume,
284 .shutdown = i8259A_shutdown,
287 static struct sys_device device_i8259A = {
289 .cls = &i8259_sysdev_class,
292 static int __init i8259A_init_sysfs(void)
294 int error = sysdev_class_register(&i8259_sysdev_class);
296 error = sysdev_register(&device_i8259A);
300 device_initcall(i8259A_init_sysfs);
302 void init_8259A(int auto_eoi)
306 i8259A_auto_eoi = auto_eoi;
308 spin_lock_irqsave(&i8259A_lock, flags);
310 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
311 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
314 * outb_p - this has to work on a wide range of PC hardware.
316 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
317 outb_p(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
318 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
319 if (auto_eoi) /* master does Auto EOI */
320 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
321 else /* master expects normal EOI */
322 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
324 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
325 outb_p(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
326 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
327 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
330 * in AEOI mode we just have to mask the interrupt
333 i8259A_irq_type.ack = disable_8259A_irq;
335 i8259A_irq_type.ack = mask_and_ack_8259A;
337 udelay(100); /* wait for 8259A to initialize */
339 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
340 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
342 spin_unlock_irqrestore(&i8259A_lock, flags);
346 * Note that on a 486, we don't want to do a SIGFPE on an irq13
347 * as the irq is unreliable, and exception 16 works correctly
348 * (ie as explained in the intel literature). On a 386, you
349 * can't use exception 16 due to bad IBM design, so we have to
350 * rely on the less exact irq13.
352 * Careful.. Not only is IRQ13 unreliable, but it is also
353 * leads to races. IBM designers who came up with it should
358 static irqreturn_t math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
360 extern void math_error(void __user *);
362 if (ignore_fpu_irq || !boot_cpu_data.hard_math)
364 math_error((void __user *)regs->eip);
369 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
370 * so allow interrupt sharing.
372 static struct irqaction fpu_irq = { math_error_irq, 0, CPU_MASK_NONE, "fpu", NULL, NULL };
374 void __init init_ISA_irqs (void)
378 #ifdef CONFIG_X86_LOCAL_APIC
383 for (i = 0; i < NR_IRQS; i++) {
384 irq_desc[i].status = IRQ_DISABLED;
385 irq_desc[i].action = NULL;
386 irq_desc[i].depth = 1;
390 * 16 old-style INTA-cycle interrupts:
392 irq_desc[i].chip = &i8259A_irq_type;
395 * 'high' PCI IRQs filled in on demand
397 irq_desc[i].chip = &no_irq_type;
402 void __init init_IRQ(void)
406 /* all the set up before the call gates are initialised */
407 pre_intr_init_hook();
410 * Cover the whole vector space, no vector can escape
411 * us. (some of these will be overridden and become
412 * 'special' SMP interrupts)
414 for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
415 int vector = FIRST_EXTERNAL_VECTOR + i;
418 if (vector != SYSCALL_VECTOR)
419 set_intr_gate(vector, interrupt[i]);
422 /* setup after call gates are initialised (usually add in
423 * the architecture specific gates)
428 * Set the clock to HZ Hz, we already have a valid
434 * External FPU? Set up irq13 if so, for
435 * original braindamaged IBM FERR coupling.
437 if (boot_cpu_data.hard_math && !cpu_has_fpu)
438 setup_irq(FPU_IRQ, &fpu_irq);
440 irq_ctx_init(smp_processor_id());