2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is backward compatible with v1, but adds
12 * LONGHAUL MSR for purpose of both frequency and voltage scaling.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14 * Version 3 of longhaul got renamed to Powersaver and redesigned
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17 * It's pretty much the same feature wise to longhaul v2, though
18 * there is provision for scaling FSB too, but this doesn't work
19 * too well in practice so we don't even try to use this.
21 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
35 #include <asm/timex.h>
38 #include <linux/acpi.h>
39 #include <acpi/processor.h>
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
53 #define CPU_NEHEMIAH 5
54 #define CPU_NEHEMIAH_C 6
57 #define USE_ACPI_C3 (1 << 1)
58 #define USE_NORTHBRIDGE (1 << 2)
61 static unsigned int numscales=16;
62 static unsigned int fsb;
64 static const struct mV_pos *vrm_mV_table;
65 static const unsigned char *mV_vrm_table;
67 static unsigned int highest_speed, lowest_speed; /* kHz */
68 static unsigned int minmult, maxmult;
69 static int can_scale_voltage;
70 static struct acpi_processor *pr = NULL;
71 static struct acpi_processor_cx *cx = NULL;
72 static u32 acpi_regs_addr;
73 static u8 longhaul_flags;
74 static unsigned int longhaul_index;
76 /* Module parameters */
77 static int scale_voltage;
78 static int disable_acpi_c3;
80 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
83 /* Clock ratios multiplied by 10 */
84 static int clock_ratio[32];
85 static int eblcr_table[32];
86 static int longhaul_version;
87 static struct cpufreq_frequency_table *longhaul_table;
89 #ifdef CONFIG_CPU_FREQ_DEBUG
90 static char speedbuffer[8];
92 static char *print_speed(int speed)
95 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
100 snprintf(speedbuffer, sizeof(speedbuffer),
101 "%dGHz", speed/1000);
103 snprintf(speedbuffer, sizeof(speedbuffer),
104 "%d.%dGHz", speed/1000, (speed%1000)/100);
111 static unsigned int calc_speed(int mult)
122 static int longhaul_get_cpu_mult(void)
124 unsigned long invalue=0,lo, hi;
126 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
127 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
128 if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
132 return eblcr_table[invalue];
135 /* For processor with BCR2 MSR */
137 static void do_longhaul1(unsigned int clock_ratio_index)
141 rdmsrl(MSR_VIA_BCR2, bcr2.val);
142 /* Enable software clock multiplier */
143 bcr2.bits.ESOFTBF = 1;
144 bcr2.bits.CLOCKMUL = clock_ratio_index & 0xff;
146 /* Sync to timer tick */
148 /* Change frequency on next halt or sleep */
149 wrmsrl(MSR_VIA_BCR2, bcr2.val);
150 /* Invoke transition */
151 ACPI_FLUSH_CPU_CACHE();
154 /* Disable software clock multiplier */
156 rdmsrl(MSR_VIA_BCR2, bcr2.val);
157 bcr2.bits.ESOFTBF = 0;
158 wrmsrl(MSR_VIA_BCR2, bcr2.val);
161 /* For processor with Longhaul MSR */
163 static void do_powersaver(int cx_address, unsigned int clock_ratio_index,
166 union msr_longhaul longhaul;
169 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
170 /* Setup new frequency */
171 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
172 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
173 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
174 /* Setup new voltage */
175 if (can_scale_voltage)
176 longhaul.bits.SoftVID = (clock_ratio_index >> 8) & 0x1f;
177 /* Sync to timer tick */
179 /* Raise voltage if necessary */
180 if (can_scale_voltage && dir) {
181 longhaul.bits.EnableSoftVID = 1;
182 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
185 ACPI_FLUSH_CPU_CACHE();
188 ACPI_FLUSH_CPU_CACHE();
191 /* Dummy op - must do something useless after P_LVL3
193 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
195 longhaul.bits.EnableSoftVID = 0;
196 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
199 /* Change frequency on next halt or sleep */
200 longhaul.bits.EnableSoftBusRatio = 1;
201 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
203 ACPI_FLUSH_CPU_CACHE();
206 ACPI_FLUSH_CPU_CACHE();
209 /* Dummy op - must do something useless after P_LVL3 read */
210 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
212 /* Disable bus ratio bit */
213 longhaul.bits.EnableSoftBusRatio = 0;
214 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
216 /* Reduce voltage if necessary */
217 if (can_scale_voltage && !dir) {
218 longhaul.bits.EnableSoftVID = 1;
219 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
222 ACPI_FLUSH_CPU_CACHE();
225 ACPI_FLUSH_CPU_CACHE();
228 /* Dummy op - must do something useless after P_LVL3
230 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
232 longhaul.bits.EnableSoftVID = 0;
233 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
238 * longhaul_set_cpu_frequency()
239 * @clock_ratio_index : bitpattern of the new multiplier.
241 * Sets a new clock ratio.
244 static void longhaul_setstate(unsigned int table_index)
246 unsigned int clock_ratio_index;
248 struct cpufreq_freqs freqs;
250 unsigned int pic1_mask, pic2_mask;
252 u32 bm_timeout = 1000;
253 unsigned int dir = 0;
255 clock_ratio_index = longhaul_table[table_index].index;
256 /* Safety precautions */
257 mult = clock_ratio[clock_ratio_index & 0x1f];
260 speed = calc_speed(mult);
261 if ((speed > highest_speed) || (speed < lowest_speed))
263 /* Voltage transition before frequency transition? */
264 if (can_scale_voltage && longhaul_index < table_index)
267 freqs.old = calc_speed(longhaul_get_cpu_mult());
269 freqs.cpu = 0; /* longhaul.c is UP only driver */
271 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
273 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
274 fsb, mult/10, mult%10, print_speed(speed/1000));
277 local_irq_save(flags);
279 pic2_mask = inb(0xA1);
280 pic1_mask = inb(0x21); /* works on C3. save mask. */
281 outb(0xFF,0xA1); /* Overkill */
282 outb(0xFE,0x21); /* TMR0 only */
284 /* Wait while PCI bus is busy. */
285 if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
286 || ((pr != NULL) && pr->flags.bm_control))) {
287 bm_status = inw(acpi_regs_addr);
289 while (bm_status && bm_timeout) {
290 outw(1 << 4, acpi_regs_addr);
292 bm_status = inw(acpi_regs_addr);
297 if (longhaul_flags & USE_NORTHBRIDGE) {
298 /* Disable AGP and PCI arbiters */
300 } else if ((pr != NULL) && pr->flags.bm_control) {
301 /* Disable bus master arbitration */
302 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
304 switch (longhaul_version) {
307 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
308 * Software controlled multipliers only.
310 case TYPE_LONGHAUL_V1:
311 do_longhaul1(clock_ratio_index);
315 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
317 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
318 * Nehemiah can do FSB scaling too, but this has never been proven
319 * to work in practice.
321 case TYPE_LONGHAUL_V2:
322 case TYPE_POWERSAVER:
323 if (longhaul_flags & USE_ACPI_C3) {
324 /* Don't allow wakeup */
325 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
326 do_powersaver(cx->address, clock_ratio_index, dir);
328 do_powersaver(0, clock_ratio_index, dir);
333 if (longhaul_flags & USE_NORTHBRIDGE) {
334 /* Enable arbiters */
336 } else if ((pr != NULL) && pr->flags.bm_control) {
337 /* Enable bus master arbitration */
338 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
340 outb(pic2_mask,0xA1); /* restore mask */
341 outb(pic1_mask,0x21);
343 local_irq_restore(flags);
346 freqs.new = calc_speed(longhaul_get_cpu_mult());
347 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
350 printk(KERN_INFO PFX "Warning: Timeout while waiting for idle PCI bus.\n");
354 * Centaur decided to make life a little more tricky.
355 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
356 * Samuel2 and above have to try and guess what the FSB is.
357 * We do this by assuming we booted at maximum multiplier, and interpolate
358 * between that value multiplied by possible FSBs and cpu_mhz which
359 * was calculated at boot time. Really ugly, but no other way to do this.
364 static int guess_fsb(int mult)
366 int speed = cpu_khz / 1000;
368 int speeds[] = { 666, 1000, 1333, 2000 };
371 for (i = 0; i < 4; i++) {
372 f_max = ((speeds[i] * mult) + 50) / 100;
373 f_max += (ROUNDING / 2);
374 f_min = f_max - ROUNDING;
375 if ((speed <= f_max) && (speed >= f_min))
376 return speeds[i] / 10;
382 static int __init longhaul_get_ranges(void)
384 unsigned int i, j, k = 0;
388 /* Get current frequency */
389 mult = longhaul_get_cpu_mult();
391 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
394 fsb = guess_fsb(mult);
396 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
399 /* Get max multiplier - as we always did.
400 * Longhaul MSR is usefull only when voltage scaling is enabled.
401 * C3 is booting at max anyway. */
403 /* Get min multiplier */
416 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
417 minmult/10, minmult%10, maxmult/10, maxmult%10);
419 highest_speed = calc_speed(maxmult);
420 lowest_speed = calc_speed(minmult);
421 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
422 print_speed(lowest_speed/1000),
423 print_speed(highest_speed/1000));
425 if (lowest_speed == highest_speed) {
426 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
429 if (lowest_speed > highest_speed) {
430 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
431 lowest_speed, highest_speed);
435 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
439 for (j = 0; j < numscales; j++) {
440 ratio = clock_ratio[j];
443 if (ratio > maxmult || ratio < minmult)
445 longhaul_table[k].frequency = calc_speed(ratio);
446 longhaul_table[k].index = j;
450 kfree(longhaul_table);
454 for (j = 0; j < k - 1; j++) {
455 unsigned int min_f, min_i;
456 min_f = longhaul_table[j].frequency;
458 for (i = j + 1; i < k; i++) {
459 if (longhaul_table[i].frequency < min_f) {
460 min_f = longhaul_table[i].frequency;
466 temp = longhaul_table[j].frequency;
467 longhaul_table[j].frequency = longhaul_table[min_i].frequency;
468 longhaul_table[min_i].frequency = temp;
469 temp = longhaul_table[j].index;
470 longhaul_table[j].index = longhaul_table[min_i].index;
471 longhaul_table[min_i].index = temp;
475 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
477 /* Find index we are running on */
478 for (j = 0; j < k; j++) {
479 if (clock_ratio[longhaul_table[j].index & 0x1f] == mult) {
488 static void __init longhaul_setup_voltagescaling(void)
490 union msr_longhaul longhaul;
491 struct mV_pos minvid, maxvid, vid;
492 unsigned int j, speed, pos, kHz_step, numvscales;
495 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
496 if (!(longhaul.bits.RevisionID & 1)) {
497 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
501 if (!longhaul.bits.VRMRev) {
502 printk(KERN_INFO PFX "VRM 8.5\n");
503 vrm_mV_table = &vrm85_mV[0];
504 mV_vrm_table = &mV_vrm85[0];
506 printk(KERN_INFO PFX "Mobile VRM\n");
507 if (cpu_model < CPU_NEHEMIAH)
509 vrm_mV_table = &mobilevrm_mV[0];
510 mV_vrm_table = &mV_mobilevrm[0];
513 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
514 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
516 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
517 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
518 "Voltage scaling disabled.\n",
519 minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
523 if (minvid.mV == maxvid.mV) {
524 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
525 "both %d.%03d. Voltage scaling disabled\n",
526 maxvid.mV/1000, maxvid.mV%1000);
530 /* How many voltage steps */
531 numvscales = maxvid.pos - minvid.pos + 1;
535 "%d possible voltage scales\n",
536 maxvid.mV/1000, maxvid.mV%1000,
537 minvid.mV/1000, minvid.mV%1000,
540 /* Calculate max frequency at min voltage */
541 j = longhaul.bits.MinMHzBR;
542 if (longhaul.bits.MinMHzBR4)
544 min_vid_speed = eblcr_table[j];
545 if (min_vid_speed == -1)
547 switch (longhaul.bits.MinMHzFSB) {
549 min_vid_speed *= 13333;
552 min_vid_speed *= 10000;
555 min_vid_speed *= 6666;
561 if (min_vid_speed >= highest_speed)
563 /* Calculate kHz for one voltage step */
564 kHz_step = (highest_speed - min_vid_speed) / numvscales;
567 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
568 speed = longhaul_table[j].frequency;
569 if (speed > min_vid_speed)
570 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
573 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
574 vid = vrm_mV_table[mV_vrm_table[pos]];
575 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n", speed, j, vid.mV);
579 can_scale_voltage = 1;
580 printk(KERN_INFO PFX "Voltage scaling enabled.\n");
584 static int longhaul_verify(struct cpufreq_policy *policy)
586 return cpufreq_frequency_table_verify(policy, longhaul_table);
590 static int longhaul_target(struct cpufreq_policy *policy,
591 unsigned int target_freq, unsigned int relation)
593 unsigned int table_index = 0;
595 unsigned int dir = 0;
598 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
601 /* Don't set same frequency again */
602 if (longhaul_index == table_index)
605 if (!can_scale_voltage)
606 longhaul_setstate(table_index);
608 /* On test system voltage transitions exceeding single
609 * step up or down were turning motherboard off. Both
610 * "ondemand" and "userspace" are unsafe. C7 is doing
611 * this in hardware, C3 is old and we need to do this
614 current_vid = (longhaul_table[longhaul_index].index >> 8) & 0x1f;
615 if (table_index > longhaul_index)
617 while (i != table_index) {
618 vid = (longhaul_table[i].index >> 8) & 0x1f;
619 if (vid != current_vid) {
620 longhaul_setstate(i);
629 longhaul_setstate(table_index);
631 longhaul_index = table_index;
636 static unsigned int longhaul_get(unsigned int cpu)
640 return calc_speed(longhaul_get_cpu_mult());
643 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
645 void *context, void **return_value)
647 struct acpi_device *d;
649 if ( acpi_bus_get_device(obj_handle, &d) ) {
652 *return_value = (void *)acpi_driver_data(d);
656 /* VIA don't support PM2 reg, but have something similar */
657 static int enable_arbiter_disable(void)
664 /* Find PLE133 host bridge */
666 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
668 /* Find PM133/VT8605 host bridge */
670 dev = pci_get_device(PCI_VENDOR_ID_VIA,
671 PCI_DEVICE_ID_VIA_8605_0, NULL);
672 /* Find CLE266 host bridge */
675 dev = pci_get_device(PCI_VENDOR_ID_VIA,
676 PCI_DEVICE_ID_VIA_862X_0, NULL);
677 /* Find CN400 V-Link host bridge */
679 dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
682 /* Enable access to port 0x22 */
683 pci_read_config_byte(dev, reg, &pci_cmd);
684 if (!(pci_cmd & 1<<7)) {
686 pci_write_config_byte(dev, reg, pci_cmd);
687 pci_read_config_byte(dev, reg, &pci_cmd);
688 if (!(pci_cmd & 1<<7)) {
690 "Can't enable access to port 0x22.\n");
700 static int longhaul_setup_southbridge(void)
705 /* Find VT8235 southbridge */
706 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
708 /* Find VT8237 southbridge */
709 dev = pci_get_device(PCI_VENDOR_ID_VIA,
710 PCI_DEVICE_ID_VIA_8237, NULL);
712 /* Set transition time to max */
713 pci_read_config_byte(dev, 0xec, &pci_cmd);
714 pci_cmd &= ~(1 << 2);
715 pci_write_config_byte(dev, 0xec, pci_cmd);
716 pci_read_config_byte(dev, 0xe4, &pci_cmd);
717 pci_cmd &= ~(1 << 7);
718 pci_write_config_byte(dev, 0xe4, pci_cmd);
719 pci_read_config_byte(dev, 0xe5, &pci_cmd);
721 pci_write_config_byte(dev, 0xe5, pci_cmd);
722 /* Get address of ACPI registers block*/
723 pci_read_config_byte(dev, 0x81, &pci_cmd);
724 if (pci_cmd & 1 << 7) {
725 pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
726 acpi_regs_addr &= 0xff00;
727 printk(KERN_INFO PFX "ACPI I/O at 0x%x\n", acpi_regs_addr);
736 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
738 struct cpuinfo_x86 *c = cpu_data;
743 /* Check what we have on this motherboard */
744 switch (c->x86_model) {
746 cpu_model = CPU_SAMUEL;
747 cpuname = "C3 'Samuel' [C5A]";
748 longhaul_version = TYPE_LONGHAUL_V1;
749 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
750 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
754 switch (c->x86_mask) {
756 longhaul_version = TYPE_LONGHAUL_V1;
757 cpu_model = CPU_SAMUEL2;
758 cpuname = "C3 'Samuel 2' [C5B]";
759 /* Note, this is not a typo, early Samuel2's had
761 memcpy(clock_ratio, samuel1_clock_ratio,
762 sizeof(samuel1_clock_ratio));
763 memcpy(eblcr_table, samuel2_eblcr,
764 sizeof(samuel2_eblcr));
767 longhaul_version = TYPE_LONGHAUL_V1;
768 if (c->x86_mask < 8) {
769 cpu_model = CPU_SAMUEL2;
770 cpuname = "C3 'Samuel 2' [C5B]";
772 cpu_model = CPU_EZRA;
773 cpuname = "C3 'Ezra' [C5C]";
775 memcpy(clock_ratio, ezra_clock_ratio,
776 sizeof(ezra_clock_ratio));
777 memcpy(eblcr_table, ezra_eblcr,
784 cpu_model = CPU_EZRA_T;
785 cpuname = "C3 'Ezra-T' [C5M]";
786 longhaul_version = TYPE_POWERSAVER;
788 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
789 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
793 longhaul_version = TYPE_POWERSAVER;
796 nehemiah_clock_ratio,
797 sizeof(nehemiah_clock_ratio));
798 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
799 switch (c->x86_mask) {
801 cpu_model = CPU_NEHEMIAH;
802 cpuname = "C3 'Nehemiah A' [C5XLOE]";
805 cpu_model = CPU_NEHEMIAH;
806 cpuname = "C3 'Nehemiah B' [C5XLOH]";
809 cpu_model = CPU_NEHEMIAH_C;
810 cpuname = "C3 'Nehemiah C' [C5P]";
819 /* Check Longhaul ver. 2 */
820 if (longhaul_version == TYPE_LONGHAUL_V2) {
821 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
822 if (lo == 0 && hi == 0)
823 /* Looks like MSR isn't present */
824 longhaul_version = TYPE_LONGHAUL_V1;
827 printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
828 switch (longhaul_version) {
829 case TYPE_LONGHAUL_V1:
830 case TYPE_LONGHAUL_V2:
831 printk ("Longhaul v%d supported.\n", longhaul_version);
833 case TYPE_POWERSAVER:
834 printk ("Powersaver supported.\n");
839 longhaul_setup_southbridge();
841 /* Find ACPI data for processor */
842 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
843 ACPI_UINT32_MAX, &longhaul_walk_callback,
846 /* Check ACPI support for C3 state */
847 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
848 cx = &pr->power.states[ACPI_STATE_C3];
849 if (cx->address > 0 && cx->latency <= 1000)
850 longhaul_flags |= USE_ACPI_C3;
852 /* Disable if it isn't working */
854 longhaul_flags &= ~USE_ACPI_C3;
855 /* Check if northbridge is friendly */
856 if (enable_arbiter_disable())
857 longhaul_flags |= USE_NORTHBRIDGE;
859 /* Check ACPI support for bus master arbiter disable */
860 if (!(longhaul_flags & USE_ACPI_C3
861 || longhaul_flags & USE_NORTHBRIDGE)
862 && ((pr == NULL) || !(pr->flags.bm_control))) {
864 "No ACPI support. Unsupported northbridge.\n");
868 if (longhaul_flags & USE_NORTHBRIDGE)
869 printk(KERN_INFO PFX "Using northbridge support.\n");
870 if (longhaul_flags & USE_ACPI_C3)
871 printk(KERN_INFO PFX "Using ACPI support.\n");
873 ret = longhaul_get_ranges();
877 if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
878 longhaul_setup_voltagescaling();
880 policy->cpuinfo.transition_latency = 200000; /* nsec */
881 policy->cur = calc_speed(longhaul_get_cpu_mult());
883 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
887 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
892 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
894 cpufreq_frequency_table_put_attr(policy->cpu);
898 static struct freq_attr* longhaul_attr[] = {
899 &cpufreq_freq_attr_scaling_available_freqs,
903 static struct cpufreq_driver longhaul_driver = {
904 .verify = longhaul_verify,
905 .target = longhaul_target,
907 .init = longhaul_cpu_init,
908 .exit = __devexit_p(longhaul_cpu_exit),
910 .owner = THIS_MODULE,
911 .attr = longhaul_attr,
915 static int __init longhaul_init(void)
917 struct cpuinfo_x86 *c = cpu_data;
919 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
923 if (num_online_cpus() > 1) {
924 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
928 #ifdef CONFIG_X86_IO_APIC
930 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
934 switch (c->x86_model) {
936 return cpufreq_register_driver(&longhaul_driver);
938 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
947 static void __exit longhaul_exit(void)
951 for (i=0; i < numscales; i++) {
952 if (clock_ratio[i] == maxmult) {
953 longhaul_setstate(i);
958 cpufreq_unregister_driver(&longhaul_driver);
959 kfree(longhaul_table);
962 module_param (disable_acpi_c3, int, 0644);
963 MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
965 module_param (scale_voltage, int, 0644);
966 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
968 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
969 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
970 MODULE_LICENSE ("GPL");
972 late_initcall(longhaul_init);
973 module_exit(longhaul_exit);