2 * arch/cris/arch-v32/drivers/nandflash.c
6 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/slab.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <asm/arch/memmap.h>
22 #include <hwregs/reg_map.h>
23 #include <hwregs/reg_rdwr.h>
24 #include <hwregs/pio_defs.h>
28 #define MANUAL_ALE_CLE_CONTROL 1
32 #define regf_NCE ce0_n
38 /* Bitmask for control pins */
39 #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
41 static struct mtd_info *crisv32_mtd;
43 * hardware specific access to control-lines
45 static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
50 struct nand_chip *this = mtd->priv;
52 local_irq_save(flags);
54 /* control bits change */
55 if (ctrl & NAND_CTRL_CHANGE) {
56 dout = REG_RD(pio, regi_pio, rw_dout);
57 dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
59 #if !MANUAL_ALE_CLE_CONTROL
60 if (ctrl & NAND_ALE) {
62 this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
63 regi_pio, rw_io_access1);
64 } else if (ctrl & NAND_CLE) {
66 this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
67 regi_pio, rw_io_access2);
69 /* A1 = CLE and A0 = ALE low */
70 this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
71 regi_pio, rw_io_access0);
75 dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
76 dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
78 REG_WR(pio, regi_pio, rw_dout, dout);
82 if (cmd != NAND_CMD_NONE)
83 writeb(cmd, this->IO_ADDR_W);
85 local_irq_restore(flags);
89 * read device ready pin
91 int crisv32_device_ready(struct mtd_info *mtd)
93 reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
98 * Main initialization routine
100 struct mtd_info *__init crisv32_nand_flash_probe(void)
102 void __iomem *read_cs;
103 void __iomem *write_cs;
105 struct nand_chip *this;
108 reg_pio_rw_man_ctrl man_ctrl = {
109 .regf_NCE = regk_pio_yes,
110 #if MANUAL_ALE_CLE_CONTROL
111 .regf_ALE = regk_pio_yes,
112 .regf_CLE = regk_pio_yes
116 .regf_NCE = regk_pio_yes,
117 #if MANUAL_ALE_CLE_CONTROL
118 .regf_ALE = regk_pio_yes,
119 .regf_CLE = regk_pio_yes
122 reg_pio_rw_dout dout = { .regf_NCE = 1 };
124 /* Allocate pio pins to pio */
125 crisv32_pinmux_alloc_fixed(pinmux_pio);
126 /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
127 REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
128 REG_WR(pio, regi_pio, rw_dout, dout);
129 REG_WR(pio, regi_pio, rw_oe, oe);
131 /* Allocate memory for MTD device structure and private data */
132 crisv32_mtd = kmalloc(sizeof(struct mtd_info) +
133 sizeof(struct nand_chip), GFP_KERNEL);
135 printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
136 "device structure.\n");
141 read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
144 /* Get pointer to private data */
145 this = (struct nand_chip *) (&crisv32_mtd[1]);
147 /* Initialize structures */
148 memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
149 memset((char *) this, 0, sizeof(struct nand_chip));
151 /* Link the private data with the MTD structure */
152 crisv32_mtd->priv = this;
154 /* Set address of NAND IO lines */
155 this->IO_ADDR_R = read_cs;
156 this->IO_ADDR_W = write_cs;
157 this->cmd_ctrl = crisv32_hwcontrol;
158 this->dev_ready = crisv32_device_ready;
159 /* 20 us command delay time */
160 this->chip_delay = 20;
161 this->ecc.mode = NAND_ECC_SOFT;
163 /* Enable the following for a flash based bad block table */
164 /* this->options = NAND_USE_FLASH_BBT; */
166 /* Scan to find existance of the device */
167 if (nand_scan(crisv32_mtd, 1)) {