2 * Etrax general port I/O device
4 * Copyright (c) 1999-2007 Axis Communications AB
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G)
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/ioport.h>
16 #include <linux/errno.h>
17 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/poll.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <asm/etraxgpio.h>
25 #include <asm/arch/svinto.h>
27 #include <asm/system.h>
29 #include <asm/arch/io_interface_mux.h>
31 #define GPIO_MAJOR 120 /* experimental MAJOR number */
37 #define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
42 static char gpio_name[] = "etrax gpio";
45 static wait_queue_head_t *gpio_wq;
48 static int gpio_ioctl(struct inode *inode, struct file *file,
49 unsigned int cmd, unsigned long arg);
50 static ssize_t gpio_write(struct file *file, const char __user *buf,
51 size_t count, loff_t *off);
52 static int gpio_open(struct inode *inode, struct file *filp);
53 static int gpio_release(struct inode *inode, struct file *filp);
54 static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
56 /* private data per open() of this driver */
59 struct gpio_private *next;
60 /* These fields are for PA and PB only */
61 volatile unsigned char *port, *shadow;
62 volatile unsigned char *dir, *dir_shadow;
63 unsigned char changeable_dir;
64 unsigned char changeable_bits;
65 unsigned char clk_mask;
66 unsigned char data_mask;
67 unsigned char write_msb;
68 unsigned char pad1, pad2, pad3;
69 /* These fields are generic */
70 unsigned long highalarm, lowalarm;
71 wait_queue_head_t alarm_wq;
75 /* linked list of alarms to check for */
77 static struct gpio_private *alarmlist;
79 static int gpio_some_alarms; /* Set if someone uses alarm */
80 static unsigned long gpio_pa_irq_enabled_mask;
82 static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
84 /* Port A and B use 8 bit access, but Port G is 32 bit */
85 #define NUM_PORTS (GPIO_MINOR_B+1)
87 static volatile unsigned char *ports[NUM_PORTS] = {
91 static volatile unsigned char *shads[NUM_PORTS] = {
96 /* What direction bits that are user changeable 1=changeable*/
97 #ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
98 #define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00
100 #ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR
101 #define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00
104 #ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS
105 #define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF
107 #ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS
108 #define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF
112 static unsigned char changeable_dir[NUM_PORTS] = {
113 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
114 CONFIG_ETRAX_PB_CHANGEABLE_DIR
116 static unsigned char changeable_bits[NUM_PORTS] = {
117 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
118 CONFIG_ETRAX_PB_CHANGEABLE_BITS
121 static volatile unsigned char *dir[NUM_PORTS] = {
126 static volatile unsigned char *dir_shadow[NUM_PORTS] = {
131 /* All bits in port g that can change dir. */
132 static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
134 /* Port G is 32 bit, handle it special, some bits are both inputs
135 and outputs at the same time, only some of the bits can change direction
136 and some of them in groups of 8 bit. */
137 static unsigned long changeable_dir_g;
138 static unsigned long dir_g_in_bits;
139 static unsigned long dir_g_out_bits;
140 static unsigned long dir_g_shadow; /* 1=output */
142 #define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
145 static unsigned int gpio_poll(struct file *file, poll_table *wait)
147 unsigned int mask = 0;
148 struct gpio_private *priv = file->private_data;
152 spin_lock_irqsave(&gpio_lock, flags);
154 poll_wait(file, &priv->alarm_wq, wait);
155 if (priv->minor == GPIO_MINOR_A) {
157 data = *R_PORT_PA_DATA;
158 /* PA has support for high level interrupt -
159 * lets activate for those low and with highalarm set
161 tmp = ~data & priv->highalarm & 0xFF;
162 tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
164 gpio_pa_irq_enabled_mask |= tmp;
165 *R_IRQ_MASK1_SET = tmp;
166 } else if (priv->minor == GPIO_MINOR_B)
167 data = *R_PORT_PB_DATA;
168 else if (priv->minor == GPIO_MINOR_G)
169 data = *R_PORT_G_DATA;
175 if ((data & priv->highalarm) ||
176 (~data & priv->lowalarm)) {
177 mask = POLLIN|POLLRDNORM;
181 spin_unlock_irqrestore(&gpio_lock, flags);
182 DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
187 int etrax_gpio_wake_up_check(void)
189 struct gpio_private *priv;
190 unsigned long data = 0;
194 spin_lock_irqsave(&gpio_lock, flags);
199 else if (priv->minor == GPIO_MINOR_G)
200 data = *R_PORT_G_DATA;
202 if ((data & priv->highalarm) ||
203 (~data & priv->lowalarm)) {
204 DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
205 wake_up_interruptible(&priv->alarm_wq);
210 spin_unlock_irqrestore(&gpio_lock, flags);
215 gpio_poll_timer_interrupt(int irq, void *dev_id)
217 if (gpio_some_alarms) {
218 etrax_gpio_wake_up_check();
225 gpio_interrupt(int irq, void *dev_id)
230 spin_lock_irqsave(&gpio_lock, flags);
232 /* Find what PA interrupts are active */
233 tmp = (*R_IRQ_READ1);
235 /* Find those that we have enabled */
236 tmp &= gpio_pa_irq_enabled_mask;
239 *R_IRQ_MASK1_CLR = tmp;
240 gpio_pa_irq_enabled_mask &= ~tmp;
242 spin_unlock_irqrestore(&gpio_lock, flags);
244 if (gpio_some_alarms)
245 return IRQ_RETVAL(etrax_gpio_wake_up_check());
250 static void gpio_write_bit(struct gpio_private *priv,
251 unsigned char data, int bit)
253 *priv->port = *priv->shadow &= ~(priv->clk_mask);
255 *priv->port = *priv->shadow |= priv->data_mask;
257 *priv->port = *priv->shadow &= ~(priv->data_mask);
259 /* For FPGA: min 5.0ns (DCC) before CCLK high */
260 *priv->port = *priv->shadow |= priv->clk_mask;
263 static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
268 for (i = 7; i >= 0; i--)
269 gpio_write_bit(priv, data, i);
271 for (i = 0; i <= 7; i++)
272 gpio_write_bit(priv, data, i);
275 static ssize_t gpio_write(struct file *file, const char __user *buf,
276 size_t count, loff_t *off)
278 struct gpio_private *priv = file->private_data;
280 ssize_t retval = count;
282 if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
285 if (!access_ok(VERIFY_READ, buf, count))
288 spin_lock_irqsave(&gpio_lock, flags);
290 /* It must have been configured using the IO_CFG_WRITE_MODE */
291 /* Perhaps a better error code? */
292 if (priv->clk_mask == 0 || priv->data_mask == 0) {
297 D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
298 "clk 0x%02X msb: %i\n",
299 count, priv->data_mask, priv->clk_mask, priv->write_msb));
302 gpio_write_byte(priv, *buf++);
305 spin_unlock_irqrestore(&gpio_lock, flags);
312 gpio_open(struct inode *inode, struct file *filp)
314 struct gpio_private *priv;
315 int p = iminor(inode);
318 if (p > GPIO_MINOR_LAST)
321 priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
328 /* initialize the io/alarm struct */
330 if (USE_PORTS(priv)) { /* A and B */
331 priv->port = ports[p];
332 priv->shadow = shads[p];
334 priv->dir_shadow = dir_shadow[p];
335 priv->changeable_dir = changeable_dir[p];
336 priv->changeable_bits = changeable_bits[p];
341 priv->dir_shadow = NULL;
342 priv->changeable_dir = 0;
343 priv->changeable_bits = 0;
350 init_waitqueue_head(&priv->alarm_wq);
352 filp->private_data = priv;
354 /* link it into our alarmlist */
355 spin_lock_irqsave(&gpio_lock, flags);
356 priv->next = alarmlist;
358 spin_unlock_irqrestore(&gpio_lock, flags);
364 gpio_release(struct inode *inode, struct file *filp)
366 struct gpio_private *p;
367 struct gpio_private *todel;
370 spin_lock_irqsave(&gpio_lock, flags);
373 todel = filp->private_data;
375 /* unlink from alarmlist and free the private structure */
378 alarmlist = todel->next;
380 while (p->next != todel)
382 p->next = todel->next;
386 /* Check if there are still any alarms set */
389 if (p->highalarm | p->lowalarm) {
390 gpio_some_alarms = 1;
395 gpio_some_alarms = 0;
397 spin_unlock_irqrestore(&gpio_lock, flags);
401 /* Main device API. ioctl's to read/set/clear bits, as well as to
402 * set alarms to wait for using a subsequent select().
404 unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
406 /* Set direction 0=unchanged 1=input,
407 * return mask with 1=input */
408 if (USE_PORTS(priv)) {
409 *priv->dir = *priv->dir_shadow &=
410 ~((unsigned char)arg & priv->changeable_dir);
411 return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
414 if (priv->minor != GPIO_MINOR_G)
417 /* We must fiddle with R_GEN_CONFIG to change dir */
418 if (((arg & dir_g_in_bits) != arg) &&
419 (arg & changeable_dir_g)) {
420 arg &= changeable_dir_g;
421 /* Clear bits in genconfig to set to input */
423 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
424 dir_g_in_bits |= (1<<0);
425 dir_g_out_bits &= ~(1<<0);
427 if ((arg & 0x0000FF00) == 0x0000FF00) {
428 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
429 dir_g_in_bits |= 0x0000FF00;
430 dir_g_out_bits &= ~0x0000FF00;
432 if ((arg & 0x00FF0000) == 0x00FF0000) {
433 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
434 dir_g_in_bits |= 0x00FF0000;
435 dir_g_out_bits &= ~0x00FF0000;
438 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
439 dir_g_in_bits |= (1<<24);
440 dir_g_out_bits &= ~(1<<24);
442 D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
443 "genconfig to 0x%08lX "
445 "out_bits: 0x%08lX\n",
446 (unsigned long)genconfig_shadow,
447 dir_g_in_bits, dir_g_out_bits));
448 *R_GEN_CONFIG = genconfig_shadow;
449 /* Must be a >120 ns delay before writing this again */
452 return dir_g_in_bits;
455 unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
457 if (USE_PORTS(priv)) {
458 *priv->dir = *priv->dir_shadow |=
459 ((unsigned char)arg & priv->changeable_dir);
460 return *priv->dir_shadow;
462 if (priv->minor != GPIO_MINOR_G)
465 /* We must fiddle with R_GEN_CONFIG to change dir */
466 if (((arg & dir_g_out_bits) != arg) &&
467 (arg & changeable_dir_g)) {
468 /* Set bits in genconfig to set to output */
470 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
471 dir_g_out_bits |= (1<<0);
472 dir_g_in_bits &= ~(1<<0);
474 if ((arg & 0x0000FF00) == 0x0000FF00) {
475 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
476 dir_g_out_bits |= 0x0000FF00;
477 dir_g_in_bits &= ~0x0000FF00;
479 if ((arg & 0x00FF0000) == 0x00FF0000) {
480 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
481 dir_g_out_bits |= 0x00FF0000;
482 dir_g_in_bits &= ~0x00FF0000;
485 genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
486 dir_g_out_bits |= (1<<24);
487 dir_g_in_bits &= ~(1<<24);
489 D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
490 "genconfig to 0x%08lX "
492 "out_bits: 0x%08lX\n",
493 (unsigned long)genconfig_shadow,
494 dir_g_in_bits, dir_g_out_bits));
495 *R_GEN_CONFIG = genconfig_shadow;
496 /* Must be a >120 ns delay before writing this again */
498 return dir_g_out_bits & 0x7FFFFFFF;
499 } /* setget_output */
502 gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
505 gpio_ioctl(struct inode *inode, struct file *file,
506 unsigned int cmd, unsigned long arg)
512 struct gpio_private *priv = file->private_data;
513 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
516 spin_lock_irqsave(&gpio_lock, flags);
518 switch (_IOC_NR(cmd)) {
519 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
521 if (USE_PORTS(priv)) {
523 } else if (priv->minor == GPIO_MINOR_G) {
524 ret = (*R_PORT_G_DATA) & 0x7FFFFFFF;
528 // set changeable bits with a 1 in arg
529 if (USE_PORTS(priv)) {
530 *priv->port = *priv->shadow |=
531 ((unsigned char)arg & priv->changeable_bits);
532 } else if (priv->minor == GPIO_MINOR_G) {
533 *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
537 // clear changeable bits with a 1 in arg
538 if (USE_PORTS(priv)) {
539 *priv->port = *priv->shadow &=
540 ~((unsigned char)arg & priv->changeable_bits);
541 } else if (priv->minor == GPIO_MINOR_G) {
542 *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
546 // set alarm when bits with 1 in arg go high
547 priv->highalarm |= arg;
548 gpio_some_alarms = 1;
551 // set alarm when bits with 1 in arg go low
552 priv->lowalarm |= arg;
553 gpio_some_alarms = 1;
556 // clear alarm for bits with 1 in arg
557 priv->highalarm &= ~arg;
558 priv->lowalarm &= ~arg;
560 /* Must update gpio_some_alarms */
561 struct gpio_private *p = alarmlist;
563 spin_lock_irq(&gpio_lock);
567 if (p->highalarm | p->lowalarm) {
573 gpio_some_alarms = some_alarms;
574 spin_unlock_irq(&gpio_lock);
577 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
578 /* Read direction 0=input 1=output */
579 if (USE_PORTS(priv)) {
580 ret = *priv->dir_shadow;
581 } else if (priv->minor == GPIO_MINOR_G) {
582 /* Note: Some bits are both in and out,
583 * Those that are dual is set here as well.
585 ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
588 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
589 /* Set direction 0=unchanged 1=input,
590 * return mask with 1=input
592 ret = setget_input(priv, arg) & 0x7FFFFFFF;
594 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
595 /* Set direction 0=unchanged 1=output,
596 * return mask with 1=output
598 ret = setget_output(priv, arg) & 0x7FFFFFFF;
604 #if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
605 ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
610 case IO_CFG_WRITE_MODE:
611 priv->clk_mask = arg & 0xFF;
612 priv->data_mask = (arg >> 8) & 0xFF;
613 priv->write_msb = (arg >> 16) & 0x01;
614 /* Check if we're allowed to change the bits and
615 * the direction is correct
617 if (!((priv->clk_mask & priv->changeable_bits) &&
618 (priv->data_mask & priv->changeable_bits) &&
619 (priv->clk_mask & *priv->dir_shadow) &&
620 (priv->data_mask & *priv->dir_shadow)))
628 /* *arg is result of reading the input pins */
629 if (USE_PORTS(priv)) {
631 } else if (priv->minor == GPIO_MINOR_G) {
632 val = *R_PORT_G_DATA;
634 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
637 case IO_READ_OUTBITS:
638 /* *arg is result of reading the output shadow */
639 if (USE_PORTS(priv)) {
641 } else if (priv->minor == GPIO_MINOR_G) {
642 val = port_g_data_shadow;
644 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
647 case IO_SETGET_INPUT:
648 /* bits set in *arg is set to input,
649 * *arg updated with current input pins.
651 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
656 val = setget_input(priv, val);
657 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
660 case IO_SETGET_OUTPUT:
661 /* bits set in *arg is set to output,
662 * *arg updated with current output pins.
664 if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
668 val = setget_output(priv, val);
669 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
673 if (priv->minor == GPIO_MINOR_LEDS)
674 ret = gpio_leds_ioctl(cmd, arg);
679 spin_unlock_irqrestore(&gpio_lock, flags);
684 gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
689 switch (_IOC_NR(cmd)) {
690 case IO_LEDACTIVE_SET:
691 green = ((unsigned char)arg) & 1;
692 red = (((unsigned char)arg) >> 1) & 1;
693 CRIS_LED_ACTIVE_SET_G(green);
694 CRIS_LED_ACTIVE_SET_R(red);
698 CRIS_LED_BIT_SET(arg);
702 CRIS_LED_BIT_CLR(arg);
712 static const struct file_operations gpio_fops = {
713 .owner = THIS_MODULE,
718 .release = gpio_release,
721 static void ioif_watcher(const unsigned int gpio_in_available,
722 const unsigned int gpio_out_available,
723 const unsigned char pa_available,
724 const unsigned char pb_available)
726 unsigned long int flags;
728 D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
729 D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
730 "PA: 0x%02x PB: 0x%02x\n",
731 gpio_in_available, gpio_out_available,
732 pa_available, pb_available));
734 spin_lock_irqsave(&gpio_lock, flags);
736 dir_g_in_bits = gpio_in_available;
737 dir_g_out_bits = gpio_out_available;
739 /* Initialise the dir_g_shadow etc. depending on genconfig */
740 /* 0=input 1=output */
741 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
742 dir_g_shadow |= (1 << 0);
743 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
744 dir_g_shadow |= 0x0000FF00;
745 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
746 dir_g_shadow |= 0x00FF0000;
747 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
748 dir_g_shadow |= (1 << 24);
750 changeable_dir_g = changeable_dir_g_mask;
751 changeable_dir_g &= dir_g_out_bits;
752 changeable_dir_g &= dir_g_in_bits;
754 /* Correct the bits that can change direction */
755 dir_g_out_bits &= ~changeable_dir_g;
756 dir_g_out_bits |= dir_g_shadow;
757 dir_g_in_bits &= ~changeable_dir_g;
758 dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
760 spin_unlock_irqrestore(&gpio_lock, flags);
762 printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
764 dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
765 printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
766 dir_g_shadow, changeable_dir_g);
769 /* main driver initialization routine, called from mem.c */
771 static int __init gpio_init(void)
774 #if defined (CONFIG_ETRAX_CSP0_LEDS)
778 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
780 printk(KERN_ERR "gpio: couldn't get a major number.\n");
785 #if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
786 CRIS_LED_NETWORK_SET(0);
787 CRIS_LED_ACTIVE_SET(0);
788 CRIS_LED_DISK_READ(0);
789 CRIS_LED_DISK_WRITE(0);
791 #if defined (CONFIG_ETRAX_CSP0_LEDS)
792 for (i = 0; i < 32; i++)
797 /* The I/O interface allocation watcher will be called when
799 if (cris_io_interface_register_watcher(ioif_watcher)){
800 printk(KERN_WARNING "gpio_init: Failed to install IO "
801 "if allocator watcher\n");
804 printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
805 "Axis Communications AB\n");
806 /* We call etrax_gpio_wake_up_check() from timer interrupt and
807 * from cpu_idle() in kernel/process.c
808 * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
811 res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
812 IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name);
814 printk(KERN_CRIT "err: timer0 irq for gpio\n");
817 res = request_irq(PA_IRQ_NBR, gpio_interrupt,
818 IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name);
820 printk(KERN_CRIT "err: PA irq for gpio\n");
825 /* this makes sure that gpio_init is called during kernel boot */
826 module_init(gpio_init);