2 * File: arch/blackfin/mach-common/ints-priority.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
49 # define BF537_GENERIC_ERROR_INT_DEMUX
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
67 unsigned long irq_flags = 0x1f;
68 EXPORT_SYMBOL(irq_flags);
70 /* The number of spurious interrupts */
71 atomic_t num_spurious;
74 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
79 /* irq number for request_irq, available in mach-bf5xx/irq.h */
81 /* corresponding bit in the SIC_ISR register */
83 } ivg_table[NR_PERI_INTS];
86 /* position of first irq in ivg_table for given ivg */
89 } ivg7_13[IVG13 - IVG7 + 1];
93 * Search SIC_IAR and fill tables with the irqvalues
94 * and their positions in the SIC_ISR register.
96 static void __init search_IAR(void)
98 unsigned ivg, irq_pos = 0;
99 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
102 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
104 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
105 int iar_shift = (irqn & 7) * 4;
107 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
108 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
109 bfin_read32((unsigned long *)SIC_IAR0 +
110 ((irqn % 32) >> 3) + ((irqn / 32) *
111 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
113 bfin_read32((unsigned long *)SIC_IAR0 +
114 (irqn >> 3)) >> iar_shift)) {
116 ivg_table[irq_pos].irqno = IVG7 + irqn;
117 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
118 ivg7_13[ivg].istop++;
126 * This is for core internal IRQs
129 static void bfin_ack_noop(unsigned int irq)
131 /* Dummy function. */
134 static void bfin_core_mask_irq(unsigned int irq)
136 irq_flags &= ~(1 << irq);
137 if (!irqs_disabled())
141 static void bfin_core_unmask_irq(unsigned int irq)
143 irq_flags |= 1 << irq;
145 * If interrupts are enabled, IMASK must contain the same value
146 * as irq_flags. Make sure that invariant holds. If interrupts
147 * are currently disabled we need not do anything; one of the
148 * callers will take care of setting IMASK to the proper value
149 * when reenabling interrupts.
150 * local_irq_enable just does "STI irq_flags", so it's exactly
153 if (!irqs_disabled())
158 static void bfin_internal_mask_irq(unsigned int irq)
161 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
162 ~(1 << SIC_SYSIRQ(irq)));
164 unsigned mask_bank, mask_bit;
165 mask_bank = SIC_SYSIRQ(irq) / 32;
166 mask_bit = SIC_SYSIRQ(irq) % 32;
167 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
173 static void bfin_internal_unmask_irq(unsigned int irq)
176 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
177 (1 << SIC_SYSIRQ(irq)));
179 unsigned mask_bank, mask_bit;
180 mask_bank = SIC_SYSIRQ(irq) / 32;
181 mask_bit = SIC_SYSIRQ(irq) % 32;
182 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
189 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
191 unsigned bank, bit, wakeup = 0;
193 bank = SIC_SYSIRQ(irq) / 32;
194 bit = SIC_SYSIRQ(irq) % 32;
231 local_irq_save(flags);
234 bfin_sic_iwr[bank] |= (1 << bit);
238 bfin_sic_iwr[bank] &= ~(1 << bit);
239 vr_wakeup &= ~wakeup;
242 local_irq_restore(flags);
248 static struct irq_chip bfin_core_irqchip = {
250 .ack = bfin_ack_noop,
251 .mask = bfin_core_mask_irq,
252 .unmask = bfin_core_unmask_irq,
255 static struct irq_chip bfin_internal_irqchip = {
257 .ack = bfin_ack_noop,
258 .mask = bfin_internal_mask_irq,
259 .unmask = bfin_internal_unmask_irq,
260 .mask_ack = bfin_internal_mask_irq,
261 .disable = bfin_internal_mask_irq,
262 .enable = bfin_internal_unmask_irq,
264 .set_wake = bfin_internal_set_wake,
268 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
269 static int error_int_mask;
271 static void bfin_generic_error_mask_irq(unsigned int irq)
273 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
276 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
279 static void bfin_generic_error_unmask_irq(unsigned int irq)
281 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
282 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
285 static struct irq_chip bfin_generic_error_irqchip = {
287 .ack = bfin_ack_noop,
288 .mask_ack = bfin_generic_error_mask_irq,
289 .mask = bfin_generic_error_mask_irq,
290 .unmask = bfin_generic_error_unmask_irq,
293 static void bfin_demux_error_irq(unsigned int int_err_irq,
294 struct irq_desc *inta_desc)
300 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
301 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
305 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
306 irq = IRQ_SPORT0_ERROR;
307 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
308 irq = IRQ_SPORT1_ERROR;
309 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
311 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
313 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
315 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
316 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
317 irq = IRQ_UART0_ERROR;
318 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
319 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
320 irq = IRQ_UART1_ERROR;
323 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
324 struct irq_desc *desc = irq_desc + irq;
325 desc->handle_irq(irq, desc);
330 bfin_write_PPI_STATUS(PPI_ERR_MASK);
332 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
334 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
337 case IRQ_SPORT0_ERROR:
338 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
341 case IRQ_SPORT1_ERROR:
342 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
346 bfin_write_CAN_GIS(CAN_ERR_MASK);
350 bfin_write_SPI_STAT(SPI_ERR_MASK);
358 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
363 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
364 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
365 __func__, __FILE__, __LINE__);
368 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
370 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
372 struct irq_desc *desc = irq_desc + irq;
373 /* May not call generic set_irq_handler() due to spinlock
375 desc->handle_irq = handle;
378 #if !defined(CONFIG_BF54x)
380 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
381 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
383 extern void bfin_gpio_irq_prepare(unsigned gpio);
385 static void bfin_gpio_ack_irq(unsigned int irq)
387 u16 gpionr = irq - IRQ_PF0;
389 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
390 set_gpio_data(gpionr, 0);
395 static void bfin_gpio_mask_ack_irq(unsigned int irq)
397 u16 gpionr = irq - IRQ_PF0;
399 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
400 set_gpio_data(gpionr, 0);
404 set_gpio_maska(gpionr, 0);
408 static void bfin_gpio_mask_irq(unsigned int irq)
410 set_gpio_maska(irq - IRQ_PF0, 0);
414 static void bfin_gpio_unmask_irq(unsigned int irq)
416 set_gpio_maska(irq - IRQ_PF0, 1);
420 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
422 u16 gpionr = irq - IRQ_PF0;
424 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
425 bfin_gpio_irq_prepare(gpionr);
427 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
428 bfin_gpio_unmask_irq(irq);
433 static void bfin_gpio_irq_shutdown(unsigned int irq)
435 bfin_gpio_mask_irq(irq);
436 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
439 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
441 u16 gpionr = irq - IRQ_PF0;
443 if (type == IRQ_TYPE_PROBE) {
444 /* only probe unenabled GPIO interrupt lines */
445 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
447 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
450 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
451 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
452 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
453 bfin_gpio_irq_prepare(gpionr);
455 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
457 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
461 set_gpio_inen(gpionr, 0);
462 set_gpio_dir(gpionr, 0);
464 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
465 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
466 set_gpio_both(gpionr, 1);
468 set_gpio_both(gpionr, 0);
470 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
471 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
473 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
475 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
476 set_gpio_edge(gpionr, 1);
477 set_gpio_inen(gpionr, 1);
478 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
479 set_gpio_data(gpionr, 0);
482 set_gpio_edge(gpionr, 0);
483 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
484 set_gpio_inen(gpionr, 1);
489 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
490 bfin_set_irq_handler(irq, handle_edge_irq);
492 bfin_set_irq_handler(irq, handle_level_irq);
498 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
500 unsigned gpio = irq_to_gpio(irq);
503 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
505 gpio_pm_wakeup_free(gpio);
511 static struct irq_chip bfin_gpio_irqchip = {
513 .ack = bfin_gpio_ack_irq,
514 .mask = bfin_gpio_mask_irq,
515 .mask_ack = bfin_gpio_mask_ack_irq,
516 .unmask = bfin_gpio_unmask_irq,
517 .disable = bfin_gpio_mask_irq,
518 .enable = bfin_gpio_unmask_irq,
519 .set_type = bfin_gpio_irq_type,
520 .startup = bfin_gpio_irq_startup,
521 .shutdown = bfin_gpio_irq_shutdown,
523 .set_wake = bfin_gpio_set_wake,
527 static void bfin_demux_gpio_irq(unsigned int inta_irq,
528 struct irq_desc *desc)
530 unsigned int i, gpio, mask, irq, search = 0;
533 #if defined(CONFIG_BF53x)
538 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
543 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
547 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
557 #elif defined(CONFIG_BF561)
574 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
577 mask = get_gpiop_data(i) &
578 (gpio_enabled[gpio_bank(i)] &
583 desc = irq_desc + irq;
584 desc->handle_irq(irq, desc);
591 gpio = irq_to_gpio(irq);
592 mask = get_gpiop_data(gpio) &
593 (gpio_enabled[gpio_bank(gpio)] &
594 get_gpiop_maska(gpio));
598 desc = irq_desc + irq;
599 desc->handle_irq(irq, desc);
608 #else /* CONFIG_BF54x */
610 #define NR_PINT_SYS_IRQS 4
611 #define NR_PINT_BITS 32
613 #define IRQ_NOT_AVAIL 0xFF
615 #define PINT_2_BANK(x) ((x) >> 5)
616 #define PINT_2_BIT(x) ((x) & 0x1F)
617 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
619 static unsigned char irq2pint_lut[NR_PINTS];
620 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
622 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
623 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
627 unsigned int mask_set;
628 unsigned int mask_clear;
629 unsigned int request;
631 unsigned int edge_set;
632 unsigned int edge_clear;
633 unsigned int invert_set;
634 unsigned int invert_clear;
635 unsigned int pinstate;
639 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
640 (struct pin_int_t *)PINT0_MASK_SET,
641 (struct pin_int_t *)PINT1_MASK_SET,
642 (struct pin_int_t *)PINT2_MASK_SET,
643 (struct pin_int_t *)PINT3_MASK_SET,
646 extern void bfin_gpio_irq_prepare(unsigned gpio);
648 inline unsigned short get_irq_base(u8 bank, u8 bmap)
653 if (bank < 2) { /*PA-PB */
654 irq_base = IRQ_PA0 + bmap * 16;
656 irq_base = IRQ_PC0 + bmap * 16;
663 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
664 void init_pint_lut(void)
666 u16 bank, bit, irq_base, bit_pos;
670 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
672 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
674 pint_assign = pint[bank]->assign;
676 for (bit = 0; bit < NR_PINT_BITS; bit++) {
678 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
680 irq_base = get_irq_base(bank, bmap);
682 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
683 bit_pos = bit + bank * NR_PINT_BITS;
685 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
686 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
694 static void bfin_gpio_ack_irq(unsigned int irq)
696 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
697 u32 pintbit = PINT_BIT(pint_val);
698 u8 bank = PINT_2_BANK(pint_val);
700 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
701 if (pint[bank]->invert_set & pintbit)
702 pint[bank]->invert_clear = pintbit;
704 pint[bank]->invert_set = pintbit;
706 pint[bank]->request = pintbit;
711 static void bfin_gpio_mask_ack_irq(unsigned int irq)
713 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
714 u32 pintbit = PINT_BIT(pint_val);
715 u8 bank = PINT_2_BANK(pint_val);
717 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
718 if (pint[bank]->invert_set & pintbit)
719 pint[bank]->invert_clear = pintbit;
721 pint[bank]->invert_set = pintbit;
724 pint[bank]->request = pintbit;
725 pint[bank]->mask_clear = pintbit;
729 static void bfin_gpio_mask_irq(unsigned int irq)
731 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
733 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
737 static void bfin_gpio_unmask_irq(unsigned int irq)
739 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
740 u32 pintbit = PINT_BIT(pint_val);
741 u8 bank = PINT_2_BANK(pint_val);
743 pint[bank]->request = pintbit;
744 pint[bank]->mask_set = pintbit;
748 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
750 u16 gpionr = irq_to_gpio(irq);
751 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
753 if (pint_val == IRQ_NOT_AVAIL) {
755 "GPIO IRQ %d :Not in PINT Assign table "
756 "Reconfigure Interrupt to Port Assignemt\n", irq);
760 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
761 bfin_gpio_irq_prepare(gpionr);
763 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
764 bfin_gpio_unmask_irq(irq);
769 static void bfin_gpio_irq_shutdown(unsigned int irq)
771 u16 gpionr = irq_to_gpio(irq);
773 bfin_gpio_mask_irq(irq);
774 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
777 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
780 u16 gpionr = irq_to_gpio(irq);
781 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
782 u32 pintbit = PINT_BIT(pint_val);
783 u8 bank = PINT_2_BANK(pint_val);
785 if (pint_val == IRQ_NOT_AVAIL)
788 if (type == IRQ_TYPE_PROBE) {
789 /* only probe unenabled GPIO interrupt lines */
790 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
792 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
795 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
796 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
797 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
798 bfin_gpio_irq_prepare(gpionr);
800 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
802 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
806 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
807 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
809 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
811 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
812 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
814 gpio_both_edge_triggered[bank] |= pintbit;
816 if (gpio_get_value(gpionr))
817 pint[bank]->invert_set = pintbit;
819 pint[bank]->invert_clear = pintbit;
821 gpio_both_edge_triggered[bank] &= ~pintbit;
824 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
825 pint[bank]->edge_set = pintbit;
826 bfin_set_irq_handler(irq, handle_edge_irq);
828 pint[bank]->edge_clear = pintbit;
829 bfin_set_irq_handler(irq, handle_level_irq);
838 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
839 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
841 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
844 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
845 u32 bank = PINT_2_BANK(pint_val);
846 u32 pintbit = PINT_BIT(pint_val);
850 pint_irq = IRQ_PINT0;
853 pint_irq = IRQ_PINT2;
856 pint_irq = IRQ_PINT3;
859 pint_irq = IRQ_PINT1;
865 bfin_internal_set_wake(pint_irq, state);
868 pint_wakeup_masks[bank] |= pintbit;
870 pint_wakeup_masks[bank] &= ~pintbit;
875 u32 bfin_pm_setup(void)
879 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
880 val = pint[i]->mask_clear;
881 pint_saved_masks[i] = val;
882 if (val ^ pint_wakeup_masks[i]) {
883 pint[i]->mask_clear = val;
884 pint[i]->mask_set = pint_wakeup_masks[i];
891 void bfin_pm_restore(void)
895 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
896 val = pint_saved_masks[i];
897 if (val ^ pint_wakeup_masks[i]) {
898 pint[i]->mask_clear = pint[i]->mask_clear;
899 pint[i]->mask_set = val;
905 static struct irq_chip bfin_gpio_irqchip = {
907 .ack = bfin_gpio_ack_irq,
908 .mask = bfin_gpio_mask_irq,
909 .mask_ack = bfin_gpio_mask_ack_irq,
910 .unmask = bfin_gpio_unmask_irq,
911 .disable = bfin_gpio_mask_irq,
912 .enable = bfin_gpio_unmask_irq,
913 .set_type = bfin_gpio_irq_type,
914 .startup = bfin_gpio_irq_startup,
915 .shutdown = bfin_gpio_irq_shutdown,
917 .set_wake = bfin_gpio_set_wake,
921 static void bfin_demux_gpio_irq(unsigned int inta_irq,
922 struct irq_desc *desc)
944 pint_val = bank * NR_PINT_BITS;
946 request = pint[bank]->request;
950 irq = pint2irq_lut[pint_val] + SYS_IRQS;
951 desc = irq_desc + irq;
952 desc->handle_irq(irq, desc);
961 void __init init_exception_vectors(void)
965 /* cannot program in software:
966 * evt0 - emulation (jtag)
969 bfin_write_EVT2(evt_nmi);
970 bfin_write_EVT3(trap);
971 bfin_write_EVT5(evt_ivhw);
972 bfin_write_EVT6(evt_timer);
973 bfin_write_EVT7(evt_evt7);
974 bfin_write_EVT8(evt_evt8);
975 bfin_write_EVT9(evt_evt9);
976 bfin_write_EVT10(evt_evt10);
977 bfin_write_EVT11(evt_evt11);
978 bfin_write_EVT12(evt_evt12);
979 bfin_write_EVT13(evt_evt13);
980 bfin_write_EVT14(evt14_softirq);
981 bfin_write_EVT15(evt_system_call);
986 * This function should be called during kernel startup to initialize
987 * the BFin IRQ handling routines.
989 int __init init_arch_irq(void)
992 unsigned long ilat = 0;
993 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
994 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
995 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
996 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
997 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
999 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1002 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1005 local_irq_disable();
1007 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1008 /* Clear EMAC Interrupt Status bits so we can demux it later */
1009 bfin_write_EMAC_SYSTAT(-1);
1013 # ifdef CONFIG_PINTx_REASSIGN
1014 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1015 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1016 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1017 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1019 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1023 for (irq = 0; irq <= SYS_IRQS; irq++) {
1024 if (irq <= IRQ_CORETMR)
1025 set_irq_chip(irq, &bfin_core_irqchip);
1027 set_irq_chip(irq, &bfin_internal_irqchip);
1030 #if defined(CONFIG_BF53x)
1032 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1035 #elif defined(CONFIG_BF54x)
1040 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1041 case IRQ_PORTF_INTA:
1042 case IRQ_PORTG_INTA:
1043 case IRQ_PORTH_INTA:
1044 #elif defined(CONFIG_BF561)
1045 case IRQ_PROG0_INTA:
1046 case IRQ_PROG1_INTA:
1047 case IRQ_PROG2_INTA:
1048 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1049 case IRQ_PORTF_INTA:
1052 set_irq_chained_handler(irq,
1053 bfin_demux_gpio_irq);
1055 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1056 case IRQ_GENERIC_ERROR:
1057 set_irq_handler(irq, bfin_demux_error_irq);
1062 set_irq_handler(irq, handle_simple_irq);
1067 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1068 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1069 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1073 /* if configured as edge, then will be changed to do_edge_IRQ */
1074 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1075 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1079 bfin_write_IMASK(0);
1081 ilat = bfin_read_ILAT();
1083 bfin_write_ILAT(ilat);
1086 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1087 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1088 * local_irq_enable()
1091 /* Therefore it's better to setup IARs before interrupts enabled */
1094 /* Enable interrupts IVG7-15 */
1095 irq_flags = irq_flags | IMASK_IVG15 |
1096 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1097 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1099 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1100 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1101 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1102 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1103 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1104 * will screw up the bootrom as it relies on MDMA0/1 waking it
1105 * up from IDLE instructions. See this report for more info:
1106 * http://blackfin.uclinux.org/gf/tracker/4323
1108 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1110 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1112 # ifdef CONFIG_BF54x
1113 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1116 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1122 #ifdef CONFIG_DO_IRQ_L1
1123 __attribute__((l1_text))
1125 void do_irq(int vec, struct pt_regs *fp)
1127 if (vec == EVT_IVTMR_P) {
1130 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1131 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1132 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1133 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1134 unsigned long sic_status[3];
1136 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1137 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1139 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1142 if (ivg >= ivg_stop) {
1143 atomic_inc(&num_spurious);
1146 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1150 unsigned long sic_status;
1152 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1155 if (ivg >= ivg_stop) {
1156 atomic_inc(&num_spurious);
1158 } else if (sic_status & ivg->isrflag)
1164 asm_do_IRQ(vec, fp);