2 * File: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: bf533 startup file
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #include <asm/trace.h>
34 #ifdef CONFIG_BFIN_KERNEL_CLOCK
35 #include <asm/mach-common/clocks.h>
36 #include <asm/mach/mem_init.h>
41 .extern _bf53x_relocate_l1_mem
43 #define INITIAL_STACK 0xFFB01000
48 /* R0: argument of command line string, passed from uboot, save it */
50 /* Enable Cycle Counter and Nesting Of Interrupts */
51 #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
54 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
59 /* Clear Out All the data and pointer Registers */
81 /* Clear Out All the DAG Registers */
97 trace_buffer_init(p0,r0);
101 p0.h = hi(FIO_MASKA_C);
102 p0.l = lo(FIO_MASKA_C);
104 w[p0] = r0.L; /* Disable all interrupts */
107 p0.h = hi(FIO_MASKB_C);
108 p0.l = lo(FIO_MASKB_C);
110 w[p0] = r0.L; /* Disable all interrupts */
113 /* Turn off the icache */
114 p0.l = LO(IMEM_CONTROL);
115 p0.h = HI(IMEM_CONTROL);
122 /* Turn off the dcache */
123 p0.l = LO(DMEM_CONTROL);
124 p0.h = HI(DMEM_CONTROL);
131 /* Initialise UART - when booting from u-boot, the UART is not disabled
132 * so if we dont initalize here, our serial console gets hosed */
133 p0.h = hi(BFIN_UART_LCR);
134 p0.l = lo(BFIN_UART_LCR);
136 w[p0] = r0.L; /* To enable DLL writes */
139 p0.h = hi(BFIN_UART_DLL);
140 p0.l = lo(BFIN_UART_DLL);
145 p0.h = hi(BFIN_UART_DLH);
146 p0.l = lo(BFIN_UART_DLH);
151 p0.h = hi(BFIN_UART_GCTL);
152 p0.l = lo(BFIN_UART_GCTL);
154 w[p0] = r0.L; /* To enable UART clock */
157 /* Initialize stack pointer */
158 sp.l = lo(INITIAL_STACK);
159 sp.h = hi(INITIAL_STACK);
163 #ifdef CONFIG_EARLY_PRINTK
165 call _init_early_exception_vectors;
169 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
170 call _bf53x_relocate_l1_mem;
171 #ifdef CONFIG_BFIN_KERNEL_CLOCK
172 call _start_dma_code;
175 /* This section keeps the processor in supervisor mode
176 * during kernel boot. Switches to user mode at end of boot.
177 * See page 3-9 of Hardware Reference manual for documentation.
180 /* EVT15 = _real_start */
212 #ifdef CONFIG_BFIN_KERNEL_CLOCK
213 ENTRY(_start_dma_code)
223 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
224 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
225 * - [7] = output delay (add 200ps of delay to mem signals)
226 * - [6] = input delay (add 200ps of input delay to mem signals)
227 * - [5] = PDWN : 1=All Clocks off
228 * - [3] = STOPCK : 1=Core Clock off
229 * - [1] = PLL_OFF : 1=Disable Power to PLL
230 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
231 * all other bits set to zero
234 p0.h = hi(PLL_LOCKCNT);
235 p0.l = lo(PLL_LOCKCNT);
240 P2.H = hi(EBIU_SDGCTL);
241 P2.L = lo(EBIU_SDGCTL);
247 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
248 r0 = r0 << 9; /* Shift it over, */
249 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
251 r1 = PLL_BYPASS; /* Bypass the PLL? */
252 r1 = r1 << 8; /* Shift it over */
253 r0 = r1 | r0; /* add them all together */
256 p0.l = lo(PLL_CTL); /* Load the address */
257 cli r2; /* Disable interrupts */
259 w[p0] = r0.l; /* Set the value */
260 idle; /* Wait for the PLL to stablize */
261 sti r2; /* Enable interrupts */
268 if ! CC jump .Lcheck_again;
270 /* Configure SCLK & CCLK Dividers */
271 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
277 p0.l = lo(EBIU_SDRRC);
278 p0.h = hi(EBIU_SDRRC);
283 P2.H = hi(EBIU_SDGCTL);
284 P2.L = lo(EBIU_SDGCTL);
287 p0.h = hi(EBIU_SDSTAT);
288 p0.l = lo(EBIU_SDSTAT);
298 R0.L = lo(mem_SDGCTL);
299 R0.H = hi(mem_SDGCTL);
307 r0.l = lo(IWR_ENABLE_ALL);
308 r0.h = hi(IWR_ENABLE_ALL);
313 ENDPROC(_start_dma_code)
314 #endif /* CONFIG_BFIN_KERNEL_CLOCK */