arch/blackfin/kernel/kgdb.c

   1 /*
   2  * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
   3  *
   4  * Copyright 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/smp.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/delay.h>
  15 #include <linux/ptrace.h>               /* for linux pt_regs struct */
  16 #include <linux/kgdb.h>
  17 #include <linux/console.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/irq.h>
  21 #include <linux/uaccess.h>
  22 #include <asm/system.h>
  23 #include <asm/traps.h>
  24 #include <asm/blackfin.h>
  25 #include <asm/dma.h>
  26
  27 /* Put the error code here just in case the user cares.  */
  28 int gdb_bfin_errcode;
  29 /* Likewise, the vector number here (since GDB only gets the signal
  30    number through the usual means, and that's not very specific).  */
  31 int gdb_bfin_vector = -1;
  32
  33 #if KGDB_MAX_NO_CPUS != 8
  34 #error change the definition of slavecpulocks
  35 #endif
  36
  37 #define IN_MEM(addr, size, l1_addr, l1_size) \
  38 ({ \
  39         unsigned long __addr = (unsigned long)(addr); \
  40         (__addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
  41 })
  42 #define ASYNC_BANK_SIZE \
  43         (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
  44          ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
  45
  46 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
  47 {
  48         gdb_regs[BFIN_R0] = regs->r0;
  49         gdb_regs[BFIN_R1] = regs->r1;
  50         gdb_regs[BFIN_R2] = regs->r2;
  51         gdb_regs[BFIN_R3] = regs->r3;
  52         gdb_regs[BFIN_R4] = regs->r4;
  53         gdb_regs[BFIN_R5] = regs->r5;
  54         gdb_regs[BFIN_R6] = regs->r6;
  55         gdb_regs[BFIN_R7] = regs->r7;
  56         gdb_regs[BFIN_P0] = regs->p0;
  57         gdb_regs[BFIN_P1] = regs->p1;
  58         gdb_regs[BFIN_P2] = regs->p2;
  59         gdb_regs[BFIN_P3] = regs->p3;
  60         gdb_regs[BFIN_P4] = regs->p4;
  61         gdb_regs[BFIN_P5] = regs->p5;
  62         gdb_regs[BFIN_SP] = regs->reserved;
  63         gdb_regs[BFIN_FP] = regs->fp;
  64         gdb_regs[BFIN_I0] = regs->i0;
  65         gdb_regs[BFIN_I1] = regs->i1;
  66         gdb_regs[BFIN_I2] = regs->i2;
  67         gdb_regs[BFIN_I3] = regs->i3;
  68         gdb_regs[BFIN_M0] = regs->m0;
  69         gdb_regs[BFIN_M1] = regs->m1;
  70         gdb_regs[BFIN_M2] = regs->m2;
  71         gdb_regs[BFIN_M3] = regs->m3;
  72         gdb_regs[BFIN_B0] = regs->b0;
  73         gdb_regs[BFIN_B1] = regs->b1;
  74         gdb_regs[BFIN_B2] = regs->b2;
  75         gdb_regs[BFIN_B3] = regs->b3;
  76         gdb_regs[BFIN_L0] = regs->l0;
  77         gdb_regs[BFIN_L1] = regs->l1;
  78         gdb_regs[BFIN_L2] = regs->l2;
  79         gdb_regs[BFIN_L3] = regs->l3;
  80         gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
  81         gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
  82         gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
  83         gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
  84         gdb_regs[BFIN_ASTAT] = regs->astat;
  85         gdb_regs[BFIN_RETS] = regs->rets;
  86         gdb_regs[BFIN_LC0] = regs->lc0;
  87         gdb_regs[BFIN_LT0] = regs->lt0;
  88         gdb_regs[BFIN_LB0] = regs->lb0;
  89         gdb_regs[BFIN_LC1] = regs->lc1;
  90         gdb_regs[BFIN_LT1] = regs->lt1;
  91         gdb_regs[BFIN_LB1] = regs->lb1;
  92         gdb_regs[BFIN_CYCLES] = 0;
  93         gdb_regs[BFIN_CYCLES2] = 0;
  94         gdb_regs[BFIN_USP] = regs->usp;
  95         gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
  96         gdb_regs[BFIN_SYSCFG] = regs->syscfg;
  97         gdb_regs[BFIN_RETI] = regs->pc;
  98         gdb_regs[BFIN_RETX] = regs->retx;
  99         gdb_regs[BFIN_RETN] = regs->retn;
 100         gdb_regs[BFIN_RETE] = regs->rete;
 101         gdb_regs[BFIN_PC] = regs->pc;
 102         gdb_regs[BFIN_CC] = 0;
 103         gdb_regs[BFIN_EXTRA1] = 0;
 104         gdb_regs[BFIN_EXTRA2] = 0;
 105         gdb_regs[BFIN_EXTRA3] = 0;
 106         gdb_regs[BFIN_IPEND] = regs->ipend;
 107 }
 108
 109 /*
 110  * Extracts ebp, esp and eip values understandable by gdb from the values
 111  * saved by switch_to.
 112  * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
 113  * prior to entering switch_to is 8 greater then the value that is saved.
 114  * If switch_to changes, change following code appropriately.
 115  */
 116 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
 117 {
 118         gdb_regs[BFIN_SP] = p->thread.ksp;
 119         gdb_regs[BFIN_PC] = p->thread.pc;
 120         gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
 121 }
 122
 123 void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 124 {
 125         regs->r0 = gdb_regs[BFIN_R0];
 126         regs->r1 = gdb_regs[BFIN_R1];
 127         regs->r2 = gdb_regs[BFIN_R2];
 128         regs->r3 = gdb_regs[BFIN_R3];
 129         regs->r4 = gdb_regs[BFIN_R4];
 130         regs->r5 = gdb_regs[BFIN_R5];
 131         regs->r6 = gdb_regs[BFIN_R6];
 132         regs->r7 = gdb_regs[BFIN_R7];
 133         regs->p0 = gdb_regs[BFIN_P0];
 134         regs->p1 = gdb_regs[BFIN_P1];
 135         regs->p2 = gdb_regs[BFIN_P2];
 136         regs->p3 = gdb_regs[BFIN_P3];
 137         regs->p4 = gdb_regs[BFIN_P4];
 138         regs->p5 = gdb_regs[BFIN_P5];
 139         regs->fp = gdb_regs[BFIN_FP];
 140         regs->i0 = gdb_regs[BFIN_I0];
 141         regs->i1 = gdb_regs[BFIN_I1];
 142         regs->i2 = gdb_regs[BFIN_I2];
 143         regs->i3 = gdb_regs[BFIN_I3];
 144         regs->m0 = gdb_regs[BFIN_M0];
 145         regs->m1 = gdb_regs[BFIN_M1];
 146         regs->m2 = gdb_regs[BFIN_M2];
 147         regs->m3 = gdb_regs[BFIN_M3];
 148         regs->b0 = gdb_regs[BFIN_B0];
 149         regs->b1 = gdb_regs[BFIN_B1];
 150         regs->b2 = gdb_regs[BFIN_B2];
 151         regs->b3 = gdb_regs[BFIN_B3];
 152         regs->l0 = gdb_regs[BFIN_L0];
 153         regs->l1 = gdb_regs[BFIN_L1];
 154         regs->l2 = gdb_regs[BFIN_L2];
 155         regs->l3 = gdb_regs[BFIN_L3];
 156         regs->a0x = gdb_regs[BFIN_A0_DOT_X];
 157         regs->a0w = gdb_regs[BFIN_A0_DOT_W];
 158         regs->a1x = gdb_regs[BFIN_A1_DOT_X];
 159         regs->a1w = gdb_regs[BFIN_A1_DOT_W];
 160         regs->rets = gdb_regs[BFIN_RETS];
 161         regs->lc0 = gdb_regs[BFIN_LC0];
 162         regs->lt0 = gdb_regs[BFIN_LT0];
 163         regs->lb0 = gdb_regs[BFIN_LB0];
 164         regs->lc1 = gdb_regs[BFIN_LC1];
 165         regs->lt1 = gdb_regs[BFIN_LT1];
 166         regs->lb1 = gdb_regs[BFIN_LB1];
 167         regs->usp = gdb_regs[BFIN_USP];
 168         regs->syscfg = gdb_regs[BFIN_SYSCFG];
 169         regs->retx = gdb_regs[BFIN_PC];
 170         regs->retn = gdb_regs[BFIN_RETN];
 171         regs->rete = gdb_regs[BFIN_RETE];
 172         regs->pc = gdb_regs[BFIN_PC];
 173
 174 #if 0                           /* can't change these */
 175         regs->astat = gdb_regs[BFIN_ASTAT];
 176         regs->seqstat = gdb_regs[BFIN_SEQSTAT];
 177         regs->ipend = gdb_regs[BFIN_IPEND];
 178 #endif
 179 }
 180
 181 struct hw_breakpoint {
 182         unsigned int occupied:1;
 183         unsigned int skip:1;
 184         unsigned int enabled:1;
 185         unsigned int type:1;
 186         unsigned int dataacc:2;
 187         unsigned short count;
 188         unsigned int addr;
 189 } breakinfo[HW_WATCHPOINT_NUM];
 190
 191 int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
 192 {
 193         int breakno;
 194         int bfin_type;
 195         int dataacc = 0;
 196
 197         switch (type) {
 198         case BP_HARDWARE_BREAKPOINT:
 199                 bfin_type = TYPE_INST_WATCHPOINT;
 200                 break;
 201         case BP_WRITE_WATCHPOINT:
 202                 dataacc = 1;
 203                 bfin_type = TYPE_DATA_WATCHPOINT;
 204                 break;
 205         case BP_READ_WATCHPOINT:
 206                 dataacc = 2;
 207                 bfin_type = TYPE_DATA_WATCHPOINT;
 208                 break;
 209         case BP_ACCESS_WATCHPOINT:
 210                 dataacc = 3;
 211                 bfin_type = TYPE_DATA_WATCHPOINT;
 212                 break;
 213         default:
 214                 return -ENOSPC;
 215         }
 216
 217         /* Becasue hardware data watchpoint impelemented in current
 218          * Blackfin can not trigger an exception event as the hardware
 219          * instrction watchpoint does, we ignaore all data watch point here.
 220          * They can be turned on easily after future blackfin design
 221          * supports this feature.
 222          */
 223         for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
 224                 if (bfin_type == breakinfo[breakno].type
 225                         && !breakinfo[breakno].occupied) {
 226                         breakinfo[breakno].occupied = 1;
 227                         breakinfo[breakno].skip = 0;
 228                         breakinfo[breakno].enabled = 1;
 229                         breakinfo[breakno].addr = addr;
 230                         breakinfo[breakno].dataacc = dataacc;
 231                         breakinfo[breakno].count = 0;
 232                         return 0;
 233                 }
 234
 235         return -ENOSPC;
 236 }
 237
 238 int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
 239 {
 240         int breakno;
 241         int bfin_type;
 242
 243         switch (type) {
 244         case BP_HARDWARE_BREAKPOINT:
 245                 bfin_type = TYPE_INST_WATCHPOINT;
 246                 break;
 247         case BP_WRITE_WATCHPOINT:
 248         case BP_READ_WATCHPOINT:
 249         case BP_ACCESS_WATCHPOINT:
 250                 bfin_type = TYPE_DATA_WATCHPOINT;
 251                 break;
 252         default:
 253                 return 0;
 254         }
 255         for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
 256                 if (bfin_type == breakinfo[breakno].type
 257                         && breakinfo[breakno].occupied
 258                         && breakinfo[breakno].addr == addr) {
 259                         breakinfo[breakno].occupied = 0;
 260                         breakinfo[breakno].enabled = 0;
 261                 }
 262
 263         return 0;
 264 }
 265
 266 void bfin_remove_all_hw_break(void)
 267 {
 268         int breakno;
 269
 270         memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
 271
 272         for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
 273                 breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
 274         for (; breakno < HW_WATCHPOINT_NUM; breakno++)
 275                 breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
 276 }
 277
 278 void bfin_correct_hw_break(void)
 279 {
 280         int breakno;
 281         unsigned int wpiactl = 0;
 282         unsigned int wpdactl = 0;
 283         int enable_wp = 0;
 284
 285         for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
 286                 if (breakinfo[breakno].enabled) {
 287                         enable_wp = 1;
 288
 289                         switch (breakno) {
 290                         case 0:
 291                                 wpiactl |= WPIAEN0|WPICNTEN0;
 292                                 bfin_write_WPIA0(breakinfo[breakno].addr);
 293                                 bfin_write_WPIACNT0(breakinfo[breakno].count
 294                                         + breakinfo->skip);
 295                                 break;
 296                         case 1:
 297                                 wpiactl |= WPIAEN1|WPICNTEN1;
 298                                 bfin_write_WPIA1(breakinfo[breakno].addr);
 299                                 bfin_write_WPIACNT1(breakinfo[breakno].count
 300                                         + breakinfo->skip);
 301                                 break;
 302                         case 2:
 303                                 wpiactl |= WPIAEN2|WPICNTEN2;
 304                                 bfin_write_WPIA2(breakinfo[breakno].addr);
 305                                 bfin_write_WPIACNT2(breakinfo[breakno].count
 306                                         + breakinfo->skip);
 307                                 break;
 308                         case 3:
 309                                 wpiactl |= WPIAEN3|WPICNTEN3;
 310                                 bfin_write_WPIA3(breakinfo[breakno].addr);
 311                                 bfin_write_WPIACNT3(breakinfo[breakno].count
 312                                         + breakinfo->skip);
 313                                 break;
 314                         case 4:
 315                                 wpiactl |= WPIAEN4|WPICNTEN4;
 316                                 bfin_write_WPIA4(breakinfo[breakno].addr);
 317                                 bfin_write_WPIACNT4(breakinfo[breakno].count
 318                                         + breakinfo->skip);
 319                                 break;
 320                         case 5:
 321                                 wpiactl |= WPIAEN5|WPICNTEN5;
 322                                 bfin_write_WPIA5(breakinfo[breakno].addr);
 323                                 bfin_write_WPIACNT5(breakinfo[breakno].count
 324                                         + breakinfo->skip);
 325                                 break;
 326                         case 6:
 327                                 wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
 328                                 wpdactl |= breakinfo[breakno].dataacc
 329                                         << WPDACC0_OFFSET;
 330                                 bfin_write_WPDA0(breakinfo[breakno].addr);
 331                                 bfin_write_WPDACNT0(breakinfo[breakno].count
 332                                         + breakinfo->skip);
 333                                 break;
 334                         case 7:
 335                                 wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
 336                                 wpdactl |= breakinfo[breakno].dataacc
 337                                         << WPDACC1_OFFSET;
 338                                 bfin_write_WPDA1(breakinfo[breakno].addr);
 339                                 bfin_write_WPDACNT1(breakinfo[breakno].count
 340                                         + breakinfo->skip);
 341                                 break;
 342                         }
 343                 }
 344
 345         /* Should enable WPPWR bit first before set any other
 346          * WPIACTL and WPDACTL bits */
 347         if (enable_wp) {
 348                 bfin_write_WPIACTL(WPPWR);
 349                 CSYNC();
 350                 bfin_write_WPIACTL(wpiactl|WPPWR);
 351                 bfin_write_WPDACTL(wpdactl);
 352                 CSYNC();
 353         }
 354 }
 355
 356 void kgdb_disable_hw_debug(struct pt_regs *regs)
 357 {
 358         /* Disable hardware debugging while we are in kgdb */
 359         bfin_write_WPIACTL(0);
 360         bfin_write_WPDACTL(0);
 361         CSYNC();
 362 }
 363
 364 #ifdef CONFIG_SMP
 365 void kgdb_passive_cpu_callback(void *info)
 366 {
 367         kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
 368 }
 369
 370 void kgdb_roundup_cpus(unsigned long flags)
 371 {
 372         smp_call_function(kgdb_passive_cpu_callback, NULL, 0);
 373 }
 374
 375 void kgdb_roundup_cpu(int cpu, unsigned long flags)
 376 {
 377         smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
 378 }
 379 #endif
 380
 381 void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
 382 {
 383         /* Master processor is completely in the debugger */
 384         gdb_bfin_vector = eVector;
 385         gdb_bfin_errcode = err_code;
 386 }
 387
 388 int kgdb_arch_handle_exception(int vector, int signo,
 389                                int err_code, char *remcom_in_buffer,
 390                                char *remcom_out_buffer,
 391                                struct pt_regs *regs)
 392 {
 393         long addr;
 394         char *ptr;
 395         int newPC;
 396         int i;
 397
 398         switch (remcom_in_buffer[0]) {
 399         case 'c':
 400         case 's':
 401                 if (kgdb_contthread && kgdb_contthread != current) {
 402                         strcpy(remcom_out_buffer, "E00");
 403                         break;
 404                 }
 405
 406                 kgdb_contthread = NULL;
 407
 408                 /* try to read optional parameter, pc unchanged if no parm */
 409                 ptr = &remcom_in_buffer[1];
 410                 if (kgdb_hex2long(&ptr, &addr)) {
 411                         regs->retx = addr;
 412                 }
 413                 newPC = regs->retx;
 414
 415                 /* clear the trace bit */
 416                 regs->syscfg &= 0xfffffffe;
 417
 418                 /* set the trace bit if we're stepping */
 419                 if (remcom_in_buffer[0] == 's') {
 420                         regs->syscfg |= 0x1;
 421                         kgdb_single_step = regs->ipend;
 422                         kgdb_single_step >>= 6;
 423                         for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
 424                                 if (kgdb_single_step & 1)
 425                                         break;
 426                         /* i indicate event priority of current stopped instruction
 427                          * user space instruction is 0, IVG15 is 1, IVTMR is 10.
 428                          * kgdb_single_step > 0 means in single step mode
 429                          */
 430                         kgdb_single_step = i + 1;
 431                 }
 432
 433                 bfin_correct_hw_break();
 434
 435                 return 0;
 436         }                       /* switch */
 437         return -1;              /* this means that we do not want to exit from the handler */
 438 }
 439
 440 struct kgdb_arch arch_kgdb_ops = {
 441         .gdb_bpt_instr = {0xa1},
 442 #ifdef CONFIG_SMP
 443         .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
 444 #else
 445         .flags = KGDB_HW_BREAKPOINT,
 446 #endif
 447         .set_hw_breakpoint = bfin_set_hw_break,
 448         .remove_hw_breakpoint = bfin_remove_hw_break,
 449         .remove_all_hw_break = bfin_remove_all_hw_break,
 450         .correct_hw_break = bfin_correct_hw_break,
 451 };
 452
 453 static int hex(char ch)
 454 {
 455         if ((ch >= 'a') && (ch <= 'f'))
 456                 return ch - 'a' + 10;
 457         if ((ch >= '0') && (ch <= '9'))
 458                 return ch - '0';
 459         if ((ch >= 'A') && (ch <= 'F'))
 460                 return ch - 'A' + 10;
 461         return -1;
 462 }
 463
 464 static int validate_memory_access_address(unsigned long addr, int size)
 465 {
 466         int cpu = raw_smp_processor_id();
 467
 468         if (size < 0)
 469                 return EFAULT;
 470         if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
 471                 return 0;
 472         if (addr >= SYSMMR_BASE)
 473                 return 0;
 474         if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
 475                 return 0;
 476         if (cpu == 0) {
 477                 if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
 478                         return 0;
 479                 if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH))
 480                         return 0;
 481                 if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
 482                         return 0;
 483                 if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
 484                         return 0;
 485 #ifdef CONFIG_SMP
 486         } else if (cpu == 1) {
 487                 if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
 488                         return 0;
 489                 if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
 490                         return 0;
 491                 if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
 492                         return 0;
 493                 if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
 494                         return 0;
 495 #endif
 496         }
 497
 498 #if L2_LENGTH
 499         if (IN_MEM(addr, size, L2_START, L2_LENGTH))
 500                 return 0;
 501 #endif
 502
 503         return EFAULT;
 504 }
 505
 506 /*
 507  * Convert the memory pointed to by mem into hex, placing result in buf.
 508  * Return a pointer to the last char put in buf (null). May return an error.
 509  */
 510 int kgdb_mem2hex(char *mem, char *buf, int count)
 511 {
 512         char *tmp;
 513         int err = 0;
 514         unsigned char *pch;
 515         unsigned short mmr16;
 516         unsigned long mmr32;
 517         int cpu = raw_smp_processor_id();
 518
 519         if (validate_memory_access_address((unsigned long)mem, count))
 520                 return EFAULT;
 521
 522         /*
 523          * We use the upper half of buf as an intermediate buffer for the
 524          * raw memory copy.  Hex conversion will work against this one.
 525          */
 526         tmp = buf + count;
 527
 528         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 529                 switch (count) {
 530                 case 2:
 531                         if ((unsigned int)mem % 2 == 0) {
 532                                 mmr16 = *(unsigned short *)mem;
 533                                 pch = (unsigned char *)&mmr16;
 534                                 *tmp++ = *pch++;
 535                                 *tmp++ = *pch++;
 536                                 tmp -= 2;
 537                         } else
 538                                 err = EFAULT;
 539                         break;
 540                 case 4:
 541                         if ((unsigned int)mem % 4 == 0) {
 542                                 mmr32 = *(unsigned long *)mem;
 543                                 pch = (unsigned char *)&mmr32;
 544                                 *tmp++ = *pch++;
 545                                 *tmp++ = *pch++;
 546                                 *tmp++ = *pch++;
 547                                 *tmp++ = *pch++;
 548                                 tmp -= 4;
 549                         } else
 550                                 err = EFAULT;
 551                         break;
 552                 default:
 553                         err = EFAULT;
 554                 }
 555         } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
 556 #ifdef CONFIG_SMP
 557                 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
 558 #endif
 559                 ) {
 560                 /* access L1 instruction SRAM*/
 561                 if (dma_memcpy(tmp, mem, count) == NULL)
 562                         err = EFAULT;
 563         } else
 564                 err = probe_kernel_read(tmp, mem, count);
 565
 566         if (!err) {
 567                 while (count > 0) {
 568                         buf = pack_hex_byte(buf, *tmp);
 569                         tmp++;
 570                         count--;
 571                 }
 572
 573                 *buf = 0;
 574         }
 575
 576         return err;
 577 }
 578
 579 /*
 580  * Copy the binary array pointed to by buf into mem.  Fix $, #, and
 581  * 0x7d escaped with 0x7d.  Return a pointer to the character after
 582  * the last byte written.
 583  */
 584 int kgdb_ebin2mem(char *buf, char *mem, int count)
 585 {
 586         char *tmp_old;
 587         char *tmp_new;
 588         unsigned short *mmr16;
 589         unsigned long *mmr32;
 590         int err = 0;
 591         int size = 0;
 592         int cpu = raw_smp_processor_id();
 593
 594         tmp_old = tmp_new = buf;
 595
 596         while (count-- > 0) {
 597                 if (*tmp_old == 0x7d)
 598                         *tmp_new = *(++tmp_old) ^ 0x20;
 599                 else
 600                         *tmp_new = *tmp_old;
 601                 tmp_new++;
 602                 tmp_old++;
 603                 size++;
 604         }
 605
 606         if (validate_memory_access_address((unsigned long)mem, size))
 607                 return EFAULT;
 608
 609         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 610                 switch (size) {
 611                 case 2:
 612                         if ((unsigned int)mem % 2 == 0) {
 613                                 mmr16 = (unsigned short *)buf;
 614                                 *(unsigned short *)mem = *mmr16;
 615                         } else
 616                                 return EFAULT;
 617                         break;
 618                 case 4:
 619                         if ((unsigned int)mem % 4 == 0) {
 620                                 mmr32 = (unsigned long *)buf;
 621                                 *(unsigned long *)mem = *mmr32;
 622                         } else
 623                                 return EFAULT;
 624                         break;
 625                 default:
 626                         return EFAULT;
 627                 }
 628         } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
 629 #ifdef CONFIG_SMP
 630                 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
 631 #endif
 632                 ) {
 633                 /* access L1 instruction SRAM */
 634                 if (dma_memcpy(mem, buf, size) == NULL)
 635                         err = EFAULT;
 636         } else
 637                 err = probe_kernel_write(mem, buf, size);
 638
 639         return err;
 640 }
 641
 642 /*
 643  * Convert the hex array pointed to by buf into binary to be placed in mem.
 644  * Return a pointer to the character AFTER the last byte written.
 645  * May return an error.
 646  */
 647 int kgdb_hex2mem(char *buf, char *mem, int count)
 648 {
 649         char *tmp_raw;
 650         char *tmp_hex;
 651         unsigned short *mmr16;
 652         unsigned long *mmr32;
 653         int cpu = raw_smp_processor_id();
 654
 655         if (validate_memory_access_address((unsigned long)mem, count))
 656                 return EFAULT;
 657
 658         /*
 659          * We use the upper half of buf as an intermediate buffer for the
 660          * raw memory that is converted from hex.
 661          */
 662         tmp_raw = buf + count * 2;
 663
 664         tmp_hex = tmp_raw - 1;
 665         while (tmp_hex >= buf) {
 666                 tmp_raw--;
 667                 *tmp_raw = hex(*tmp_hex--);
 668                 *tmp_raw |= hex(*tmp_hex--) << 4;
 669         }
 670
 671         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 672                 switch (count) {
 673                 case 2:
 674                         if ((unsigned int)mem % 2 == 0) {
 675                                 mmr16 = (unsigned short *)tmp_raw;
 676                                 *(unsigned short *)mem = *mmr16;
 677                         } else
 678                                 return EFAULT;
 679                         break;
 680                 case 4:
 681                         if ((unsigned int)mem % 4 == 0) {
 682                                 mmr32 = (unsigned long *)tmp_raw;
 683                                 *(unsigned long *)mem = *mmr32;
 684                         } else
 685                                 return EFAULT;
 686                         break;
 687                 default:
 688                         return EFAULT;
 689                 }
 690         } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
 691 #ifdef CONFIG_SMP
 692                 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
 693 #endif
 694                 ) {
 695                 /* access L1 instruction SRAM */
 696                 if (dma_memcpy(mem, tmp_raw, count) == NULL)
 697                         return EFAULT;
 698         } else
 699                 return probe_kernel_write(mem, tmp_raw, count);
 700         return 0;
 701 }
 702
 703 int kgdb_validate_break_address(unsigned long addr)
 704 {
 705         int cpu = raw_smp_processor_id();
 706
 707         if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
 708                 return 0;
 709         if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
 710                 return 0;
 711         if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
 712                 return 0;
 713 #ifdef CONFIG_SMP
 714         else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
 715                 return 0;
 716 #endif
 717 #if L2_LENGTH
 718         if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
 719                 return 0;
 720 #endif
 721
 722         return EFAULT;
 723 }
 724
 725 int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
 726 {
 727         int err;
 728         int cpu = raw_smp_processor_id();
 729
 730         if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
 731 #ifdef CONFIG_SMP
 732                 || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
 733 #endif
 734                 ) {
 735                 /* access L1 instruction SRAM */
 736                 if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
 737                         == NULL)
 738                         return -EFAULT;
 739
 740                 if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
 741                         BREAK_INSTR_SIZE) == NULL)
 742                         return -EFAULT;
 743
 744                 return 0;
 745         } else {
 746                 err = probe_kernel_read(saved_instr, (char *)addr,
 747                         BREAK_INSTR_SIZE);
 748                 if (err)
 749                         return err;
 750
 751                 return probe_kernel_write((char *)addr,
 752                         arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
 753         }
 754 }
 755
 756 int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
 757 {
 758         if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) {
 759                 /* access L1 instruction SRAM */
 760                 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
 761                         return -EFAULT;
 762
 763                 return 0;
 764         } else
 765                 return probe_kernel_write((char *)addr,
 766                                 (char *)bundle, BREAK_INSTR_SIZE);
 767 }
 768
 769 int kgdb_arch_init(void)
 770 {
 771         kgdb_single_step = 0;
 772
 773         bfin_remove_all_hw_break();
 774         return 0;
 775 }
 776
 777 void kgdb_arch_exit(void)
 778 {
 779 }