arch/blackfin/kernel/kgdb.c

   1 /*
   2  * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
   3  *
   4  * Copyright 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/smp.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/delay.h>
  15 #include <linux/ptrace.h>               /* for linux pt_regs struct */
  16 #include <linux/kgdb.h>
  17 #include <linux/console.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/irq.h>
  21 #include <linux/uaccess.h>
  22 #include <asm/system.h>
  23 #include <asm/traps.h>
  24 #include <asm/blackfin.h>
  25 #include <asm/dma.h>
  26
  27 /* Put the error code here just in case the user cares.  */
  28 int gdb_bfin_errcode;
  29 /* Likewise, the vector number here (since GDB only gets the signal
  30    number through the usual means, and that's not very specific).  */
  31 int gdb_bfin_vector = -1;
  32
  33 #if KGDB_MAX_NO_CPUS != 8
  34 #error change the definition of slavecpulocks
  35 #endif
  36
  37 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
  38 {
  39         gdb_regs[BFIN_R0] = regs->r0;
  40         gdb_regs[BFIN_R1] = regs->r1;
  41         gdb_regs[BFIN_R2] = regs->r2;
  42         gdb_regs[BFIN_R3] = regs->r3;
  43         gdb_regs[BFIN_R4] = regs->r4;
  44         gdb_regs[BFIN_R5] = regs->r5;
  45         gdb_regs[BFIN_R6] = regs->r6;
  46         gdb_regs[BFIN_R7] = regs->r7;
  47         gdb_regs[BFIN_P0] = regs->p0;
  48         gdb_regs[BFIN_P1] = regs->p1;
  49         gdb_regs[BFIN_P2] = regs->p2;
  50         gdb_regs[BFIN_P3] = regs->p3;
  51         gdb_regs[BFIN_P4] = regs->p4;
  52         gdb_regs[BFIN_P5] = regs->p5;
  53         gdb_regs[BFIN_SP] = regs->reserved;
  54         gdb_regs[BFIN_FP] = regs->fp;
  55         gdb_regs[BFIN_I0] = regs->i0;
  56         gdb_regs[BFIN_I1] = regs->i1;
  57         gdb_regs[BFIN_I2] = regs->i2;
  58         gdb_regs[BFIN_I3] = regs->i3;
  59         gdb_regs[BFIN_M0] = regs->m0;
  60         gdb_regs[BFIN_M1] = regs->m1;
  61         gdb_regs[BFIN_M2] = regs->m2;
  62         gdb_regs[BFIN_M3] = regs->m3;
  63         gdb_regs[BFIN_B0] = regs->b0;
  64         gdb_regs[BFIN_B1] = regs->b1;
  65         gdb_regs[BFIN_B2] = regs->b2;
  66         gdb_regs[BFIN_B3] = regs->b3;
  67         gdb_regs[BFIN_L0] = regs->l0;
  68         gdb_regs[BFIN_L1] = regs->l1;
  69         gdb_regs[BFIN_L2] = regs->l2;
  70         gdb_regs[BFIN_L3] = regs->l3;
  71         gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
  72         gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
  73         gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
  74         gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
  75         gdb_regs[BFIN_ASTAT] = regs->astat;
  76         gdb_regs[BFIN_RETS] = regs->rets;
  77         gdb_regs[BFIN_LC0] = regs->lc0;
  78         gdb_regs[BFIN_LT0] = regs->lt0;
  79         gdb_regs[BFIN_LB0] = regs->lb0;
  80         gdb_regs[BFIN_LC1] = regs->lc1;
  81         gdb_regs[BFIN_LT1] = regs->lt1;
  82         gdb_regs[BFIN_LB1] = regs->lb1;
  83         gdb_regs[BFIN_CYCLES] = 0;
  84         gdb_regs[BFIN_CYCLES2] = 0;
  85         gdb_regs[BFIN_USP] = regs->usp;
  86         gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
  87         gdb_regs[BFIN_SYSCFG] = regs->syscfg;
  88         gdb_regs[BFIN_RETI] = regs->pc;
  89         gdb_regs[BFIN_RETX] = regs->retx;
  90         gdb_regs[BFIN_RETN] = regs->retn;
  91         gdb_regs[BFIN_RETE] = regs->rete;
  92         gdb_regs[BFIN_PC] = regs->pc;
  93         gdb_regs[BFIN_CC] = 0;
  94         gdb_regs[BFIN_EXTRA1] = 0;
  95         gdb_regs[BFIN_EXTRA2] = 0;
  96         gdb_regs[BFIN_EXTRA3] = 0;
  97         gdb_regs[BFIN_IPEND] = regs->ipend;
  98 }
  99
 100 /*
 101  * Extracts ebp, esp and eip values understandable by gdb from the values
 102  * saved by switch_to.
 103  * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
 104  * prior to entering switch_to is 8 greater then the value that is saved.
 105  * If switch_to changes, change following code appropriately.
 106  */
 107 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
 108 {
 109         gdb_regs[BFIN_SP] = p->thread.ksp;
 110         gdb_regs[BFIN_PC] = p->thread.pc;
 111         gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
 112 }
 113
 114 void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 115 {
 116         regs->r0 = gdb_regs[BFIN_R0];
 117         regs->r1 = gdb_regs[BFIN_R1];
 118         regs->r2 = gdb_regs[BFIN_R2];
 119         regs->r3 = gdb_regs[BFIN_R3];
 120         regs->r4 = gdb_regs[BFIN_R4];
 121         regs->r5 = gdb_regs[BFIN_R5];
 122         regs->r6 = gdb_regs[BFIN_R6];
 123         regs->r7 = gdb_regs[BFIN_R7];
 124         regs->p0 = gdb_regs[BFIN_P0];
 125         regs->p1 = gdb_regs[BFIN_P1];
 126         regs->p2 = gdb_regs[BFIN_P2];
 127         regs->p3 = gdb_regs[BFIN_P3];
 128         regs->p4 = gdb_regs[BFIN_P4];
 129         regs->p5 = gdb_regs[BFIN_P5];
 130         regs->fp = gdb_regs[BFIN_FP];
 131         regs->i0 = gdb_regs[BFIN_I0];
 132         regs->i1 = gdb_regs[BFIN_I1];
 133         regs->i2 = gdb_regs[BFIN_I2];
 134         regs->i3 = gdb_regs[BFIN_I3];
 135         regs->m0 = gdb_regs[BFIN_M0];
 136         regs->m1 = gdb_regs[BFIN_M1];
 137         regs->m2 = gdb_regs[BFIN_M2];
 138         regs->m3 = gdb_regs[BFIN_M3];
 139         regs->b0 = gdb_regs[BFIN_B0];
 140         regs->b1 = gdb_regs[BFIN_B1];
 141         regs->b2 = gdb_regs[BFIN_B2];
 142         regs->b3 = gdb_regs[BFIN_B3];
 143         regs->l0 = gdb_regs[BFIN_L0];
 144         regs->l1 = gdb_regs[BFIN_L1];
 145         regs->l2 = gdb_regs[BFIN_L2];
 146         regs->l3 = gdb_regs[BFIN_L3];
 147         regs->a0x = gdb_regs[BFIN_A0_DOT_X];
 148         regs->a0w = gdb_regs[BFIN_A0_DOT_W];
 149         regs->a1x = gdb_regs[BFIN_A1_DOT_X];
 150         regs->a1w = gdb_regs[BFIN_A1_DOT_W];
 151         regs->rets = gdb_regs[BFIN_RETS];
 152         regs->lc0 = gdb_regs[BFIN_LC0];
 153         regs->lt0 = gdb_regs[BFIN_LT0];
 154         regs->lb0 = gdb_regs[BFIN_LB0];
 155         regs->lc1 = gdb_regs[BFIN_LC1];
 156         regs->lt1 = gdb_regs[BFIN_LT1];
 157         regs->lb1 = gdb_regs[BFIN_LB1];
 158         regs->usp = gdb_regs[BFIN_USP];
 159         regs->syscfg = gdb_regs[BFIN_SYSCFG];
 160         regs->retx = gdb_regs[BFIN_PC];
 161         regs->retn = gdb_regs[BFIN_RETN];
 162         regs->rete = gdb_regs[BFIN_RETE];
 163         regs->pc = gdb_regs[BFIN_PC];
 164
 165 #if 0                           /* can't change these */
 166         regs->astat = gdb_regs[BFIN_ASTAT];
 167         regs->seqstat = gdb_regs[BFIN_SEQSTAT];
 168         regs->ipend = gdb_regs[BFIN_IPEND];
 169 #endif
 170 }
 171
 172 struct hw_breakpoint {
 173         unsigned int occupied:1;
 174         unsigned int skip:1;
 175         unsigned int enabled:1;
 176         unsigned int type:1;
 177         unsigned int dataacc:2;
 178         unsigned short count;
 179         unsigned int addr;
 180 } breakinfo[HW_WATCHPOINT_NUM];
 181
 182 int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
 183 {
 184         int breakno;
 185         int bfin_type;
 186         int dataacc = 0;
 187
 188         switch (type) {
 189         case BP_HARDWARE_BREAKPOINT:
 190                 bfin_type = TYPE_INST_WATCHPOINT;
 191                 break;
 192         case BP_WRITE_WATCHPOINT:
 193                 dataacc = 1;
 194                 bfin_type = TYPE_DATA_WATCHPOINT;
 195                 break;
 196         case BP_READ_WATCHPOINT:
 197                 dataacc = 2;
 198                 bfin_type = TYPE_DATA_WATCHPOINT;
 199                 break;
 200         case BP_ACCESS_WATCHPOINT:
 201                 dataacc = 3;
 202                 bfin_type = TYPE_DATA_WATCHPOINT;
 203                 break;
 204         default:
 205                 return -ENOSPC;
 206         }
 207
 208         /* Becasue hardware data watchpoint impelemented in current
 209          * Blackfin can not trigger an exception event as the hardware
 210          * instrction watchpoint does, we ignaore all data watch point here.
 211          * They can be turned on easily after future blackfin design
 212          * supports this feature.
 213          */
 214         for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
 215                 if (bfin_type == breakinfo[breakno].type
 216                         && !breakinfo[breakno].occupied) {
 217                         breakinfo[breakno].occupied = 1;
 218                         breakinfo[breakno].skip = 0;
 219                         breakinfo[breakno].enabled = 1;
 220                         breakinfo[breakno].addr = addr;
 221                         breakinfo[breakno].dataacc = dataacc;
 222                         breakinfo[breakno].count = 0;
 223                         return 0;
 224                 }
 225
 226         return -ENOSPC;
 227 }
 228
 229 int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
 230 {
 231         int breakno;
 232         int bfin_type;
 233
 234         switch (type) {
 235         case BP_HARDWARE_BREAKPOINT:
 236                 bfin_type = TYPE_INST_WATCHPOINT;
 237                 break;
 238         case BP_WRITE_WATCHPOINT:
 239         case BP_READ_WATCHPOINT:
 240         case BP_ACCESS_WATCHPOINT:
 241                 bfin_type = TYPE_DATA_WATCHPOINT;
 242                 break;
 243         default:
 244                 return 0;
 245         }
 246         for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
 247                 if (bfin_type == breakinfo[breakno].type
 248                         && breakinfo[breakno].occupied
 249                         && breakinfo[breakno].addr == addr) {
 250                         breakinfo[breakno].occupied = 0;
 251                         breakinfo[breakno].enabled = 0;
 252                 }
 253
 254         return 0;
 255 }
 256
 257 void bfin_remove_all_hw_break(void)
 258 {
 259         int breakno;
 260
 261         memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
 262
 263         for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
 264                 breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
 265         for (; breakno < HW_WATCHPOINT_NUM; breakno++)
 266                 breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
 267 }
 268
 269 void bfin_correct_hw_break(void)
 270 {
 271         int breakno;
 272         unsigned int wpiactl = 0;
 273         unsigned int wpdactl = 0;
 274         int enable_wp = 0;
 275
 276         for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
 277                 if (breakinfo[breakno].enabled) {
 278                         enable_wp = 1;
 279
 280                         switch (breakno) {
 281                         case 0:
 282                                 wpiactl |= WPIAEN0|WPICNTEN0;
 283                                 bfin_write_WPIA0(breakinfo[breakno].addr);
 284                                 bfin_write_WPIACNT0(breakinfo[breakno].count
 285                                         + breakinfo->skip);
 286                                 break;
 287                         case 1:
 288                                 wpiactl |= WPIAEN1|WPICNTEN1;
 289                                 bfin_write_WPIA1(breakinfo[breakno].addr);
 290                                 bfin_write_WPIACNT1(breakinfo[breakno].count
 291                                         + breakinfo->skip);
 292                                 break;
 293                         case 2:
 294                                 wpiactl |= WPIAEN2|WPICNTEN2;
 295                                 bfin_write_WPIA2(breakinfo[breakno].addr);
 296                                 bfin_write_WPIACNT2(breakinfo[breakno].count
 297                                         + breakinfo->skip);
 298                                 break;
 299                         case 3:
 300                                 wpiactl |= WPIAEN3|WPICNTEN3;
 301                                 bfin_write_WPIA3(breakinfo[breakno].addr);
 302                                 bfin_write_WPIACNT3(breakinfo[breakno].count
 303                                         + breakinfo->skip);
 304                                 break;
 305                         case 4:
 306                                 wpiactl |= WPIAEN4|WPICNTEN4;
 307                                 bfin_write_WPIA4(breakinfo[breakno].addr);
 308                                 bfin_write_WPIACNT4(breakinfo[breakno].count
 309                                         + breakinfo->skip);
 310                                 break;
 311                         case 5:
 312                                 wpiactl |= WPIAEN5|WPICNTEN5;
 313                                 bfin_write_WPIA5(breakinfo[breakno].addr);
 314                                 bfin_write_WPIACNT5(breakinfo[breakno].count
 315                                         + breakinfo->skip);
 316                                 break;
 317                         case 6:
 318                                 wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
 319                                 wpdactl |= breakinfo[breakno].dataacc
 320                                         << WPDACC0_OFFSET;
 321                                 bfin_write_WPDA0(breakinfo[breakno].addr);
 322                                 bfin_write_WPDACNT0(breakinfo[breakno].count
 323                                         + breakinfo->skip);
 324                                 break;
 325                         case 7:
 326                                 wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
 327                                 wpdactl |= breakinfo[breakno].dataacc
 328                                         << WPDACC1_OFFSET;
 329                                 bfin_write_WPDA1(breakinfo[breakno].addr);
 330                                 bfin_write_WPDACNT1(breakinfo[breakno].count
 331                                         + breakinfo->skip);
 332                                 break;
 333                         }
 334                 }
 335
 336         /* Should enable WPPWR bit first before set any other
 337          * WPIACTL and WPDACTL bits */
 338         if (enable_wp) {
 339                 bfin_write_WPIACTL(WPPWR);
 340                 CSYNC();
 341                 bfin_write_WPIACTL(wpiactl|WPPWR);
 342                 bfin_write_WPDACTL(wpdactl);
 343                 CSYNC();
 344         }
 345 }
 346
 347 void kgdb_disable_hw_debug(struct pt_regs *regs)
 348 {
 349         /* Disable hardware debugging while we are in kgdb */
 350         bfin_write_WPIACTL(0);
 351         bfin_write_WPDACTL(0);
 352         CSYNC();
 353 }
 354
 355 #ifdef CONFIG_SMP
 356 void kgdb_passive_cpu_callback(void *info)
 357 {
 358         kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
 359 }
 360
 361 void kgdb_roundup_cpus(unsigned long flags)
 362 {
 363         smp_call_function(kgdb_passive_cpu_callback, NULL, 0);
 364 }
 365
 366 void kgdb_roundup_cpu(int cpu, unsigned long flags)
 367 {
 368         smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
 369 }
 370 #endif
 371
 372 void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
 373 {
 374         /* Master processor is completely in the debugger */
 375         gdb_bfin_vector = eVector;
 376         gdb_bfin_errcode = err_code;
 377 }
 378
 379 int kgdb_arch_handle_exception(int vector, int signo,
 380                                int err_code, char *remcom_in_buffer,
 381                                char *remcom_out_buffer,
 382                                struct pt_regs *regs)
 383 {
 384         long addr;
 385         char *ptr;
 386         int newPC;
 387         int i;
 388
 389         switch (remcom_in_buffer[0]) {
 390         case 'c':
 391         case 's':
 392                 if (kgdb_contthread && kgdb_contthread != current) {
 393                         strcpy(remcom_out_buffer, "E00");
 394                         break;
 395                 }
 396
 397                 kgdb_contthread = NULL;
 398
 399                 /* try to read optional parameter, pc unchanged if no parm */
 400                 ptr = &remcom_in_buffer[1];
 401                 if (kgdb_hex2long(&ptr, &addr)) {
 402                         regs->retx = addr;
 403                 }
 404                 newPC = regs->retx;
 405
 406                 /* clear the trace bit */
 407                 regs->syscfg &= 0xfffffffe;
 408
 409                 /* set the trace bit if we're stepping */
 410                 if (remcom_in_buffer[0] == 's') {
 411                         regs->syscfg |= 0x1;
 412                         kgdb_single_step = regs->ipend;
 413                         kgdb_single_step >>= 6;
 414                         for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
 415                                 if (kgdb_single_step & 1)
 416                                         break;
 417                         /* i indicate event priority of current stopped instruction
 418                          * user space instruction is 0, IVG15 is 1, IVTMR is 10.
 419                          * kgdb_single_step > 0 means in single step mode
 420                          */
 421                         kgdb_single_step = i + 1;
 422                 }
 423
 424                 bfin_correct_hw_break();
 425
 426                 return 0;
 427         }                       /* switch */
 428         return -1;              /* this means that we do not want to exit from the handler */
 429 }
 430
 431 struct kgdb_arch arch_kgdb_ops = {
 432         .gdb_bpt_instr = {0xa1},
 433 #ifdef CONFIG_SMP
 434         .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
 435 #else
 436         .flags = KGDB_HW_BREAKPOINT,
 437 #endif
 438         .set_hw_breakpoint = bfin_set_hw_break,
 439         .remove_hw_breakpoint = bfin_remove_hw_break,
 440         .remove_all_hw_break = bfin_remove_all_hw_break,
 441         .correct_hw_break = bfin_correct_hw_break,
 442 };
 443
 444 static int hex(char ch)
 445 {
 446         if ((ch >= 'a') && (ch <= 'f'))
 447                 return ch - 'a' + 10;
 448         if ((ch >= '0') && (ch <= '9'))
 449                 return ch - '0';
 450         if ((ch >= 'A') && (ch <= 'F'))
 451                 return ch - 'A' + 10;
 452         return -1;
 453 }
 454
 455 static int validate_memory_access_address(unsigned long addr, int size)
 456 {
 457         int cpu = raw_smp_processor_id();
 458
 459         if (size < 0)
 460                 return EFAULT;
 461         if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
 462                 return 0;
 463         if (addr >= SYSMMR_BASE)
 464                 return 0;
 465         if (addr >= ASYNC_BANK0_BASE
 466            && addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
 467                 return 0;
 468         if (cpu == 0) {
 469                 if (addr >= L1_SCRATCH_START
 470                    && (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
 471                         return 0;
 472 #if L1_CODE_LENGTH != 0
 473                 if (addr >= L1_CODE_START
 474                    && (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
 475                         return 0;
 476 #endif
 477 #if L1_DATA_A_LENGTH != 0
 478                 if (addr >= L1_DATA_A_START
 479                    && (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
 480                         return 0;
 481 #endif
 482 #if L1_DATA_B_LENGTH != 0
 483                 if (addr >= L1_DATA_B_START
 484                    && (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
 485                         return 0;
 486 #endif
 487 #ifdef CONFIG_SMP
 488         } else if (cpu == 1) {
 489                 if (addr >= COREB_L1_SCRATCH_START
 490                    && (addr + size <= COREB_L1_SCRATCH_START
 491                    + L1_SCRATCH_LENGTH))
 492                         return 0;
 493 # if L1_CODE_LENGTH != 0
 494                 if (addr >= COREB_L1_CODE_START
 495                    && (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
 496                         return 0;
 497 # endif
 498 # if L1_DATA_A_LENGTH != 0
 499                 if (addr >= COREB_L1_DATA_A_START
 500                    && (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
 501                         return 0;
 502 # endif
 503 # if L1_DATA_B_LENGTH != 0
 504                 if (addr >= COREB_L1_DATA_B_START
 505                    && (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
 506                         return 0;
 507 # endif
 508 #endif
 509         }
 510
 511 #if L2_LENGTH != 0
 512         if (addr >= L2_START
 513            && addr + size <= L2_START + L2_LENGTH)
 514                 return 0;
 515 #endif
 516
 517         return EFAULT;
 518 }
 519
 520 /*
 521  * Convert the memory pointed to by mem into hex, placing result in buf.
 522  * Return a pointer to the last char put in buf (null). May return an error.
 523  */
 524 int kgdb_mem2hex(char *mem, char *buf, int count)
 525 {
 526         char *tmp;
 527         int err = 0;
 528         unsigned char *pch;
 529         unsigned short mmr16;
 530         unsigned long mmr32;
 531         int cpu = raw_smp_processor_id();
 532
 533         if (validate_memory_access_address((unsigned long)mem, count))
 534                 return EFAULT;
 535
 536         /*
 537          * We use the upper half of buf as an intermediate buffer for the
 538          * raw memory copy.  Hex conversion will work against this one.
 539          */
 540         tmp = buf + count;
 541
 542         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 543                 switch (count) {
 544                 case 2:
 545                         if ((unsigned int)mem % 2 == 0) {
 546                                 mmr16 = *(unsigned short *)mem;
 547                                 pch = (unsigned char *)&mmr16;
 548                                 *tmp++ = *pch++;
 549                                 *tmp++ = *pch++;
 550                                 tmp -= 2;
 551                         } else
 552                                 err = EFAULT;
 553                         break;
 554                 case 4:
 555                         if ((unsigned int)mem % 4 == 0) {
 556                                 mmr32 = *(unsigned long *)mem;
 557                                 pch = (unsigned char *)&mmr32;
 558                                 *tmp++ = *pch++;
 559                                 *tmp++ = *pch++;
 560                                 *tmp++ = *pch++;
 561                                 *tmp++ = *pch++;
 562                                 tmp -= 4;
 563                         } else
 564                                 err = EFAULT;
 565                         break;
 566                 default:
 567                         err = EFAULT;
 568                 }
 569         } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
 570                 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
 571 #ifdef CONFIG_SMP
 572                 || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
 573                 (unsigned int)(mem + count) <=
 574                 COREB_L1_CODE_START + L1_CODE_LENGTH)
 575 #endif
 576                 ) {
 577                 /* access L1 instruction SRAM*/
 578                 if (dma_memcpy(tmp, mem, count) == NULL)
 579                         err = EFAULT;
 580         } else
 581                 err = probe_kernel_read(tmp, mem, count);
 582
 583         if (!err) {
 584                 while (count > 0) {
 585                         buf = pack_hex_byte(buf, *tmp);
 586                         tmp++;
 587                         count--;
 588                 }
 589
 590                 *buf = 0;
 591         }
 592
 593         return err;
 594 }
 595
 596 /*
 597  * Copy the binary array pointed to by buf into mem.  Fix $, #, and
 598  * 0x7d escaped with 0x7d.  Return a pointer to the character after
 599  * the last byte written.
 600  */
 601 int kgdb_ebin2mem(char *buf, char *mem, int count)
 602 {
 603         char *tmp_old;
 604         char *tmp_new;
 605         unsigned short *mmr16;
 606         unsigned long *mmr32;
 607         int err = 0;
 608         int size = 0;
 609         int cpu = raw_smp_processor_id();
 610
 611         tmp_old = tmp_new = buf;
 612
 613         while (count-- > 0) {
 614                 if (*tmp_old == 0x7d)
 615                         *tmp_new = *(++tmp_old) ^ 0x20;
 616                 else
 617                         *tmp_new = *tmp_old;
 618                 tmp_new++;
 619                 tmp_old++;
 620                 size++;
 621         }
 622
 623         if (validate_memory_access_address((unsigned long)mem, size))
 624                 return EFAULT;
 625
 626         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 627                 switch (size) {
 628                 case 2:
 629                         if ((unsigned int)mem % 2 == 0) {
 630                                 mmr16 = (unsigned short *)buf;
 631                                 *(unsigned short *)mem = *mmr16;
 632                         } else
 633                                 return EFAULT;
 634                         break;
 635                 case 4:
 636                         if ((unsigned int)mem % 4 == 0) {
 637                                 mmr32 = (unsigned long *)buf;
 638                                 *(unsigned long *)mem = *mmr32;
 639                         } else
 640                                 return EFAULT;
 641                         break;
 642                 default:
 643                         return EFAULT;
 644                 }
 645         } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
 646                 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
 647 #ifdef CONFIG_SMP
 648                 || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
 649                 (unsigned int)(mem + count) <=
 650                 COREB_L1_CODE_START + L1_CODE_LENGTH)
 651 #endif
 652                 ) {
 653                 /* access L1 instruction SRAM */
 654                 if (dma_memcpy(mem, buf, size) == NULL)
 655                         err = EFAULT;
 656         } else
 657                 err = probe_kernel_write(mem, buf, size);
 658
 659         return err;
 660 }
 661
 662 /*
 663  * Convert the hex array pointed to by buf into binary to be placed in mem.
 664  * Return a pointer to the character AFTER the last byte written.
 665  * May return an error.
 666  */
 667 int kgdb_hex2mem(char *buf, char *mem, int count)
 668 {
 669         char *tmp_raw;
 670         char *tmp_hex;
 671         unsigned short *mmr16;
 672         unsigned long *mmr32;
 673         int cpu = raw_smp_processor_id();
 674
 675         if (validate_memory_access_address((unsigned long)mem, count))
 676                 return EFAULT;
 677
 678         /*
 679          * We use the upper half of buf as an intermediate buffer for the
 680          * raw memory that is converted from hex.
 681          */
 682         tmp_raw = buf + count * 2;
 683
 684         tmp_hex = tmp_raw - 1;
 685         while (tmp_hex >= buf) {
 686                 tmp_raw--;
 687                 *tmp_raw = hex(*tmp_hex--);
 688                 *tmp_raw |= hex(*tmp_hex--) << 4;
 689         }
 690
 691         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 692                 switch (count) {
 693                 case 2:
 694                         if ((unsigned int)mem % 2 == 0) {
 695                                 mmr16 = (unsigned short *)tmp_raw;
 696                                 *(unsigned short *)mem = *mmr16;
 697                         } else
 698                                 return EFAULT;
 699                         break;
 700                 case 4:
 701                         if ((unsigned int)mem % 4 == 0) {
 702                                 mmr32 = (unsigned long *)tmp_raw;
 703                                 *(unsigned long *)mem = *mmr32;
 704                         } else
 705                                 return EFAULT;
 706                         break;
 707                 default:
 708                         return EFAULT;
 709                 }
 710         } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
 711                 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
 712 #ifdef CONFIG_SMP
 713                 || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
 714                 (unsigned int)(mem + count) <=
 715                 COREB_L1_CODE_START + L1_CODE_LENGTH)
 716 #endif
 717                 ) {
 718                 /* access L1 instruction SRAM */
 719                 if (dma_memcpy(mem, tmp_raw, count) == NULL)
 720                         return EFAULT;
 721         } else
 722                 return probe_kernel_write(mem, tmp_raw, count);
 723         return 0;
 724 }
 725
 726 int kgdb_validate_break_address(unsigned long addr)
 727 {
 728         int cpu = raw_smp_processor_id();
 729
 730         if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
 731                 return 0;
 732         if (addr >= ASYNC_BANK0_BASE
 733            && addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
 734                 return 0;
 735 #if L1_CODE_LENGTH != 0
 736         if (cpu == 0 && addr >= L1_CODE_START
 737            && addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
 738                 return 0;
 739 # ifdef CONFIG_SMP
 740         else if (cpu == 1 && addr >= COREB_L1_CODE_START
 741            && addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
 742                 return 0;
 743 # endif
 744 #endif
 745 #if L2_LENGTH != 0
 746         if (addr >= L2_START
 747            && addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
 748                 return 0;
 749 #endif
 750
 751         return EFAULT;
 752 }
 753
 754 int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
 755 {
 756         int err;
 757         int cpu = raw_smp_processor_id();
 758
 759         if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START
 760                 && (unsigned int)(addr + BREAK_INSTR_SIZE)
 761                 <= L1_CODE_START + L1_CODE_LENGTH)
 762 #ifdef CONFIG_SMP
 763                 || (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START
 764                 && (unsigned int)(addr + BREAK_INSTR_SIZE)
 765                 <= COREB_L1_CODE_START + L1_CODE_LENGTH)
 766 #endif
 767                 ) {
 768                 /* access L1 instruction SRAM */
 769                 if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
 770                         == NULL)
 771                         return -EFAULT;
 772
 773                 if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
 774                         BREAK_INSTR_SIZE) == NULL)
 775                         return -EFAULT;
 776
 777                 return 0;
 778         } else {
 779                 err = probe_kernel_read(saved_instr, (char *)addr,
 780                         BREAK_INSTR_SIZE);
 781                 if (err)
 782                         return err;
 783
 784                 return probe_kernel_write((char *)addr,
 785                         arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
 786         }
 787 }
 788
 789 int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
 790 {
 791         if ((unsigned int)addr >= L1_CODE_START &&
 792                 (unsigned int)(addr + BREAK_INSTR_SIZE) <=
 793                         L1_CODE_START + L1_CODE_LENGTH) {
 794                 /* access L1 instruction SRAM */
 795                 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
 796                         return -EFAULT;
 797
 798                 return 0;
 799         } else
 800                 return probe_kernel_write((char *)addr,
 801                                 (char *)bundle, BREAK_INSTR_SIZE);
 802 }
 803
 804 int kgdb_arch_init(void)
 805 {
 806         kgdb_single_step = 0;
 807
 808         bfin_remove_all_hw_break();
 809         return 0;
 810 }
 811
 812 void kgdb_arch_exit(void)
 813 {
 814 }