arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dw_dmac.h>
  11 #include <linux/fb.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/gpio.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/usb/atmel_usba_udc.h>
  18
  19 #include <asm/atmel-mci.h>
  20 #include <asm/io.h>
  21 #include <asm/irq.h>
  22
  23 #include <mach/at32ap700x.h>
  24 #include <mach/board.h>
  25 #include <mach/hmatrix.h>
  26 #include <mach/portmux.h>
  27 #include <mach/sram.h>
  28
  29 #include <video/atmel_lcdc.h>
  30
  31 #include "clock.h"
  32 #include "pio.h"
  33 #include "pm.h"
  34
  35
  36 #define PBMEM(base)                                     \
  37         {                                               \
  38                 .start          = base,                 \
  39                 .end            = base + 0x3ff,         \
  40                 .flags          = IORESOURCE_MEM,       \
  41         }
  42 #define IRQ(num)                                        \
  43         {                                               \
  44                 .start          = num,                  \
  45                 .end            = num,                  \
  46                 .flags          = IORESOURCE_IRQ,       \
  47         }
  48 #define NAMED_IRQ(num, _name)                           \
  49         {                                               \
  50                 .start          = num,                  \
  51                 .end            = num,                  \
  52                 .name           = _name,                \
  53                 .flags          = IORESOURCE_IRQ,       \
  54         }
  55
  56 /* REVISIT these assume *every* device supports DMA, but several
  57  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  58  */
  59 #define DEFINE_DEV(_name, _id)                                  \
  60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  61 static struct platform_device _name##_id##_device = {           \
  62         .name           = #_name,                               \
  63         .id             = _id,                                  \
  64         .dev            = {                                     \
  65                 .dma_mask = &_name##_id##_dma_mask,             \
  66                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  67         },                                                      \
  68         .resource       = _name##_id##_resource,                \
  69         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  70 }
  71 #define DEFINE_DEV_DATA(_name, _id)                             \
  72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  73 static struct platform_device _name##_id##_device = {           \
  74         .name           = #_name,                               \
  75         .id             = _id,                                  \
  76         .dev            = {                                     \
  77                 .dma_mask = &_name##_id##_dma_mask,             \
  78                 .platform_data  = &_name##_id##_data,           \
  79                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  80         },                                                      \
  81         .resource       = _name##_id##_resource,                \
  82         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  83 }
  84
  85 #define select_peripheral(port, pin_mask, periph, flags)        \
  86         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
  87                            GPIO_##periph, flags)
  88
  89 #define DEV_CLK(_name, devname, bus, _index)                    \
  90 static struct clk devname##_##_name = {                         \
  91         .name           = #_name,                               \
  92         .dev            = &devname##_device.dev,                \
  93         .parent         = &bus##_clk,                           \
  94         .mode           = bus##_clk_mode,                       \
  95         .get_rate       = bus##_clk_get_rate,                   \
  96         .index          = _index,                               \
  97 }
  98
  99 static DEFINE_SPINLOCK(pm_lock);
 100
 101 static struct clk osc0;
 102 static struct clk osc1;
 103
 104 static unsigned long osc_get_rate(struct clk *clk)
 105 {
 106         return at32_board_osc_rates[clk->index];
 107 }
 108
 109 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 110 {
 111         unsigned long div, mul, rate;
 112
 113         div = PM_BFEXT(PLLDIV, control) + 1;
 114         mul = PM_BFEXT(PLLMUL, control) + 1;
 115
 116         rate = clk->parent->get_rate(clk->parent);
 117         rate = (rate + div / 2) / div;
 118         rate *= mul;
 119
 120         return rate;
 121 }
 122
 123 static long pll_set_rate(struct clk *clk, unsigned long rate,
 124                          u32 *pll_ctrl)
 125 {
 126         unsigned long mul;
 127         unsigned long mul_best_fit = 0;
 128         unsigned long div;
 129         unsigned long div_min;
 130         unsigned long div_max;
 131         unsigned long div_best_fit = 0;
 132         unsigned long base;
 133         unsigned long pll_in;
 134         unsigned long actual = 0;
 135         unsigned long rate_error;
 136         unsigned long rate_error_prev = ~0UL;
 137         u32 ctrl;
 138
 139         /* Rate must be between 80 MHz and 200 Mhz. */
 140         if (rate < 80000000UL || rate > 200000000UL)
 141                 return -EINVAL;
 142
 143         ctrl = PM_BF(PLLOPT, 4);
 144         base = clk->parent->get_rate(clk->parent);
 145
 146         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 147         div_min = DIV_ROUND_UP(base, 32000000UL);
 148         div_max = base / 6000000UL;
 149
 150         if (div_max < div_min)
 151                 return -EINVAL;
 152
 153         for (div = div_min; div <= div_max; div++) {
 154                 pll_in = (base + div / 2) / div;
 155                 mul = (rate + pll_in / 2) / pll_in;
 156
 157                 if (mul == 0)
 158                         continue;
 159
 160                 actual = pll_in * mul;
 161                 rate_error = abs(actual - rate);
 162
 163                 if (rate_error < rate_error_prev) {
 164                         mul_best_fit = mul;
 165                         div_best_fit = div;
 166                         rate_error_prev = rate_error;
 167                 }
 168
 169                 if (rate_error == 0)
 170                         break;
 171         }
 172
 173         if (div_best_fit == 0)
 174                 return -EINVAL;
 175
 176         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 177         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 178         ctrl |= PM_BF(PLLCOUNT, 16);
 179
 180         if (clk->parent == &osc1)
 181                 ctrl |= PM_BIT(PLLOSC);
 182
 183         *pll_ctrl = ctrl;
 184
 185         return actual;
 186 }
 187
 188 static unsigned long pll0_get_rate(struct clk *clk)
 189 {
 190         u32 control;
 191
 192         control = pm_readl(PLL0);
 193
 194         return pll_get_rate(clk, control);
 195 }
 196
 197 static void pll1_mode(struct clk *clk, int enabled)
 198 {
 199         unsigned long timeout;
 200         u32 status;
 201         u32 ctrl;
 202
 203         ctrl = pm_readl(PLL1);
 204
 205         if (enabled) {
 206                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 207                         pr_debug("clk %s: failed to enable, rate not set\n",
 208                                         clk->name);
 209                         return;
 210                 }
 211
 212                 ctrl |= PM_BIT(PLLEN);
 213                 pm_writel(PLL1, ctrl);
 214
 215                 /* Wait for PLL lock. */
 216                 for (timeout = 10000; timeout; timeout--) {
 217                         status = pm_readl(ISR);
 218                         if (status & PM_BIT(LOCK1))
 219                                 break;
 220                         udelay(10);
 221                 }
 222
 223                 if (!(status & PM_BIT(LOCK1)))
 224                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 225                                         clk->name);
 226         } else {
 227                 ctrl &= ~PM_BIT(PLLEN);
 228                 pm_writel(PLL1, ctrl);
 229         }
 230 }
 231
 232 static unsigned long pll1_get_rate(struct clk *clk)
 233 {
 234         u32 control;
 235
 236         control = pm_readl(PLL1);
 237
 238         return pll_get_rate(clk, control);
 239 }
 240
 241 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 242 {
 243         u32 ctrl = 0;
 244         unsigned long actual_rate;
 245
 246         actual_rate = pll_set_rate(clk, rate, &ctrl);
 247
 248         if (apply) {
 249                 if (actual_rate != rate)
 250                         return -EINVAL;
 251                 if (clk->users > 0)
 252                         return -EBUSY;
 253                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 254                                 clk->name, rate, actual_rate);
 255                 pm_writel(PLL1, ctrl);
 256         }
 257
 258         return actual_rate;
 259 }
 260
 261 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 262 {
 263         u32 ctrl;
 264
 265         if (clk->users > 0)
 266                 return -EBUSY;
 267
 268         ctrl = pm_readl(PLL1);
 269         WARN_ON(ctrl & PM_BIT(PLLEN));
 270
 271         if (parent == &osc0)
 272                 ctrl &= ~PM_BIT(PLLOSC);
 273         else if (parent == &osc1)
 274                 ctrl |= PM_BIT(PLLOSC);
 275         else
 276                 return -EINVAL;
 277
 278         pm_writel(PLL1, ctrl);
 279         clk->parent = parent;
 280
 281         return 0;
 282 }
 283
 284 /*
 285  * The AT32AP7000 has five primary clock sources: One 32kHz
 286  * oscillator, two crystal oscillators and two PLLs.
 287  */
 288 static struct clk osc32k = {
 289         .name           = "osc32k",
 290         .get_rate       = osc_get_rate,
 291         .users          = 1,
 292         .index          = 0,
 293 };
 294 static struct clk osc0 = {
 295         .name           = "osc0",
 296         .get_rate       = osc_get_rate,
 297         .users          = 1,
 298         .index          = 1,
 299 };
 300 static struct clk osc1 = {
 301         .name           = "osc1",
 302         .get_rate       = osc_get_rate,
 303         .index          = 2,
 304 };
 305 static struct clk pll0 = {
 306         .name           = "pll0",
 307         .get_rate       = pll0_get_rate,
 308         .parent         = &osc0,
 309 };
 310 static struct clk pll1 = {
 311         .name           = "pll1",
 312         .mode           = pll1_mode,
 313         .get_rate       = pll1_get_rate,
 314         .set_rate       = pll1_set_rate,
 315         .set_parent     = pll1_set_parent,
 316         .parent         = &osc0,
 317 };
 318
 319 /*
 320  * The main clock can be either osc0 or pll0.  The boot loader may
 321  * have chosen one for us, so we don't really know which one until we
 322  * have a look at the SM.
 323  */
 324 static struct clk *main_clock;
 325
 326 /*
 327  * Synchronous clocks are generated from the main clock. The clocks
 328  * must satisfy the constraint
 329  *   fCPU >= fHSB >= fPB
 330  * i.e. each clock must not be faster than its parent.
 331  */
 332 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 333 {
 334         return main_clock->get_rate(main_clock) >> shift;
 335 };
 336
 337 static void cpu_clk_mode(struct clk *clk, int enabled)
 338 {
 339         unsigned long flags;
 340         u32 mask;
 341
 342         spin_lock_irqsave(&pm_lock, flags);
 343         mask = pm_readl(CPU_MASK);
 344         if (enabled)
 345                 mask |= 1 << clk->index;
 346         else
 347                 mask &= ~(1 << clk->index);
 348         pm_writel(CPU_MASK, mask);
 349         spin_unlock_irqrestore(&pm_lock, flags);
 350 }
 351
 352 static unsigned long cpu_clk_get_rate(struct clk *clk)
 353 {
 354         unsigned long cksel, shift = 0;
 355
 356         cksel = pm_readl(CKSEL);
 357         if (cksel & PM_BIT(CPUDIV))
 358                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 359
 360         return bus_clk_get_rate(clk, shift);
 361 }
 362
 363 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 364 {
 365         u32 control;
 366         unsigned long parent_rate, child_div, actual_rate, div;
 367
 368         parent_rate = clk->parent->get_rate(clk->parent);
 369         control = pm_readl(CKSEL);
 370
 371         if (control & PM_BIT(HSBDIV))
 372                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 373         else
 374                 child_div = 1;
 375
 376         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 377                 actual_rate = parent_rate;
 378                 control &= ~PM_BIT(CPUDIV);
 379         } else {
 380                 unsigned int cpusel;
 381                 div = (parent_rate + rate / 2) / rate;
 382                 if (div > child_div)
 383                         div = child_div;
 384                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 385                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 386                 actual_rate = parent_rate / (1 << (cpusel + 1));
 387         }
 388
 389         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 390                         clk->name, rate, actual_rate);
 391
 392         if (apply)
 393                 pm_writel(CKSEL, control);
 394
 395         return actual_rate;
 396 }
 397
 398 static void hsb_clk_mode(struct clk *clk, int enabled)
 399 {
 400         unsigned long flags;
 401         u32 mask;
 402
 403         spin_lock_irqsave(&pm_lock, flags);
 404         mask = pm_readl(HSB_MASK);
 405         if (enabled)
 406                 mask |= 1 << clk->index;
 407         else
 408                 mask &= ~(1 << clk->index);
 409         pm_writel(HSB_MASK, mask);
 410         spin_unlock_irqrestore(&pm_lock, flags);
 411 }
 412
 413 static unsigned long hsb_clk_get_rate(struct clk *clk)
 414 {
 415         unsigned long cksel, shift = 0;
 416
 417         cksel = pm_readl(CKSEL);
 418         if (cksel & PM_BIT(HSBDIV))
 419                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 420
 421         return bus_clk_get_rate(clk, shift);
 422 }
 423
 424 static void pba_clk_mode(struct clk *clk, int enabled)
 425 {
 426         unsigned long flags;
 427         u32 mask;
 428
 429         spin_lock_irqsave(&pm_lock, flags);
 430         mask = pm_readl(PBA_MASK);
 431         if (enabled)
 432                 mask |= 1 << clk->index;
 433         else
 434                 mask &= ~(1 << clk->index);
 435         pm_writel(PBA_MASK, mask);
 436         spin_unlock_irqrestore(&pm_lock, flags);
 437 }
 438
 439 static unsigned long pba_clk_get_rate(struct clk *clk)
 440 {
 441         unsigned long cksel, shift = 0;
 442
 443         cksel = pm_readl(CKSEL);
 444         if (cksel & PM_BIT(PBADIV))
 445                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 446
 447         return bus_clk_get_rate(clk, shift);
 448 }
 449
 450 static void pbb_clk_mode(struct clk *clk, int enabled)
 451 {
 452         unsigned long flags;
 453         u32 mask;
 454
 455         spin_lock_irqsave(&pm_lock, flags);
 456         mask = pm_readl(PBB_MASK);
 457         if (enabled)
 458                 mask |= 1 << clk->index;
 459         else
 460                 mask &= ~(1 << clk->index);
 461         pm_writel(PBB_MASK, mask);
 462         spin_unlock_irqrestore(&pm_lock, flags);
 463 }
 464
 465 static unsigned long pbb_clk_get_rate(struct clk *clk)
 466 {
 467         unsigned long cksel, shift = 0;
 468
 469         cksel = pm_readl(CKSEL);
 470         if (cksel & PM_BIT(PBBDIV))
 471                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 472
 473         return bus_clk_get_rate(clk, shift);
 474 }
 475
 476 static struct clk cpu_clk = {
 477         .name           = "cpu",
 478         .get_rate       = cpu_clk_get_rate,
 479         .set_rate       = cpu_clk_set_rate,
 480         .users          = 1,
 481 };
 482 static struct clk hsb_clk = {
 483         .name           = "hsb",
 484         .parent         = &cpu_clk,
 485         .get_rate       = hsb_clk_get_rate,
 486 };
 487 static struct clk pba_clk = {
 488         .name           = "pba",
 489         .parent         = &hsb_clk,
 490         .mode           = hsb_clk_mode,
 491         .get_rate       = pba_clk_get_rate,
 492         .index          = 1,
 493 };
 494 static struct clk pbb_clk = {
 495         .name           = "pbb",
 496         .parent         = &hsb_clk,
 497         .mode           = hsb_clk_mode,
 498         .get_rate       = pbb_clk_get_rate,
 499         .users          = 1,
 500         .index          = 2,
 501 };
 502
 503 /* --------------------------------------------------------------------
 504  *  Generic Clock operations
 505  * -------------------------------------------------------------------- */
 506
 507 static void genclk_mode(struct clk *clk, int enabled)
 508 {
 509         u32 control;
 510
 511         control = pm_readl(GCCTRL(clk->index));
 512         if (enabled)
 513                 control |= PM_BIT(CEN);
 514         else
 515                 control &= ~PM_BIT(CEN);
 516         pm_writel(GCCTRL(clk->index), control);
 517 }
 518
 519 static unsigned long genclk_get_rate(struct clk *clk)
 520 {
 521         u32 control;
 522         unsigned long div = 1;
 523
 524         control = pm_readl(GCCTRL(clk->index));
 525         if (control & PM_BIT(DIVEN))
 526                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 527
 528         return clk->parent->get_rate(clk->parent) / div;
 529 }
 530
 531 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 532 {
 533         u32 control;
 534         unsigned long parent_rate, actual_rate, div;
 535
 536         parent_rate = clk->parent->get_rate(clk->parent);
 537         control = pm_readl(GCCTRL(clk->index));
 538
 539         if (rate > 3 * parent_rate / 4) {
 540                 actual_rate = parent_rate;
 541                 control &= ~PM_BIT(DIVEN);
 542         } else {
 543                 div = (parent_rate + rate) / (2 * rate) - 1;
 544                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 545                 actual_rate = parent_rate / (2 * (div + 1));
 546         }
 547
 548         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 549                 clk->name, rate, actual_rate);
 550
 551         if (apply)
 552                 pm_writel(GCCTRL(clk->index), control);
 553
 554         return actual_rate;
 555 }
 556
 557 int genclk_set_parent(struct clk *clk, struct clk *parent)
 558 {
 559         u32 control;
 560
 561         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 562                 clk->name, parent->name, clk->parent->name);
 563
 564         control = pm_readl(GCCTRL(clk->index));
 565
 566         if (parent == &osc1 || parent == &pll1)
 567                 control |= PM_BIT(OSCSEL);
 568         else if (parent == &osc0 || parent == &pll0)
 569                 control &= ~PM_BIT(OSCSEL);
 570         else
 571                 return -EINVAL;
 572
 573         if (parent == &pll0 || parent == &pll1)
 574                 control |= PM_BIT(PLLSEL);
 575         else
 576                 control &= ~PM_BIT(PLLSEL);
 577
 578         pm_writel(GCCTRL(clk->index), control);
 579         clk->parent = parent;
 580
 581         return 0;
 582 }
 583
 584 static void __init genclk_init_parent(struct clk *clk)
 585 {
 586         u32 control;
 587         struct clk *parent;
 588
 589         BUG_ON(clk->index > 7);
 590
 591         control = pm_readl(GCCTRL(clk->index));
 592         if (control & PM_BIT(OSCSEL))
 593                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 594         else
 595                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 596
 597         clk->parent = parent;
 598 }
 599
 600 static struct dw_dma_platform_data dw_dmac0_data = {
 601         .nr_channels    = 3,
 602 };
 603
 604 static struct resource dw_dmac0_resource[] = {
 605         PBMEM(0xff200000),
 606         IRQ(2),
 607 };
 608 DEFINE_DEV_DATA(dw_dmac, 0);
 609 DEV_CLK(hclk, dw_dmac0, hsb, 10);
 610
 611 /* --------------------------------------------------------------------
 612  *  System peripherals
 613  * -------------------------------------------------------------------- */
 614 static struct resource at32_pm0_resource[] = {
 615         {
 616                 .start  = 0xfff00000,
 617                 .end    = 0xfff0007f,
 618                 .flags  = IORESOURCE_MEM,
 619         },
 620         IRQ(20),
 621 };
 622
 623 static struct resource at32ap700x_rtc0_resource[] = {
 624         {
 625                 .start  = 0xfff00080,
 626                 .end    = 0xfff000af,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629         IRQ(21),
 630 };
 631
 632 static struct resource at32_wdt0_resource[] = {
 633         {
 634                 .start  = 0xfff000b0,
 635                 .end    = 0xfff000cf,
 636                 .flags  = IORESOURCE_MEM,
 637         },
 638 };
 639
 640 static struct resource at32_eic0_resource[] = {
 641         {
 642                 .start  = 0xfff00100,
 643                 .end    = 0xfff0013f,
 644                 .flags  = IORESOURCE_MEM,
 645         },
 646         IRQ(19),
 647 };
 648
 649 DEFINE_DEV(at32_pm, 0);
 650 DEFINE_DEV(at32ap700x_rtc, 0);
 651 DEFINE_DEV(at32_wdt, 0);
 652 DEFINE_DEV(at32_eic, 0);
 653
 654 /*
 655  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 656  * is always running.
 657  */
 658 static struct clk at32_pm_pclk = {
 659         .name           = "pclk",
 660         .dev            = &at32_pm0_device.dev,
 661         .parent         = &pbb_clk,
 662         .mode           = pbb_clk_mode,
 663         .get_rate       = pbb_clk_get_rate,
 664         .users          = 1,
 665         .index          = 0,
 666 };
 667
 668 static struct resource intc0_resource[] = {
 669         PBMEM(0xfff00400),
 670 };
 671 struct platform_device at32_intc0_device = {
 672         .name           = "intc",
 673         .id             = 0,
 674         .resource       = intc0_resource,
 675         .num_resources  = ARRAY_SIZE(intc0_resource),
 676 };
 677 DEV_CLK(pclk, at32_intc0, pbb, 1);
 678
 679 static struct clk ebi_clk = {
 680         .name           = "ebi",
 681         .parent         = &hsb_clk,
 682         .mode           = hsb_clk_mode,
 683         .get_rate       = hsb_clk_get_rate,
 684         .users          = 1,
 685 };
 686 static struct clk hramc_clk = {
 687         .name           = "hramc",
 688         .parent         = &hsb_clk,
 689         .mode           = hsb_clk_mode,
 690         .get_rate       = hsb_clk_get_rate,
 691         .users          = 1,
 692         .index          = 3,
 693 };
 694 static struct clk sdramc_clk = {
 695         .name           = "sdramc_clk",
 696         .parent         = &pbb_clk,
 697         .mode           = pbb_clk_mode,
 698         .get_rate       = pbb_clk_get_rate,
 699         .users          = 1,
 700         .index          = 14,
 701 };
 702
 703 static struct resource smc0_resource[] = {
 704         PBMEM(0xfff03400),
 705 };
 706 DEFINE_DEV(smc, 0);
 707 DEV_CLK(pclk, smc0, pbb, 13);
 708 DEV_CLK(mck, smc0, hsb, 0);
 709
 710 static struct platform_device pdc_device = {
 711         .name           = "pdc",
 712         .id             = 0,
 713 };
 714 DEV_CLK(hclk, pdc, hsb, 4);
 715 DEV_CLK(pclk, pdc, pba, 16);
 716
 717 static struct clk pico_clk = {
 718         .name           = "pico",
 719         .parent         = &cpu_clk,
 720         .mode           = cpu_clk_mode,
 721         .get_rate       = cpu_clk_get_rate,
 722         .users          = 1,
 723 };
 724
 725 /* --------------------------------------------------------------------
 726  * HMATRIX
 727  * -------------------------------------------------------------------- */
 728
 729 struct clk at32_hmatrix_clk = {
 730         .name           = "hmatrix_clk",
 731         .parent         = &pbb_clk,
 732         .mode           = pbb_clk_mode,
 733         .get_rate       = pbb_clk_get_rate,
 734         .index          = 2,
 735         .users          = 1,
 736 };
 737
 738 /*
 739  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 740  * External Bus Interface (EBI). This can be used to enable special
 741  * features like CompactFlash support, NAND Flash support, etc. on
 742  * certain chipselects.
 743  */
 744 static inline void set_ebi_sfr_bits(u32 mask)
 745 {
 746         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
 747 }
 748
 749 /* --------------------------------------------------------------------
 750  *  Timer/Counter (TC)
 751  * -------------------------------------------------------------------- */
 752
 753 static struct resource at32_tcb0_resource[] = {
 754         PBMEM(0xfff00c00),
 755         IRQ(22),
 756 };
 757 static struct platform_device at32_tcb0_device = {
 758         .name           = "atmel_tcb",
 759         .id             = 0,
 760         .resource       = at32_tcb0_resource,
 761         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 762 };
 763 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 764
 765 static struct resource at32_tcb1_resource[] = {
 766         PBMEM(0xfff01000),
 767         IRQ(23),
 768 };
 769 static struct platform_device at32_tcb1_device = {
 770         .name           = "atmel_tcb",
 771         .id             = 1,
 772         .resource       = at32_tcb1_resource,
 773         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 774 };
 775 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 776
 777 /* --------------------------------------------------------------------
 778  *  PIO
 779  * -------------------------------------------------------------------- */
 780
 781 static struct resource pio0_resource[] = {
 782         PBMEM(0xffe02800),
 783         IRQ(13),
 784 };
 785 DEFINE_DEV(pio, 0);
 786 DEV_CLK(mck, pio0, pba, 10);
 787
 788 static struct resource pio1_resource[] = {
 789         PBMEM(0xffe02c00),
 790         IRQ(14),
 791 };
 792 DEFINE_DEV(pio, 1);
 793 DEV_CLK(mck, pio1, pba, 11);
 794
 795 static struct resource pio2_resource[] = {
 796         PBMEM(0xffe03000),
 797         IRQ(15),
 798 };
 799 DEFINE_DEV(pio, 2);
 800 DEV_CLK(mck, pio2, pba, 12);
 801
 802 static struct resource pio3_resource[] = {
 803         PBMEM(0xffe03400),
 804         IRQ(16),
 805 };
 806 DEFINE_DEV(pio, 3);
 807 DEV_CLK(mck, pio3, pba, 13);
 808
 809 static struct resource pio4_resource[] = {
 810         PBMEM(0xffe03800),
 811         IRQ(17),
 812 };
 813 DEFINE_DEV(pio, 4);
 814 DEV_CLK(mck, pio4, pba, 14);
 815
 816 void __init at32_add_system_devices(void)
 817 {
 818         platform_device_register(&at32_pm0_device);
 819         platform_device_register(&at32_intc0_device);
 820         platform_device_register(&at32ap700x_rtc0_device);
 821         platform_device_register(&at32_wdt0_device);
 822         platform_device_register(&at32_eic0_device);
 823         platform_device_register(&smc0_device);
 824         platform_device_register(&pdc_device);
 825         platform_device_register(&dw_dmac0_device);
 826
 827         platform_device_register(&at32_tcb0_device);
 828         platform_device_register(&at32_tcb1_device);
 829
 830         platform_device_register(&pio0_device);
 831         platform_device_register(&pio1_device);
 832         platform_device_register(&pio2_device);
 833         platform_device_register(&pio3_device);
 834         platform_device_register(&pio4_device);
 835 }
 836
 837 /* --------------------------------------------------------------------
 838  *  PSIF
 839  * -------------------------------------------------------------------- */
 840 static struct resource atmel_psif0_resource[] __initdata = {
 841         {
 842                 .start  = 0xffe03c00,
 843                 .end    = 0xffe03cff,
 844                 .flags  = IORESOURCE_MEM,
 845         },
 846         IRQ(18),
 847 };
 848 static struct clk atmel_psif0_pclk = {
 849         .name           = "pclk",
 850         .parent         = &pba_clk,
 851         .mode           = pba_clk_mode,
 852         .get_rate       = pba_clk_get_rate,
 853         .index          = 15,
 854 };
 855
 856 static struct resource atmel_psif1_resource[] __initdata = {
 857         {
 858                 .start  = 0xffe03d00,
 859                 .end    = 0xffe03dff,
 860                 .flags  = IORESOURCE_MEM,
 861         },
 862         IRQ(18),
 863 };
 864 static struct clk atmel_psif1_pclk = {
 865         .name           = "pclk",
 866         .parent         = &pba_clk,
 867         .mode           = pba_clk_mode,
 868         .get_rate       = pba_clk_get_rate,
 869         .index          = 15,
 870 };
 871
 872 struct platform_device *__init at32_add_device_psif(unsigned int id)
 873 {
 874         struct platform_device *pdev;
 875         u32 pin_mask;
 876
 877         if (!(id == 0 || id == 1))
 878                 return NULL;
 879
 880         pdev = platform_device_alloc("atmel_psif", id);
 881         if (!pdev)
 882                 return NULL;
 883
 884         switch (id) {
 885         case 0:
 886                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
 887
 888                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
 889                                         ARRAY_SIZE(atmel_psif0_resource)))
 890                         goto err_add_resources;
 891                 atmel_psif0_pclk.dev = &pdev->dev;
 892                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 893                 break;
 894         case 1:
 895                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
 896
 897                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
 898                                         ARRAY_SIZE(atmel_psif1_resource)))
 899                         goto err_add_resources;
 900                 atmel_psif1_pclk.dev = &pdev->dev;
 901                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
 902                 break;
 903         default:
 904                 return NULL;
 905         }
 906
 907         platform_device_add(pdev);
 908         return pdev;
 909
 910 err_add_resources:
 911         platform_device_put(pdev);
 912         return NULL;
 913 }
 914
 915 /* --------------------------------------------------------------------
 916  *  USART
 917  * -------------------------------------------------------------------- */
 918
 919 static struct atmel_uart_data atmel_usart0_data = {
 920         .use_dma_tx     = 1,
 921         .use_dma_rx     = 1,
 922 };
 923 static struct resource atmel_usart0_resource[] = {
 924         PBMEM(0xffe00c00),
 925         IRQ(6),
 926 };
 927 DEFINE_DEV_DATA(atmel_usart, 0);
 928 DEV_CLK(usart, atmel_usart0, pba, 3);
 929
 930 static struct atmel_uart_data atmel_usart1_data = {
 931         .use_dma_tx     = 1,
 932         .use_dma_rx     = 1,
 933 };
 934 static struct resource atmel_usart1_resource[] = {
 935         PBMEM(0xffe01000),
 936         IRQ(7),
 937 };
 938 DEFINE_DEV_DATA(atmel_usart, 1);
 939 DEV_CLK(usart, atmel_usart1, pba, 4);
 940
 941 static struct atmel_uart_data atmel_usart2_data = {
 942         .use_dma_tx     = 1,
 943         .use_dma_rx     = 1,
 944 };
 945 static struct resource atmel_usart2_resource[] = {
 946         PBMEM(0xffe01400),
 947         IRQ(8),
 948 };
 949 DEFINE_DEV_DATA(atmel_usart, 2);
 950 DEV_CLK(usart, atmel_usart2, pba, 5);
 951
 952 static struct atmel_uart_data atmel_usart3_data = {
 953         .use_dma_tx     = 1,
 954         .use_dma_rx     = 1,
 955 };
 956 static struct resource atmel_usart3_resource[] = {
 957         PBMEM(0xffe01800),
 958         IRQ(9),
 959 };
 960 DEFINE_DEV_DATA(atmel_usart, 3);
 961 DEV_CLK(usart, atmel_usart3, pba, 6);
 962
 963 static inline void configure_usart0_pins(void)
 964 {
 965         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
 966
 967         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
 968 }
 969
 970 static inline void configure_usart1_pins(void)
 971 {
 972         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
 973
 974         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 975 }
 976
 977 static inline void configure_usart2_pins(void)
 978 {
 979         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
 980
 981         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
 982 }
 983
 984 static inline void configure_usart3_pins(void)
 985 {
 986         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
 987
 988         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
 989 }
 990
 991 static struct platform_device *__initdata at32_usarts[4];
 992
 993 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 994 {
 995         struct platform_device *pdev;
 996
 997         switch (hw_id) {
 998         case 0:
 999                 pdev = &atmel_usart0_device;
1000                 configure_usart0_pins();
1001                 break;
1002         case 1:
1003                 pdev = &atmel_usart1_device;
1004                 configure_usart1_pins();
1005                 break;
1006         case 2:
1007                 pdev = &atmel_usart2_device;
1008                 configure_usart2_pins();
1009                 break;
1010         case 3:
1011                 pdev = &atmel_usart3_device;
1012                 configure_usart3_pins();
1013                 break;
1014         default:
1015                 return;
1016         }
1017
1018         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1019                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1020                 struct atmel_uart_data *data = pdev->dev.platform_data;
1021                 data->regs = (void __iomem *)pdev->resource[0].start;
1022         }
1023
1024         pdev->id = line;
1025         at32_usarts[line] = pdev;
1026 }
1027
1028 struct platform_device *__init at32_add_device_usart(unsigned int id)
1029 {
1030         platform_device_register(at32_usarts[id]);
1031         return at32_usarts[id];
1032 }
1033
1034 struct platform_device *atmel_default_console_device;
1035
1036 void __init at32_setup_serial_console(unsigned int usart_id)
1037 {
1038         atmel_default_console_device = at32_usarts[usart_id];
1039 }
1040
1041 /* --------------------------------------------------------------------
1042  *  Ethernet
1043  * -------------------------------------------------------------------- */
1044
1045 #ifdef CONFIG_CPU_AT32AP7000
1046 static struct eth_platform_data macb0_data;
1047 static struct resource macb0_resource[] = {
1048         PBMEM(0xfff01800),
1049         IRQ(25),
1050 };
1051 DEFINE_DEV_DATA(macb, 0);
1052 DEV_CLK(hclk, macb0, hsb, 8);
1053 DEV_CLK(pclk, macb0, pbb, 6);
1054
1055 static struct eth_platform_data macb1_data;
1056 static struct resource macb1_resource[] = {
1057         PBMEM(0xfff01c00),
1058         IRQ(26),
1059 };
1060 DEFINE_DEV_DATA(macb, 1);
1061 DEV_CLK(hclk, macb1, hsb, 9);
1062 DEV_CLK(pclk, macb1, pbb, 7);
1063
1064 struct platform_device *__init
1065 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1066 {
1067         struct platform_device *pdev;
1068         u32 pin_mask;
1069
1070         switch (id) {
1071         case 0:
1072                 pdev = &macb0_device;
1073
1074                 pin_mask  = (1 << 3);   /* TXD0 */
1075                 pin_mask |= (1 << 4);   /* TXD1 */
1076                 pin_mask |= (1 << 7);   /* TXEN */
1077                 pin_mask |= (1 << 8);   /* TXCK */
1078                 pin_mask |= (1 << 9);   /* RXD0 */
1079                 pin_mask |= (1 << 10);  /* RXD1 */
1080                 pin_mask |= (1 << 13);  /* RXER */
1081                 pin_mask |= (1 << 15);  /* RXDV */
1082                 pin_mask |= (1 << 16);  /* MDC  */
1083                 pin_mask |= (1 << 17);  /* MDIO */
1084
1085                 if (!data->is_rmii) {
1086                         pin_mask |= (1 << 0);   /* COL  */
1087                         pin_mask |= (1 << 1);   /* CRS  */
1088                         pin_mask |= (1 << 2);   /* TXER */
1089                         pin_mask |= (1 << 5);   /* TXD2 */
1090                         pin_mask |= (1 << 6);   /* TXD3 */
1091                         pin_mask |= (1 << 11);  /* RXD2 */
1092                         pin_mask |= (1 << 12);  /* RXD3 */
1093                         pin_mask |= (1 << 14);  /* RXCK */
1094 #ifndef CONFIG_BOARD_MIMC200
1095                         pin_mask |= (1 << 18);  /* SPD  */
1096 #endif
1097                 }
1098
1099                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1100
1101                 break;
1102
1103         case 1:
1104                 pdev = &macb1_device;
1105
1106                 pin_mask  = (1 << 13);  /* TXD0 */
1107                 pin_mask |= (1 << 14);  /* TXD1 */
1108                 pin_mask |= (1 << 11);  /* TXEN */
1109                 pin_mask |= (1 << 12);  /* TXCK */
1110                 pin_mask |= (1 << 10);  /* RXD0 */
1111                 pin_mask |= (1 << 6);   /* RXD1 */
1112                 pin_mask |= (1 << 5);   /* RXER */
1113                 pin_mask |= (1 << 4);   /* RXDV */
1114                 pin_mask |= (1 << 3);   /* MDC  */
1115                 pin_mask |= (1 << 2);   /* MDIO */
1116
1117 #ifndef CONFIG_BOARD_MIMC200
1118                 if (!data->is_rmii)
1119                         pin_mask |= (1 << 15);  /* SPD  */
1120 #endif
1121
1122                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1123
1124                 if (!data->is_rmii) {
1125                         pin_mask  = (1 << 19);  /* COL  */
1126                         pin_mask |= (1 << 23);  /* CRS  */
1127                         pin_mask |= (1 << 26);  /* TXER */
1128                         pin_mask |= (1 << 27);  /* TXD2 */
1129                         pin_mask |= (1 << 28);  /* TXD3 */
1130                         pin_mask |= (1 << 29);  /* RXD2 */
1131                         pin_mask |= (1 << 30);  /* RXD3 */
1132                         pin_mask |= (1 << 24);  /* RXCK */
1133
1134                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1135                 }
1136                 break;
1137
1138         default:
1139                 return NULL;
1140         }
1141
1142         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1143         platform_device_register(pdev);
1144
1145         return pdev;
1146 }
1147 #endif
1148
1149 /* --------------------------------------------------------------------
1150  *  SPI
1151  * -------------------------------------------------------------------- */
1152 static struct resource atmel_spi0_resource[] = {
1153         PBMEM(0xffe00000),
1154         IRQ(3),
1155 };
1156 DEFINE_DEV(atmel_spi, 0);
1157 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1158
1159 static struct resource atmel_spi1_resource[] = {
1160         PBMEM(0xffe00400),
1161         IRQ(4),
1162 };
1163 DEFINE_DEV(atmel_spi, 1);
1164 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1165
1166 static void __init
1167 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1168                       unsigned int n, const u8 *pins)
1169 {
1170         unsigned int pin, mode;
1171
1172         for (; n; n--, b++) {
1173                 b->bus_num = bus_num;
1174                 if (b->chip_select >= 4)
1175                         continue;
1176                 pin = (unsigned)b->controller_data;
1177                 if (!pin) {
1178                         pin = pins[b->chip_select];
1179                         b->controller_data = (void *)pin;
1180                 }
1181                 mode = AT32_GPIOF_OUTPUT;
1182                 if (!(b->mode & SPI_CS_HIGH))
1183                         mode |= AT32_GPIOF_HIGH;
1184                 at32_select_gpio(pin, mode);
1185         }
1186 }
1187
1188 struct platform_device *__init
1189 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1190 {
1191         /*
1192          * Manage the chipselects as GPIOs, normally using the same pins
1193          * the SPI controller expects; but boards can use other pins.
1194          */
1195         static u8 __initdata spi0_pins[] =
1196                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1197                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1198         static u8 __initdata spi1_pins[] =
1199                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1200                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1201         struct platform_device *pdev;
1202         u32 pin_mask;
1203
1204         switch (id) {
1205         case 0:
1206                 pdev = &atmel_spi0_device;
1207                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1208
1209                 /* pullup MISO so a level is always defined */
1210                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1211                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1212
1213                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1214                 break;
1215
1216         case 1:
1217                 pdev = &atmel_spi1_device;
1218                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1219
1220                 /* pullup MISO so a level is always defined */
1221                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1222                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1223
1224                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1225                 break;
1226
1227         default:
1228                 return NULL;
1229         }
1230
1231         spi_register_board_info(b, n);
1232         platform_device_register(pdev);
1233         return pdev;
1234 }
1235
1236 /* --------------------------------------------------------------------
1237  *  TWI
1238  * -------------------------------------------------------------------- */
1239 static struct resource atmel_twi0_resource[] __initdata = {
1240         PBMEM(0xffe00800),
1241         IRQ(5),
1242 };
1243 static struct clk atmel_twi0_pclk = {
1244         .name           = "twi_pclk",
1245         .parent         = &pba_clk,
1246         .mode           = pba_clk_mode,
1247         .get_rate       = pba_clk_get_rate,
1248         .index          = 2,
1249 };
1250
1251 struct platform_device *__init at32_add_device_twi(unsigned int id,
1252                                                     struct i2c_board_info *b,
1253                                                     unsigned int n)
1254 {
1255         struct platform_device *pdev;
1256         u32 pin_mask;
1257
1258         if (id != 0)
1259                 return NULL;
1260
1261         pdev = platform_device_alloc("atmel_twi", id);
1262         if (!pdev)
1263                 return NULL;
1264
1265         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1266                                 ARRAY_SIZE(atmel_twi0_resource)))
1267                 goto err_add_resources;
1268
1269         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1270
1271         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1272
1273         atmel_twi0_pclk.dev = &pdev->dev;
1274
1275         if (b)
1276                 i2c_register_board_info(id, b, n);
1277
1278         platform_device_add(pdev);
1279         return pdev;
1280
1281 err_add_resources:
1282         platform_device_put(pdev);
1283         return NULL;
1284 }
1285
1286 /* --------------------------------------------------------------------
1287  * MMC
1288  * -------------------------------------------------------------------- */
1289 static struct resource atmel_mci0_resource[] __initdata = {
1290         PBMEM(0xfff02400),
1291         IRQ(28),
1292 };
1293 static struct clk atmel_mci0_pclk = {
1294         .name           = "mci_clk",
1295         .parent         = &pbb_clk,
1296         .mode           = pbb_clk_mode,
1297         .get_rate       = pbb_clk_get_rate,
1298         .index          = 9,
1299 };
1300
1301 struct platform_device *__init
1302 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1303 {
1304         struct platform_device          *pdev;
1305         struct dw_dma_slave             *dws;
1306         u32                             pioa_mask;
1307         u32                             piob_mask;
1308
1309         if (id != 0 || !data)
1310                 return NULL;
1311
1312         /* Must have at least one usable slot */
1313         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1314                 return NULL;
1315
1316         pdev = platform_device_alloc("atmel_mci", id);
1317         if (!pdev)
1318                 goto fail;
1319
1320         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1321                                 ARRAY_SIZE(atmel_mci0_resource)))
1322                 goto fail;
1323
1324         if (data->dma_slave)
1325                 dws = kmemdup(to_dw_dma_slave(data->dma_slave),
1326                                 sizeof(struct dw_dma_slave), GFP_KERNEL);
1327         else
1328                 dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
1329
1330         dws->slave.dev = &pdev->dev;
1331         dws->slave.dma_dev = &dw_dmac0_device.dev;
1332         dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
1333         dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1334                                 | DWC_CFGH_DST_PER(1));
1335         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1336                                 | DWC_CFGL_HS_SRC_POL);
1337
1338         data->dma_slave = &dws->slave;
1339
1340         if (platform_device_add_data(pdev, data,
1341                                 sizeof(struct mci_platform_data)))
1342                 goto fail;
1343
1344         /* CLK line is common to both slots */
1345         pioa_mask = 1 << 10;
1346
1347         switch (data->slot[0].bus_width) {
1348         case 4:
1349                 pioa_mask |= 1 << 13;           /* DATA1 */
1350                 pioa_mask |= 1 << 14;           /* DATA2 */
1351                 pioa_mask |= 1 << 15;           /* DATA3 */
1352                 /* fall through */
1353         case 1:
1354                 pioa_mask |= 1 << 11;           /* CMD   */
1355                 pioa_mask |= 1 << 12;           /* DATA0 */
1356
1357                 if (gpio_is_valid(data->slot[0].detect_pin))
1358                         at32_select_gpio(data->slot[0].detect_pin, 0);
1359                 if (gpio_is_valid(data->slot[0].wp_pin))
1360                         at32_select_gpio(data->slot[0].wp_pin, 0);
1361                 break;
1362         case 0:
1363                 /* Slot is unused */
1364                 break;
1365         default:
1366                 goto fail;
1367         }
1368
1369         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1370         piob_mask = 0;
1371
1372         switch (data->slot[1].bus_width) {
1373         case 4:
1374                 piob_mask |= 1 <<  8;           /* DATA1 */
1375                 piob_mask |= 1 <<  9;           /* DATA2 */
1376                 piob_mask |= 1 << 10;           /* DATA3 */
1377                 /* fall through */
1378         case 1:
1379                 piob_mask |= 1 <<  6;           /* CMD   */
1380                 piob_mask |= 1 <<  7;           /* DATA0 */
1381                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1382
1383                 if (gpio_is_valid(data->slot[1].detect_pin))
1384                         at32_select_gpio(data->slot[1].detect_pin, 0);
1385                 if (gpio_is_valid(data->slot[1].wp_pin))
1386                         at32_select_gpio(data->slot[1].wp_pin, 0);
1387                 break;
1388         case 0:
1389                 /* Slot is unused */
1390                 break;
1391         default:
1392                 if (!data->slot[0].bus_width)
1393                         goto fail;
1394
1395                 data->slot[1].bus_width = 0;
1396                 break;
1397         }
1398
1399         atmel_mci0_pclk.dev = &pdev->dev;
1400
1401         platform_device_add(pdev);
1402         return pdev;
1403
1404 fail:
1405         platform_device_put(pdev);
1406         return NULL;
1407 }
1408
1409 /* --------------------------------------------------------------------
1410  *  LCDC
1411  * -------------------------------------------------------------------- */
1412 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1413 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1414 static struct resource atmel_lcdfb0_resource[] = {
1415         {
1416                 .start          = 0xff000000,
1417                 .end            = 0xff000fff,
1418                 .flags          = IORESOURCE_MEM,
1419         },
1420         IRQ(1),
1421         {
1422                 /* Placeholder for pre-allocated fb memory */
1423                 .start          = 0x00000000,
1424                 .end            = 0x00000000,
1425                 .flags          = 0,
1426         },
1427 };
1428 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1429 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1430 static struct clk atmel_lcdfb0_pixclk = {
1431         .name           = "lcdc_clk",
1432         .dev            = &atmel_lcdfb0_device.dev,
1433         .mode           = genclk_mode,
1434         .get_rate       = genclk_get_rate,
1435         .set_rate       = genclk_set_rate,
1436         .set_parent     = genclk_set_parent,
1437         .index          = 7,
1438 };
1439
1440 struct platform_device *__init
1441 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1442                      unsigned long fbmem_start, unsigned long fbmem_len,
1443                      u64 pin_mask)
1444 {
1445         struct platform_device *pdev;
1446         struct atmel_lcdfb_info *info;
1447         struct fb_monspecs *monspecs;
1448         struct fb_videomode *modedb;
1449         unsigned int modedb_size;
1450         u32 portc_mask, portd_mask, porte_mask;
1451
1452         /*
1453          * Do a deep copy of the fb data, monspecs and modedb. Make
1454          * sure all allocations are done before setting up the
1455          * portmux.
1456          */
1457         monspecs = kmemdup(data->default_monspecs,
1458                            sizeof(struct fb_monspecs), GFP_KERNEL);
1459         if (!monspecs)
1460                 return NULL;
1461
1462         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1463         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1464         if (!modedb)
1465                 goto err_dup_modedb;
1466         monspecs->modedb = modedb;
1467
1468         switch (id) {
1469         case 0:
1470                 pdev = &atmel_lcdfb0_device;
1471
1472                 if (pin_mask == 0ULL)
1473                         /* Default to "full" lcdc control signals and 24bit */
1474                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1475
1476                 /* LCDC on port C */
1477                 portc_mask = (pin_mask & 0xfff80000) >> 19;
1478                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1479
1480                 /* LCDC on port D */
1481                 portd_mask = pin_mask & 0x0003ffff;
1482                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1483
1484                 /* LCDC on port E */
1485                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1486                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1487
1488                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1489                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1490                 break;
1491
1492         default:
1493                 goto err_invalid_id;
1494         }
1495
1496         if (fbmem_len) {
1497                 pdev->resource[2].start = fbmem_start;
1498                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1499                 pdev->resource[2].flags = IORESOURCE_MEM;
1500         }
1501
1502         info = pdev->dev.platform_data;
1503         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1504         info->default_monspecs = monspecs;
1505
1506         platform_device_register(pdev);
1507         return pdev;
1508
1509 err_invalid_id:
1510         kfree(modedb);
1511 err_dup_modedb:
1512         kfree(monspecs);
1513         return NULL;
1514 }
1515 #endif
1516
1517 /* --------------------------------------------------------------------
1518  *  PWM
1519  * -------------------------------------------------------------------- */
1520 static struct resource atmel_pwm0_resource[] __initdata = {
1521         PBMEM(0xfff01400),
1522         IRQ(24),
1523 };
1524 static struct clk atmel_pwm0_mck = {
1525         .name           = "pwm_clk",
1526         .parent         = &pbb_clk,
1527         .mode           = pbb_clk_mode,
1528         .get_rate       = pbb_clk_get_rate,
1529         .index          = 5,
1530 };
1531
1532 struct platform_device *__init at32_add_device_pwm(u32 mask)
1533 {
1534         struct platform_device *pdev;
1535         u32 pin_mask;
1536
1537         if (!mask)
1538                 return NULL;
1539
1540         pdev = platform_device_alloc("atmel_pwm", 0);
1541         if (!pdev)
1542                 return NULL;
1543
1544         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1545                                 ARRAY_SIZE(atmel_pwm0_resource)))
1546                 goto out_free_pdev;
1547
1548         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1549                 goto out_free_pdev;
1550
1551         pin_mask = 0;
1552         if (mask & (1 << 0))
1553                 pin_mask |= (1 << 28);
1554         if (mask & (1 << 1))
1555                 pin_mask |= (1 << 29);
1556         if (pin_mask > 0)
1557                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1558
1559         pin_mask = 0;
1560         if (mask & (1 << 2))
1561                 pin_mask |= (1 << 21);
1562         if (mask & (1 << 3))
1563                 pin_mask |= (1 << 22);
1564         if (pin_mask > 0)
1565                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1566
1567         atmel_pwm0_mck.dev = &pdev->dev;
1568
1569         platform_device_add(pdev);
1570
1571         return pdev;
1572
1573 out_free_pdev:
1574         platform_device_put(pdev);
1575         return NULL;
1576 }
1577
1578 /* --------------------------------------------------------------------
1579  *  SSC
1580  * -------------------------------------------------------------------- */
1581 static struct resource ssc0_resource[] = {
1582         PBMEM(0xffe01c00),
1583         IRQ(10),
1584 };
1585 DEFINE_DEV(ssc, 0);
1586 DEV_CLK(pclk, ssc0, pba, 7);
1587
1588 static struct resource ssc1_resource[] = {
1589         PBMEM(0xffe02000),
1590         IRQ(11),
1591 };
1592 DEFINE_DEV(ssc, 1);
1593 DEV_CLK(pclk, ssc1, pba, 8);
1594
1595 static struct resource ssc2_resource[] = {
1596         PBMEM(0xffe02400),
1597         IRQ(12),
1598 };
1599 DEFINE_DEV(ssc, 2);
1600 DEV_CLK(pclk, ssc2, pba, 9);
1601
1602 struct platform_device *__init
1603 at32_add_device_ssc(unsigned int id, unsigned int flags)
1604 {
1605         struct platform_device *pdev;
1606         u32 pin_mask = 0;
1607
1608         switch (id) {
1609         case 0:
1610                 pdev = &ssc0_device;
1611                 if (flags & ATMEL_SSC_RF)
1612                         pin_mask |= (1 << 21);  /* RF */
1613                 if (flags & ATMEL_SSC_RK)
1614                         pin_mask |= (1 << 22);  /* RK */
1615                 if (flags & ATMEL_SSC_TK)
1616                         pin_mask |= (1 << 23);  /* TK */
1617                 if (flags & ATMEL_SSC_TF)
1618                         pin_mask |= (1 << 24);  /* TF */
1619                 if (flags & ATMEL_SSC_TD)
1620                         pin_mask |= (1 << 25);  /* TD */
1621                 if (flags & ATMEL_SSC_RD)
1622                         pin_mask |= (1 << 26);  /* RD */
1623
1624                 if (pin_mask > 0)
1625                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1626
1627                 break;
1628         case 1:
1629                 pdev = &ssc1_device;
1630                 if (flags & ATMEL_SSC_RF)
1631                         pin_mask |= (1 << 0);   /* RF */
1632                 if (flags & ATMEL_SSC_RK)
1633                         pin_mask |= (1 << 1);   /* RK */
1634                 if (flags & ATMEL_SSC_TK)
1635                         pin_mask |= (1 << 2);   /* TK */
1636                 if (flags & ATMEL_SSC_TF)
1637                         pin_mask |= (1 << 3);   /* TF */
1638                 if (flags & ATMEL_SSC_TD)
1639                         pin_mask |= (1 << 4);   /* TD */
1640                 if (flags & ATMEL_SSC_RD)
1641                         pin_mask |= (1 << 5);   /* RD */
1642
1643                 if (pin_mask > 0)
1644                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1645
1646                 break;
1647         case 2:
1648                 pdev = &ssc2_device;
1649                 if (flags & ATMEL_SSC_TD)
1650                         pin_mask |= (1 << 13);  /* TD */
1651                 if (flags & ATMEL_SSC_RD)
1652                         pin_mask |= (1 << 14);  /* RD */
1653                 if (flags & ATMEL_SSC_TK)
1654                         pin_mask |= (1 << 15);  /* TK */
1655                 if (flags & ATMEL_SSC_TF)
1656                         pin_mask |= (1 << 16);  /* TF */
1657                 if (flags & ATMEL_SSC_RF)
1658                         pin_mask |= (1 << 17);  /* RF */
1659                 if (flags & ATMEL_SSC_RK)
1660                         pin_mask |= (1 << 18);  /* RK */
1661
1662                 if (pin_mask > 0)
1663                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1664
1665                 break;
1666         default:
1667                 return NULL;
1668         }
1669
1670         platform_device_register(pdev);
1671         return pdev;
1672 }
1673
1674 /* --------------------------------------------------------------------
1675  *  USB Device Controller
1676  * -------------------------------------------------------------------- */
1677 static struct resource usba0_resource[] __initdata = {
1678         {
1679                 .start          = 0xff300000,
1680                 .end            = 0xff3fffff,
1681                 .flags          = IORESOURCE_MEM,
1682         }, {
1683                 .start          = 0xfff03000,
1684                 .end            = 0xfff033ff,
1685                 .flags          = IORESOURCE_MEM,
1686         },
1687         IRQ(31),
1688 };
1689 static struct clk usba0_pclk = {
1690         .name           = "pclk",
1691         .parent         = &pbb_clk,
1692         .mode           = pbb_clk_mode,
1693         .get_rate       = pbb_clk_get_rate,
1694         .index          = 12,
1695 };
1696 static struct clk usba0_hclk = {
1697         .name           = "hclk",
1698         .parent         = &hsb_clk,
1699         .mode           = hsb_clk_mode,
1700         .get_rate       = hsb_clk_get_rate,
1701         .index          = 6,
1702 };
1703
1704 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1705         [idx] = {                                               \
1706                 .name           = nam,                          \
1707                 .index          = idx,                          \
1708                 .fifo_size      = maxpkt,                       \
1709                 .nr_banks       = maxbk,                        \
1710                 .can_dma        = dma,                          \
1711                 .can_isoc       = isoc,                         \
1712         }
1713
1714 static struct usba_ep_data at32_usba_ep[] __initdata = {
1715         EP("ep0",     0,   64, 1, 0, 0),
1716         EP("ep1",     1,  512, 2, 1, 1),
1717         EP("ep2",     2,  512, 2, 1, 1),
1718         EP("ep3-int", 3,   64, 3, 1, 0),
1719         EP("ep4-int", 4,   64, 3, 1, 0),
1720         EP("ep5",     5, 1024, 3, 1, 1),
1721         EP("ep6",     6, 1024, 3, 1, 1),
1722 };
1723
1724 #undef EP
1725
1726 struct platform_device *__init
1727 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1728 {
1729         /*
1730          * pdata doesn't have room for any endpoints, so we need to
1731          * append room for the ones we need right after it.
1732          */
1733         struct {
1734                 struct usba_platform_data pdata;
1735                 struct usba_ep_data ep[7];
1736         } usba_data;
1737         struct platform_device *pdev;
1738
1739         if (id != 0)
1740                 return NULL;
1741
1742         pdev = platform_device_alloc("atmel_usba_udc", 0);
1743         if (!pdev)
1744                 return NULL;
1745
1746         if (platform_device_add_resources(pdev, usba0_resource,
1747                                           ARRAY_SIZE(usba0_resource)))
1748                 goto out_free_pdev;
1749
1750         if (data)
1751                 usba_data.pdata.vbus_pin = data->vbus_pin;
1752         else
1753                 usba_data.pdata.vbus_pin = -EINVAL;
1754
1755         data = &usba_data.pdata;
1756         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1757         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1758
1759         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1760                 goto out_free_pdev;
1761
1762         if (data->vbus_pin >= 0)
1763                 at32_select_gpio(data->vbus_pin, 0);
1764
1765         usba0_pclk.dev = &pdev->dev;
1766         usba0_hclk.dev = &pdev->dev;
1767
1768         platform_device_add(pdev);
1769
1770         return pdev;
1771
1772 out_free_pdev:
1773         platform_device_put(pdev);
1774         return NULL;
1775 }
1776
1777 /* --------------------------------------------------------------------
1778  * IDE / CompactFlash
1779  * -------------------------------------------------------------------- */
1780 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1781 static struct resource at32_smc_cs4_resource[] __initdata = {
1782         {
1783                 .start  = 0x04000000,
1784                 .end    = 0x07ffffff,
1785                 .flags  = IORESOURCE_MEM,
1786         },
1787         IRQ(~0UL), /* Magic IRQ will be overridden */
1788 };
1789 static struct resource at32_smc_cs5_resource[] __initdata = {
1790         {
1791                 .start  = 0x20000000,
1792                 .end    = 0x23ffffff,
1793                 .flags  = IORESOURCE_MEM,
1794         },
1795         IRQ(~0UL), /* Magic IRQ will be overridden */
1796 };
1797
1798 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1799                 unsigned int cs, unsigned int extint)
1800 {
1801         static unsigned int extint_pin_map[4] __initdata = {
1802                 (1 << 25),
1803                 (1 << 26),
1804                 (1 << 27),
1805                 (1 << 28),
1806         };
1807         static bool common_pins_initialized __initdata = false;
1808         unsigned int extint_pin;
1809         int ret;
1810         u32 pin_mask;
1811
1812         if (extint >= ARRAY_SIZE(extint_pin_map))
1813                 return -EINVAL;
1814         extint_pin = extint_pin_map[extint];
1815
1816         switch (cs) {
1817         case 4:
1818                 ret = platform_device_add_resources(pdev,
1819                                 at32_smc_cs4_resource,
1820                                 ARRAY_SIZE(at32_smc_cs4_resource));
1821                 if (ret)
1822                         return ret;
1823
1824                 /* NCS4   -> OE_N  */
1825                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1826                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1827                 break;
1828         case 5:
1829                 ret = platform_device_add_resources(pdev,
1830                                 at32_smc_cs5_resource,
1831                                 ARRAY_SIZE(at32_smc_cs5_resource));
1832                 if (ret)
1833                         return ret;
1834
1835                 /* NCS5   -> OE_N  */
1836                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1837                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1838                 break;
1839         default:
1840                 return -EINVAL;
1841         }
1842
1843         if (!common_pins_initialized) {
1844                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1845                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1846                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1847                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1848
1849                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1850
1851                 common_pins_initialized = true;
1852         }
1853
1854         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1855
1856         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1857         pdev->resource[1].end = pdev->resource[1].start;
1858
1859         return 0;
1860 }
1861
1862 struct platform_device *__init
1863 at32_add_device_ide(unsigned int id, unsigned int extint,
1864                     struct ide_platform_data *data)
1865 {
1866         struct platform_device *pdev;
1867
1868         pdev = platform_device_alloc("at32_ide", id);
1869         if (!pdev)
1870                 goto fail;
1871
1872         if (platform_device_add_data(pdev, data,
1873                                 sizeof(struct ide_platform_data)))
1874                 goto fail;
1875
1876         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1877                 goto fail;
1878
1879         platform_device_add(pdev);
1880         return pdev;
1881
1882 fail:
1883         platform_device_put(pdev);
1884         return NULL;
1885 }
1886
1887 struct platform_device *__init
1888 at32_add_device_cf(unsigned int id, unsigned int extint,
1889                     struct cf_platform_data *data)
1890 {
1891         struct platform_device *pdev;
1892
1893         pdev = platform_device_alloc("at32_cf", id);
1894         if (!pdev)
1895                 goto fail;
1896
1897         if (platform_device_add_data(pdev, data,
1898                                 sizeof(struct cf_platform_data)))
1899                 goto fail;
1900
1901         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1902                 goto fail;
1903
1904         if (gpio_is_valid(data->detect_pin))
1905                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1906         if (gpio_is_valid(data->reset_pin))
1907                 at32_select_gpio(data->reset_pin, 0);
1908         if (gpio_is_valid(data->vcc_pin))
1909                 at32_select_gpio(data->vcc_pin, 0);
1910         /* READY is used as extint, so we can't select it as gpio */
1911
1912         platform_device_add(pdev);
1913         return pdev;
1914
1915 fail:
1916         platform_device_put(pdev);
1917         return NULL;
1918 }
1919 #endif
1920
1921 /* --------------------------------------------------------------------
1922  * NAND Flash / SmartMedia
1923  * -------------------------------------------------------------------- */
1924 static struct resource smc_cs3_resource[] __initdata = {
1925         {
1926                 .start  = 0x0c000000,
1927                 .end    = 0x0fffffff,
1928                 .flags  = IORESOURCE_MEM,
1929         }, {
1930                 .start  = 0xfff03c00,
1931                 .end    = 0xfff03fff,
1932                 .flags  = IORESOURCE_MEM,
1933         },
1934 };
1935
1936 struct platform_device *__init
1937 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1938 {
1939         struct platform_device *pdev;
1940
1941         if (id != 0 || !data)
1942                 return NULL;
1943
1944         pdev = platform_device_alloc("atmel_nand", id);
1945         if (!pdev)
1946                 goto fail;
1947
1948         if (platform_device_add_resources(pdev, smc_cs3_resource,
1949                                 ARRAY_SIZE(smc_cs3_resource)))
1950                 goto fail;
1951
1952         if (platform_device_add_data(pdev, data,
1953                                 sizeof(struct atmel_nand_data)))
1954                 goto fail;
1955
1956         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1957         if (data->enable_pin)
1958                 at32_select_gpio(data->enable_pin,
1959                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1960         if (data->rdy_pin)
1961                 at32_select_gpio(data->rdy_pin, 0);
1962         if (data->det_pin)
1963                 at32_select_gpio(data->det_pin, 0);
1964
1965         platform_device_add(pdev);
1966         return pdev;
1967
1968 fail:
1969         platform_device_put(pdev);
1970         return NULL;
1971 }
1972
1973 /* --------------------------------------------------------------------
1974  * AC97C
1975  * -------------------------------------------------------------------- */
1976 static struct resource atmel_ac97c0_resource[] __initdata = {
1977         PBMEM(0xfff02800),
1978         IRQ(29),
1979 };
1980 static struct clk atmel_ac97c0_pclk = {
1981         .name           = "pclk",
1982         .parent         = &pbb_clk,
1983         .mode           = pbb_clk_mode,
1984         .get_rate       = pbb_clk_get_rate,
1985         .index          = 10,
1986 };
1987
1988 struct platform_device *__init
1989 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1990 {
1991         struct platform_device *pdev;
1992         struct ac97c_platform_data _data;
1993         u32 pin_mask;
1994
1995         if (id != 0)
1996                 return NULL;
1997
1998         pdev = platform_device_alloc("atmel_ac97c", id);
1999         if (!pdev)
2000                 return NULL;
2001
2002         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2003                                 ARRAY_SIZE(atmel_ac97c0_resource)))
2004                 goto fail;
2005
2006         if (!data) {
2007                 data = &_data;
2008                 memset(data, 0, sizeof(struct ac97c_platform_data));
2009                 data->reset_pin = GPIO_PIN_NONE;
2010         }
2011
2012         data->dma_rx_periph_id = 3;
2013         data->dma_tx_periph_id = 4;
2014         data->dma_controller_id = 0;
2015
2016         if (platform_device_add_data(pdev, data,
2017                                 sizeof(struct ac97c_platform_data)))
2018                 goto fail;
2019
2020         pin_mask  = (1 << 20) | (1 << 21);      /* SDO & SYNC */
2021         pin_mask |= (1 << 22) | (1 << 23);      /* SCLK & SDI */
2022
2023         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2024
2025         /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
2026         if (data->reset_pin != GPIO_PIN_NONE)
2027                 at32_select_gpio(data->reset_pin, 0);
2028
2029         atmel_ac97c0_pclk.dev = &pdev->dev;
2030
2031         platform_device_add(pdev);
2032         return pdev;
2033
2034 fail:
2035         platform_device_put(pdev);
2036         return NULL;
2037 }
2038
2039 /* --------------------------------------------------------------------
2040  * ABDAC
2041  * -------------------------------------------------------------------- */
2042 static struct resource abdac0_resource[] __initdata = {
2043         PBMEM(0xfff02000),
2044         IRQ(27),
2045 };
2046 static struct clk abdac0_pclk = {
2047         .name           = "pclk",
2048         .parent         = &pbb_clk,
2049         .mode           = pbb_clk_mode,
2050         .get_rate       = pbb_clk_get_rate,
2051         .index          = 8,
2052 };
2053 static struct clk abdac0_sample_clk = {
2054         .name           = "sample_clk",
2055         .mode           = genclk_mode,
2056         .get_rate       = genclk_get_rate,
2057         .set_rate       = genclk_set_rate,
2058         .set_parent     = genclk_set_parent,
2059         .index          = 6,
2060 };
2061
2062 struct platform_device *__init at32_add_device_abdac(unsigned int id)
2063 {
2064         struct platform_device *pdev;
2065         u32 pin_mask;
2066
2067         if (id != 0)
2068                 return NULL;
2069
2070         pdev = platform_device_alloc("abdac", id);
2071         if (!pdev)
2072                 return NULL;
2073
2074         if (platform_device_add_resources(pdev, abdac0_resource,
2075                                 ARRAY_SIZE(abdac0_resource)))
2076                 goto err_add_resources;
2077
2078         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2079         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2080
2081         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2082
2083         abdac0_pclk.dev = &pdev->dev;
2084         abdac0_sample_clk.dev = &pdev->dev;
2085
2086         platform_device_add(pdev);
2087         return pdev;
2088
2089 err_add_resources:
2090         platform_device_put(pdev);
2091         return NULL;
2092 }
2093
2094 /* --------------------------------------------------------------------
2095  *  GCLK
2096  * -------------------------------------------------------------------- */
2097 static struct clk gclk0 = {
2098         .name           = "gclk0",
2099         .mode           = genclk_mode,
2100         .get_rate       = genclk_get_rate,
2101         .set_rate       = genclk_set_rate,
2102         .set_parent     = genclk_set_parent,
2103         .index          = 0,
2104 };
2105 static struct clk gclk1 = {
2106         .name           = "gclk1",
2107         .mode           = genclk_mode,
2108         .get_rate       = genclk_get_rate,
2109         .set_rate       = genclk_set_rate,
2110         .set_parent     = genclk_set_parent,
2111         .index          = 1,
2112 };
2113 static struct clk gclk2 = {
2114         .name           = "gclk2",
2115         .mode           = genclk_mode,
2116         .get_rate       = genclk_get_rate,
2117         .set_rate       = genclk_set_rate,
2118         .set_parent     = genclk_set_parent,
2119         .index          = 2,
2120 };
2121 static struct clk gclk3 = {
2122         .name           = "gclk3",
2123         .mode           = genclk_mode,
2124         .get_rate       = genclk_get_rate,
2125         .set_rate       = genclk_set_rate,
2126         .set_parent     = genclk_set_parent,
2127         .index          = 3,
2128 };
2129 static struct clk gclk4 = {
2130         .name           = "gclk4",
2131         .mode           = genclk_mode,
2132         .get_rate       = genclk_get_rate,
2133         .set_rate       = genclk_set_rate,
2134         .set_parent     = genclk_set_parent,
2135         .index          = 4,
2136 };
2137
2138 static __initdata struct clk *init_clocks[] = {
2139         &osc32k,
2140         &osc0,
2141         &osc1,
2142         &pll0,
2143         &pll1,
2144         &cpu_clk,
2145         &hsb_clk,
2146         &pba_clk,
2147         &pbb_clk,
2148         &at32_pm_pclk,
2149         &at32_intc0_pclk,
2150         &at32_hmatrix_clk,
2151         &ebi_clk,
2152         &hramc_clk,
2153         &sdramc_clk,
2154         &smc0_pclk,
2155         &smc0_mck,
2156         &pdc_hclk,
2157         &pdc_pclk,
2158         &dw_dmac0_hclk,
2159         &pico_clk,
2160         &pio0_mck,
2161         &pio1_mck,
2162         &pio2_mck,
2163         &pio3_mck,
2164         &pio4_mck,
2165         &at32_tcb0_t0_clk,
2166         &at32_tcb1_t0_clk,
2167         &atmel_psif0_pclk,
2168         &atmel_psif1_pclk,
2169         &atmel_usart0_usart,
2170         &atmel_usart1_usart,
2171         &atmel_usart2_usart,
2172         &atmel_usart3_usart,
2173         &atmel_pwm0_mck,
2174 #if defined(CONFIG_CPU_AT32AP7000)
2175         &macb0_hclk,
2176         &macb0_pclk,
2177         &macb1_hclk,
2178         &macb1_pclk,
2179 #endif
2180         &atmel_spi0_spi_clk,
2181         &atmel_spi1_spi_clk,
2182         &atmel_twi0_pclk,
2183         &atmel_mci0_pclk,
2184 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2185         &atmel_lcdfb0_hck1,
2186         &atmel_lcdfb0_pixclk,
2187 #endif
2188         &ssc0_pclk,
2189         &ssc1_pclk,
2190         &ssc2_pclk,
2191         &usba0_hclk,
2192         &usba0_pclk,
2193         &atmel_ac97c0_pclk,
2194         &abdac0_pclk,
2195         &abdac0_sample_clk,
2196         &gclk0,
2197         &gclk1,
2198         &gclk2,
2199         &gclk3,
2200         &gclk4,
2201 };
2202
2203 void __init setup_platform(void)
2204 {
2205         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2206         int i;
2207
2208         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2209                 main_clock = &pll0;
2210                 cpu_clk.parent = &pll0;
2211         } else {
2212                 main_clock = &osc0;
2213                 cpu_clk.parent = &osc0;
2214         }
2215
2216         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2217                 pll0.parent = &osc1;
2218         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2219                 pll1.parent = &osc1;
2220
2221         genclk_init_parent(&gclk0);
2222         genclk_init_parent(&gclk1);
2223         genclk_init_parent(&gclk2);
2224         genclk_init_parent(&gclk3);
2225         genclk_init_parent(&gclk4);
2226 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2227         genclk_init_parent(&atmel_lcdfb0_pixclk);
2228 #endif
2229         genclk_init_parent(&abdac0_sample_clk);
2230
2231         /*
2232          * Build initial dynamic clock list by registering all clocks
2233          * from the array.
2234          * At the same time, turn on all clocks that have at least one
2235          * user already, and turn off everything else. We only do this
2236          * for module clocks, and even though it isn't particularly
2237          * pretty to  check the address of the mode function, it should
2238          * do the trick...
2239          */
2240         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2241                 struct clk *clk = init_clocks[i];
2242
2243                 /* first, register clock */
2244                 at32_clk_register(clk);
2245
2246                 if (clk->users == 0)
2247                         continue;
2248
2249                 if (clk->mode == &cpu_clk_mode)
2250                         cpu_mask |= 1 << clk->index;
2251                 else if (clk->mode == &hsb_clk_mode)
2252                         hsb_mask |= 1 << clk->index;
2253                 else if (clk->mode == &pba_clk_mode)
2254                         pba_mask |= 1 << clk->index;
2255                 else if (clk->mode == &pbb_clk_mode)
2256                         pbb_mask |= 1 << clk->index;
2257         }
2258
2259         pm_writel(CPU_MASK, cpu_mask);
2260         pm_writel(HSB_MASK, hsb_mask);
2261         pm_writel(PBA_MASK, pba_mask);
2262         pm_writel(PBB_MASK, pbb_mask);
2263
2264         /* Initialize the port muxes */
2265         at32_init_pio(&pio0_device);
2266         at32_init_pio(&pio1_device);
2267         at32_init_pio(&pio2_device);
2268         at32_init_pio(&pio3_device);
2269         at32_init_pio(&pio4_device);
2270 }
2271
2272 struct gen_pool *sram_pool;
2273
2274 static int __init sram_init(void)
2275 {
2276         struct gen_pool *pool;
2277
2278         /* 1KiB granularity */
2279         pool = gen_pool_create(10, -1);
2280         if (!pool)
2281                 goto fail;
2282
2283         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2284                 goto err_pool_add;
2285
2286         sram_pool = pool;
2287         return 0;
2288
2289 err_pool_add:
2290         gen_pool_destroy(pool);
2291 fail:
2292         pr_err("Failed to create SRAM pool\n");
2293         return -ENOMEM;
2294 }
2295 core_initcall(sram_init);