2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/spi/spi.h>
15 #include <linux/usb/atmel_usba_udc.h>
20 #include <asm/arch/at32ap700x.h>
21 #include <asm/arch/board.h>
22 #include <asm/arch/portmux.h>
24 #include <video/atmel_lcdc.h>
35 .end = base + 0x3ff, \
36 .flags = IORESOURCE_MEM, \
42 .flags = IORESOURCE_IRQ, \
44 #define NAMED_IRQ(num, _name) \
49 .flags = IORESOURCE_IRQ, \
52 /* REVISIT these assume *every* device supports DMA, but several
53 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
55 #define DEFINE_DEV(_name, _id) \
56 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
57 static struct platform_device _name##_id##_device = { \
61 .dma_mask = &_name##_id##_dma_mask, \
62 .coherent_dma_mask = DMA_32BIT_MASK, \
64 .resource = _name##_id##_resource, \
65 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
67 #define DEFINE_DEV_DATA(_name, _id) \
68 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
69 static struct platform_device _name##_id##_device = { \
73 .dma_mask = &_name##_id##_dma_mask, \
74 .platform_data = &_name##_id##_data, \
75 .coherent_dma_mask = DMA_32BIT_MASK, \
77 .resource = _name##_id##_resource, \
78 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
81 #define select_peripheral(pin, periph, flags) \
82 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
84 #define DEV_CLK(_name, devname, bus, _index) \
85 static struct clk devname##_##_name = { \
87 .dev = &devname##_device.dev, \
88 .parent = &bus##_clk, \
89 .mode = bus##_clk_mode, \
90 .get_rate = bus##_clk_get_rate, \
94 static DEFINE_SPINLOCK(pm_lock);
96 static struct clk osc0;
97 static struct clk osc1;
99 static unsigned long osc_get_rate(struct clk *clk)
101 return at32_board_osc_rates[clk->index];
104 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
106 unsigned long div, mul, rate;
108 div = PM_BFEXT(PLLDIV, control) + 1;
109 mul = PM_BFEXT(PLLMUL, control) + 1;
111 rate = clk->parent->get_rate(clk->parent);
112 rate = (rate + div / 2) / div;
118 static long pll_set_rate(struct clk *clk, unsigned long rate,
122 unsigned long mul_best_fit = 0;
124 unsigned long div_min;
125 unsigned long div_max;
126 unsigned long div_best_fit = 0;
128 unsigned long pll_in;
129 unsigned long actual = 0;
130 unsigned long rate_error;
131 unsigned long rate_error_prev = ~0UL;
134 /* Rate must be between 80 MHz and 200 Mhz. */
135 if (rate < 80000000UL || rate > 200000000UL)
138 ctrl = PM_BF(PLLOPT, 4);
139 base = clk->parent->get_rate(clk->parent);
141 /* PLL input frequency must be between 6 MHz and 32 MHz. */
142 div_min = DIV_ROUND_UP(base, 32000000UL);
143 div_max = base / 6000000UL;
145 if (div_max < div_min)
148 for (div = div_min; div <= div_max; div++) {
149 pll_in = (base + div / 2) / div;
150 mul = (rate + pll_in / 2) / pll_in;
155 actual = pll_in * mul;
156 rate_error = abs(actual - rate);
158 if (rate_error < rate_error_prev) {
161 rate_error_prev = rate_error;
168 if (div_best_fit == 0)
171 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
172 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
173 ctrl |= PM_BF(PLLCOUNT, 16);
175 if (clk->parent == &osc1)
176 ctrl |= PM_BIT(PLLOSC);
183 static unsigned long pll0_get_rate(struct clk *clk)
187 control = pm_readl(PLL0);
189 return pll_get_rate(clk, control);
192 static void pll1_mode(struct clk *clk, int enabled)
194 unsigned long timeout;
198 ctrl = pm_readl(PLL1);
201 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
202 pr_debug("clk %s: failed to enable, rate not set\n",
207 ctrl |= PM_BIT(PLLEN);
208 pm_writel(PLL1, ctrl);
210 /* Wait for PLL lock. */
211 for (timeout = 10000; timeout; timeout--) {
212 status = pm_readl(ISR);
213 if (status & PM_BIT(LOCK1))
218 if (!(status & PM_BIT(LOCK1)))
219 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
222 ctrl &= ~PM_BIT(PLLEN);
223 pm_writel(PLL1, ctrl);
227 static unsigned long pll1_get_rate(struct clk *clk)
231 control = pm_readl(PLL1);
233 return pll_get_rate(clk, control);
236 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
239 unsigned long actual_rate;
241 actual_rate = pll_set_rate(clk, rate, &ctrl);
244 if (actual_rate != rate)
248 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
249 clk->name, rate, actual_rate);
250 pm_writel(PLL1, ctrl);
256 static int pll1_set_parent(struct clk *clk, struct clk *parent)
263 ctrl = pm_readl(PLL1);
264 WARN_ON(ctrl & PM_BIT(PLLEN));
267 ctrl &= ~PM_BIT(PLLOSC);
268 else if (parent == &osc1)
269 ctrl |= PM_BIT(PLLOSC);
273 pm_writel(PLL1, ctrl);
274 clk->parent = parent;
280 * The AT32AP7000 has five primary clock sources: One 32kHz
281 * oscillator, two crystal oscillators and two PLLs.
283 static struct clk osc32k = {
285 .get_rate = osc_get_rate,
289 static struct clk osc0 = {
291 .get_rate = osc_get_rate,
295 static struct clk osc1 = {
297 .get_rate = osc_get_rate,
300 static struct clk pll0 = {
302 .get_rate = pll0_get_rate,
305 static struct clk pll1 = {
308 .get_rate = pll1_get_rate,
309 .set_rate = pll1_set_rate,
310 .set_parent = pll1_set_parent,
315 * The main clock can be either osc0 or pll0. The boot loader may
316 * have chosen one for us, so we don't really know which one until we
317 * have a look at the SM.
319 static struct clk *main_clock;
322 * Synchronous clocks are generated from the main clock. The clocks
323 * must satisfy the constraint
324 * fCPU >= fHSB >= fPB
325 * i.e. each clock must not be faster than its parent.
327 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
329 return main_clock->get_rate(main_clock) >> shift;
332 static void cpu_clk_mode(struct clk *clk, int enabled)
337 spin_lock_irqsave(&pm_lock, flags);
338 mask = pm_readl(CPU_MASK);
340 mask |= 1 << clk->index;
342 mask &= ~(1 << clk->index);
343 pm_writel(CPU_MASK, mask);
344 spin_unlock_irqrestore(&pm_lock, flags);
347 static unsigned long cpu_clk_get_rate(struct clk *clk)
349 unsigned long cksel, shift = 0;
351 cksel = pm_readl(CKSEL);
352 if (cksel & PM_BIT(CPUDIV))
353 shift = PM_BFEXT(CPUSEL, cksel) + 1;
355 return bus_clk_get_rate(clk, shift);
358 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
361 unsigned long parent_rate, child_div, actual_rate, div;
363 parent_rate = clk->parent->get_rate(clk->parent);
364 control = pm_readl(CKSEL);
366 if (control & PM_BIT(HSBDIV))
367 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
371 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
372 actual_rate = parent_rate;
373 control &= ~PM_BIT(CPUDIV);
376 div = (parent_rate + rate / 2) / rate;
379 cpusel = (div > 1) ? (fls(div) - 2) : 0;
380 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
381 actual_rate = parent_rate / (1 << (cpusel + 1));
384 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
385 clk->name, rate, actual_rate);
388 pm_writel(CKSEL, control);
393 static void hsb_clk_mode(struct clk *clk, int enabled)
398 spin_lock_irqsave(&pm_lock, flags);
399 mask = pm_readl(HSB_MASK);
401 mask |= 1 << clk->index;
403 mask &= ~(1 << clk->index);
404 pm_writel(HSB_MASK, mask);
405 spin_unlock_irqrestore(&pm_lock, flags);
408 static unsigned long hsb_clk_get_rate(struct clk *clk)
410 unsigned long cksel, shift = 0;
412 cksel = pm_readl(CKSEL);
413 if (cksel & PM_BIT(HSBDIV))
414 shift = PM_BFEXT(HSBSEL, cksel) + 1;
416 return bus_clk_get_rate(clk, shift);
419 static void pba_clk_mode(struct clk *clk, int enabled)
424 spin_lock_irqsave(&pm_lock, flags);
425 mask = pm_readl(PBA_MASK);
427 mask |= 1 << clk->index;
429 mask &= ~(1 << clk->index);
430 pm_writel(PBA_MASK, mask);
431 spin_unlock_irqrestore(&pm_lock, flags);
434 static unsigned long pba_clk_get_rate(struct clk *clk)
436 unsigned long cksel, shift = 0;
438 cksel = pm_readl(CKSEL);
439 if (cksel & PM_BIT(PBADIV))
440 shift = PM_BFEXT(PBASEL, cksel) + 1;
442 return bus_clk_get_rate(clk, shift);
445 static void pbb_clk_mode(struct clk *clk, int enabled)
450 spin_lock_irqsave(&pm_lock, flags);
451 mask = pm_readl(PBB_MASK);
453 mask |= 1 << clk->index;
455 mask &= ~(1 << clk->index);
456 pm_writel(PBB_MASK, mask);
457 spin_unlock_irqrestore(&pm_lock, flags);
460 static unsigned long pbb_clk_get_rate(struct clk *clk)
462 unsigned long cksel, shift = 0;
464 cksel = pm_readl(CKSEL);
465 if (cksel & PM_BIT(PBBDIV))
466 shift = PM_BFEXT(PBBSEL, cksel) + 1;
468 return bus_clk_get_rate(clk, shift);
471 static struct clk cpu_clk = {
473 .get_rate = cpu_clk_get_rate,
474 .set_rate = cpu_clk_set_rate,
477 static struct clk hsb_clk = {
480 .get_rate = hsb_clk_get_rate,
482 static struct clk pba_clk = {
485 .mode = hsb_clk_mode,
486 .get_rate = pba_clk_get_rate,
489 static struct clk pbb_clk = {
492 .mode = hsb_clk_mode,
493 .get_rate = pbb_clk_get_rate,
498 /* --------------------------------------------------------------------
499 * Generic Clock operations
500 * -------------------------------------------------------------------- */
502 static void genclk_mode(struct clk *clk, int enabled)
506 control = pm_readl(GCCTRL(clk->index));
508 control |= PM_BIT(CEN);
510 control &= ~PM_BIT(CEN);
511 pm_writel(GCCTRL(clk->index), control);
514 static unsigned long genclk_get_rate(struct clk *clk)
517 unsigned long div = 1;
519 control = pm_readl(GCCTRL(clk->index));
520 if (control & PM_BIT(DIVEN))
521 div = 2 * (PM_BFEXT(DIV, control) + 1);
523 return clk->parent->get_rate(clk->parent) / div;
526 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
529 unsigned long parent_rate, actual_rate, div;
531 parent_rate = clk->parent->get_rate(clk->parent);
532 control = pm_readl(GCCTRL(clk->index));
534 if (rate > 3 * parent_rate / 4) {
535 actual_rate = parent_rate;
536 control &= ~PM_BIT(DIVEN);
538 div = (parent_rate + rate) / (2 * rate) - 1;
539 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
540 actual_rate = parent_rate / (2 * (div + 1));
543 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
544 clk->name, rate, actual_rate);
547 pm_writel(GCCTRL(clk->index), control);
552 int genclk_set_parent(struct clk *clk, struct clk *parent)
556 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
557 clk->name, parent->name, clk->parent->name);
559 control = pm_readl(GCCTRL(clk->index));
561 if (parent == &osc1 || parent == &pll1)
562 control |= PM_BIT(OSCSEL);
563 else if (parent == &osc0 || parent == &pll0)
564 control &= ~PM_BIT(OSCSEL);
568 if (parent == &pll0 || parent == &pll1)
569 control |= PM_BIT(PLLSEL);
571 control &= ~PM_BIT(PLLSEL);
573 pm_writel(GCCTRL(clk->index), control);
574 clk->parent = parent;
579 static void __init genclk_init_parent(struct clk *clk)
584 BUG_ON(clk->index > 7);
586 control = pm_readl(GCCTRL(clk->index));
587 if (control & PM_BIT(OSCSEL))
588 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
590 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
592 clk->parent = parent;
595 /* --------------------------------------------------------------------
597 * -------------------------------------------------------------------- */
598 static struct resource at32_pm0_resource[] = {
602 .flags = IORESOURCE_MEM,
607 static struct resource at32ap700x_rtc0_resource[] = {
611 .flags = IORESOURCE_MEM,
616 static struct resource at32_wdt0_resource[] = {
620 .flags = IORESOURCE_MEM,
624 static struct resource at32_eic0_resource[] = {
628 .flags = IORESOURCE_MEM,
633 DEFINE_DEV(at32_pm, 0);
634 DEFINE_DEV(at32ap700x_rtc, 0);
635 DEFINE_DEV(at32_wdt, 0);
636 DEFINE_DEV(at32_eic, 0);
639 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
642 static struct clk at32_pm_pclk = {
644 .dev = &at32_pm0_device.dev,
646 .mode = pbb_clk_mode,
647 .get_rate = pbb_clk_get_rate,
652 static struct resource intc0_resource[] = {
655 struct platform_device at32_intc0_device = {
658 .resource = intc0_resource,
659 .num_resources = ARRAY_SIZE(intc0_resource),
661 DEV_CLK(pclk, at32_intc0, pbb, 1);
663 static struct clk ebi_clk = {
666 .mode = hsb_clk_mode,
667 .get_rate = hsb_clk_get_rate,
670 static struct clk hramc_clk = {
673 .mode = hsb_clk_mode,
674 .get_rate = hsb_clk_get_rate,
679 static struct resource smc0_resource[] = {
683 DEV_CLK(pclk, smc0, pbb, 13);
684 DEV_CLK(mck, smc0, hsb, 0);
686 static struct platform_device pdc_device = {
690 DEV_CLK(hclk, pdc, hsb, 4);
691 DEV_CLK(pclk, pdc, pba, 16);
693 static struct clk pico_clk = {
696 .mode = cpu_clk_mode,
697 .get_rate = cpu_clk_get_rate,
701 static struct resource dmaca0_resource[] = {
705 .flags = IORESOURCE_MEM,
709 DEFINE_DEV(dmaca, 0);
710 DEV_CLK(hclk, dmaca0, hsb, 10);
712 /* --------------------------------------------------------------------
714 * -------------------------------------------------------------------- */
716 static struct clk hmatrix_clk = {
717 .name = "hmatrix_clk",
719 .mode = pbb_clk_mode,
720 .get_rate = pbb_clk_get_rate,
724 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
726 #define hmatrix_readl(reg) \
727 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
728 #define hmatrix_writel(reg,value) \
729 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
732 * Set bits in the HMATRIX Special Function Register (SFR) used by the
733 * External Bus Interface (EBI). This can be used to enable special
734 * features like CompactFlash support, NAND Flash support, etc. on
735 * certain chipselects.
737 static inline void set_ebi_sfr_bits(u32 mask)
741 clk_enable(&hmatrix_clk);
742 sfr = hmatrix_readl(SFR4);
744 hmatrix_writel(SFR4, sfr);
745 clk_disable(&hmatrix_clk);
748 /* --------------------------------------------------------------------
750 * -------------------------------------------------------------------- */
752 static struct resource at32_tcb0_resource[] = {
756 static struct platform_device at32_tcb0_device = {
759 .resource = at32_tcb0_resource,
760 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
762 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
764 static struct resource at32_tcb1_resource[] = {
768 static struct platform_device at32_tcb1_device = {
771 .resource = at32_tcb1_resource,
772 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
774 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
776 /* --------------------------------------------------------------------
778 * -------------------------------------------------------------------- */
780 static struct resource pio0_resource[] = {
785 DEV_CLK(mck, pio0, pba, 10);
787 static struct resource pio1_resource[] = {
792 DEV_CLK(mck, pio1, pba, 11);
794 static struct resource pio2_resource[] = {
799 DEV_CLK(mck, pio2, pba, 12);
801 static struct resource pio3_resource[] = {
806 DEV_CLK(mck, pio3, pba, 13);
808 static struct resource pio4_resource[] = {
813 DEV_CLK(mck, pio4, pba, 14);
815 void __init at32_add_system_devices(void)
817 platform_device_register(&at32_pm0_device);
818 platform_device_register(&at32_intc0_device);
819 platform_device_register(&at32ap700x_rtc0_device);
820 platform_device_register(&at32_wdt0_device);
821 platform_device_register(&at32_eic0_device);
822 platform_device_register(&smc0_device);
823 platform_device_register(&pdc_device);
824 platform_device_register(&dmaca0_device);
826 platform_device_register(&at32_tcb0_device);
827 platform_device_register(&at32_tcb1_device);
829 platform_device_register(&pio0_device);
830 platform_device_register(&pio1_device);
831 platform_device_register(&pio2_device);
832 platform_device_register(&pio3_device);
833 platform_device_register(&pio4_device);
836 /* --------------------------------------------------------------------
838 * -------------------------------------------------------------------- */
839 static struct resource atmel_psif0_resource[] __initdata = {
843 .flags = IORESOURCE_MEM,
847 static struct clk atmel_psif0_pclk = {
850 .mode = pba_clk_mode,
851 .get_rate = pba_clk_get_rate,
855 static struct resource atmel_psif1_resource[] __initdata = {
859 .flags = IORESOURCE_MEM,
863 static struct clk atmel_psif1_pclk = {
866 .mode = pba_clk_mode,
867 .get_rate = pba_clk_get_rate,
871 struct platform_device *__init at32_add_device_psif(unsigned int id)
873 struct platform_device *pdev;
875 if (!(id == 0 || id == 1))
878 pdev = platform_device_alloc("atmel_psif", id);
884 if (platform_device_add_resources(pdev, atmel_psif0_resource,
885 ARRAY_SIZE(atmel_psif0_resource)))
886 goto err_add_resources;
887 atmel_psif0_pclk.dev = &pdev->dev;
888 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
889 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
892 if (platform_device_add_resources(pdev, atmel_psif1_resource,
893 ARRAY_SIZE(atmel_psif1_resource)))
894 goto err_add_resources;
895 atmel_psif1_pclk.dev = &pdev->dev;
896 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
897 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
903 platform_device_add(pdev);
907 platform_device_put(pdev);
911 /* --------------------------------------------------------------------
913 * -------------------------------------------------------------------- */
915 static struct atmel_uart_data atmel_usart0_data = {
919 static struct resource atmel_usart0_resource[] = {
923 DEFINE_DEV_DATA(atmel_usart, 0);
924 DEV_CLK(usart, atmel_usart0, pba, 3);
926 static struct atmel_uart_data atmel_usart1_data = {
930 static struct resource atmel_usart1_resource[] = {
934 DEFINE_DEV_DATA(atmel_usart, 1);
935 DEV_CLK(usart, atmel_usart1, pba, 4);
937 static struct atmel_uart_data atmel_usart2_data = {
941 static struct resource atmel_usart2_resource[] = {
945 DEFINE_DEV_DATA(atmel_usart, 2);
946 DEV_CLK(usart, atmel_usart2, pba, 5);
948 static struct atmel_uart_data atmel_usart3_data = {
952 static struct resource atmel_usart3_resource[] = {
956 DEFINE_DEV_DATA(atmel_usart, 3);
957 DEV_CLK(usart, atmel_usart3, pba, 6);
959 static inline void configure_usart0_pins(void)
961 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
962 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
965 static inline void configure_usart1_pins(void)
967 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
968 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
971 static inline void configure_usart2_pins(void)
973 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
974 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
977 static inline void configure_usart3_pins(void)
979 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
980 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
983 static struct platform_device *__initdata at32_usarts[4];
985 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
987 struct platform_device *pdev;
991 pdev = &atmel_usart0_device;
992 configure_usart0_pins();
995 pdev = &atmel_usart1_device;
996 configure_usart1_pins();
999 pdev = &atmel_usart2_device;
1000 configure_usart2_pins();
1003 pdev = &atmel_usart3_device;
1004 configure_usart3_pins();
1010 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1011 /* Addresses in the P4 segment are permanently mapped 1:1 */
1012 struct atmel_uart_data *data = pdev->dev.platform_data;
1013 data->regs = (void __iomem *)pdev->resource[0].start;
1017 at32_usarts[line] = pdev;
1020 struct platform_device *__init at32_add_device_usart(unsigned int id)
1022 platform_device_register(at32_usarts[id]);
1023 return at32_usarts[id];
1026 struct platform_device *atmel_default_console_device;
1028 void __init at32_setup_serial_console(unsigned int usart_id)
1030 atmel_default_console_device = at32_usarts[usart_id];
1033 /* --------------------------------------------------------------------
1035 * -------------------------------------------------------------------- */
1037 #ifdef CONFIG_CPU_AT32AP7000
1038 static struct eth_platform_data macb0_data;
1039 static struct resource macb0_resource[] = {
1043 DEFINE_DEV_DATA(macb, 0);
1044 DEV_CLK(hclk, macb0, hsb, 8);
1045 DEV_CLK(pclk, macb0, pbb, 6);
1047 static struct eth_platform_data macb1_data;
1048 static struct resource macb1_resource[] = {
1052 DEFINE_DEV_DATA(macb, 1);
1053 DEV_CLK(hclk, macb1, hsb, 9);
1054 DEV_CLK(pclk, macb1, pbb, 7);
1056 struct platform_device *__init
1057 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1059 struct platform_device *pdev;
1063 pdev = &macb0_device;
1065 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
1066 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
1067 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
1068 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
1069 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
1070 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1071 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1072 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1073 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
1074 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1076 if (!data->is_rmii) {
1077 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
1078 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
1079 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
1080 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
1081 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
1082 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1083 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1084 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1085 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
1090 pdev = &macb1_device;
1092 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
1093 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
1094 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
1095 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
1096 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
1097 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
1098 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
1099 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
1100 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
1101 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
1103 if (!data->is_rmii) {
1104 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
1105 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
1106 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1107 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1108 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1109 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1110 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1111 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1112 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
1120 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1121 platform_device_register(pdev);
1127 /* --------------------------------------------------------------------
1129 * -------------------------------------------------------------------- */
1130 static struct resource atmel_spi0_resource[] = {
1134 DEFINE_DEV(atmel_spi, 0);
1135 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1137 static struct resource atmel_spi1_resource[] = {
1141 DEFINE_DEV(atmel_spi, 1);
1142 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1145 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1146 unsigned int n, const u8 *pins)
1148 unsigned int pin, mode;
1150 for (; n; n--, b++) {
1151 b->bus_num = bus_num;
1152 if (b->chip_select >= 4)
1154 pin = (unsigned)b->controller_data;
1156 pin = pins[b->chip_select];
1157 b->controller_data = (void *)pin;
1159 mode = AT32_GPIOF_OUTPUT;
1160 if (!(b->mode & SPI_CS_HIGH))
1161 mode |= AT32_GPIOF_HIGH;
1162 at32_select_gpio(pin, mode);
1166 struct platform_device *__init
1167 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1170 * Manage the chipselects as GPIOs, normally using the same pins
1171 * the SPI controller expects; but boards can use other pins.
1173 static u8 __initdata spi0_pins[] =
1174 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1175 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1176 static u8 __initdata spi1_pins[] =
1177 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1178 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1179 struct platform_device *pdev;
1183 pdev = &atmel_spi0_device;
1184 /* pullup MISO so a level is always defined */
1185 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1186 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1187 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1188 at32_spi_setup_slaves(0, b, n, spi0_pins);
1192 pdev = &atmel_spi1_device;
1193 /* pullup MISO so a level is always defined */
1194 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1195 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1196 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1197 at32_spi_setup_slaves(1, b, n, spi1_pins);
1204 spi_register_board_info(b, n);
1205 platform_device_register(pdev);
1209 /* --------------------------------------------------------------------
1211 * -------------------------------------------------------------------- */
1212 static struct resource atmel_twi0_resource[] __initdata = {
1216 static struct clk atmel_twi0_pclk = {
1219 .mode = pba_clk_mode,
1220 .get_rate = pba_clk_get_rate,
1224 struct platform_device *__init at32_add_device_twi(unsigned int id,
1225 struct i2c_board_info *b,
1228 struct platform_device *pdev;
1233 pdev = platform_device_alloc("atmel_twi", id);
1237 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1238 ARRAY_SIZE(atmel_twi0_resource)))
1239 goto err_add_resources;
1241 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1242 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1244 atmel_twi0_pclk.dev = &pdev->dev;
1247 i2c_register_board_info(id, b, n);
1249 platform_device_add(pdev);
1253 platform_device_put(pdev);
1257 /* --------------------------------------------------------------------
1259 * -------------------------------------------------------------------- */
1260 static struct resource atmel_mci0_resource[] __initdata = {
1264 static struct clk atmel_mci0_pclk = {
1267 .mode = pbb_clk_mode,
1268 .get_rate = pbb_clk_get_rate,
1272 struct platform_device *__init at32_add_device_mci(unsigned int id)
1274 struct platform_device *pdev;
1279 pdev = platform_device_alloc("atmel_mci", id);
1283 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1284 ARRAY_SIZE(atmel_mci0_resource)))
1285 goto err_add_resources;
1287 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1288 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1289 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1290 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1291 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1292 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1294 atmel_mci0_pclk.dev = &pdev->dev;
1296 platform_device_add(pdev);
1300 platform_device_put(pdev);
1304 /* --------------------------------------------------------------------
1306 * -------------------------------------------------------------------- */
1307 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1308 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1309 static struct resource atmel_lcdfb0_resource[] = {
1311 .start = 0xff000000,
1313 .flags = IORESOURCE_MEM,
1317 /* Placeholder for pre-allocated fb memory */
1318 .start = 0x00000000,
1323 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1324 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1325 static struct clk atmel_lcdfb0_pixclk = {
1327 .dev = &atmel_lcdfb0_device.dev,
1328 .mode = genclk_mode,
1329 .get_rate = genclk_get_rate,
1330 .set_rate = genclk_set_rate,
1331 .set_parent = genclk_set_parent,
1335 struct platform_device *__init
1336 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1337 unsigned long fbmem_start, unsigned long fbmem_len,
1338 unsigned int pin_config)
1340 struct platform_device *pdev;
1341 struct atmel_lcdfb_info *info;
1342 struct fb_monspecs *monspecs;
1343 struct fb_videomode *modedb;
1344 unsigned int modedb_size;
1347 * Do a deep copy of the fb data, monspecs and modedb. Make
1348 * sure all allocations are done before setting up the
1351 monspecs = kmemdup(data->default_monspecs,
1352 sizeof(struct fb_monspecs), GFP_KERNEL);
1356 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1357 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1359 goto err_dup_modedb;
1360 monspecs->modedb = modedb;
1364 pdev = &atmel_lcdfb0_device;
1366 switch (pin_config) {
1368 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1369 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1370 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1371 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1372 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1373 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1374 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1375 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1376 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1377 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1378 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1379 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1380 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1381 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1382 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1383 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1384 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1385 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1386 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1387 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1388 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1389 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1390 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1391 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1392 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1393 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1394 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1395 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1396 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1397 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1398 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1401 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1402 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1403 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1404 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1405 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1406 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1407 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1408 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1409 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1410 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1411 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1412 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1413 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1414 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1415 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1416 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1417 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1418 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1419 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1420 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1421 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1422 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1423 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1424 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1425 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1426 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1427 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1428 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1429 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1430 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1431 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1434 goto err_invalid_id;
1437 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1438 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1442 goto err_invalid_id;
1446 pdev->resource[2].start = fbmem_start;
1447 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1448 pdev->resource[2].flags = IORESOURCE_MEM;
1451 info = pdev->dev.platform_data;
1452 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1453 info->default_monspecs = monspecs;
1455 platform_device_register(pdev);
1466 /* --------------------------------------------------------------------
1468 * -------------------------------------------------------------------- */
1469 static struct resource atmel_pwm0_resource[] __initdata = {
1473 static struct clk atmel_pwm0_mck = {
1476 .mode = pbb_clk_mode,
1477 .get_rate = pbb_clk_get_rate,
1481 struct platform_device *__init at32_add_device_pwm(u32 mask)
1483 struct platform_device *pdev;
1488 pdev = platform_device_alloc("atmel_pwm", 0);
1492 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1493 ARRAY_SIZE(atmel_pwm0_resource)))
1496 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1499 if (mask & (1 << 0))
1500 select_peripheral(PA(28), PERIPH_A, 0);
1501 if (mask & (1 << 1))
1502 select_peripheral(PA(29), PERIPH_A, 0);
1503 if (mask & (1 << 2))
1504 select_peripheral(PA(21), PERIPH_B, 0);
1505 if (mask & (1 << 3))
1506 select_peripheral(PA(22), PERIPH_B, 0);
1508 atmel_pwm0_mck.dev = &pdev->dev;
1510 platform_device_add(pdev);
1515 platform_device_put(pdev);
1519 /* --------------------------------------------------------------------
1521 * -------------------------------------------------------------------- */
1522 static struct resource ssc0_resource[] = {
1527 DEV_CLK(pclk, ssc0, pba, 7);
1529 static struct resource ssc1_resource[] = {
1534 DEV_CLK(pclk, ssc1, pba, 8);
1536 static struct resource ssc2_resource[] = {
1541 DEV_CLK(pclk, ssc2, pba, 9);
1543 struct platform_device *__init
1544 at32_add_device_ssc(unsigned int id, unsigned int flags)
1546 struct platform_device *pdev;
1550 pdev = &ssc0_device;
1551 if (flags & ATMEL_SSC_RF)
1552 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1553 if (flags & ATMEL_SSC_RK)
1554 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1555 if (flags & ATMEL_SSC_TK)
1556 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1557 if (flags & ATMEL_SSC_TF)
1558 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1559 if (flags & ATMEL_SSC_TD)
1560 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1561 if (flags & ATMEL_SSC_RD)
1562 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1565 pdev = &ssc1_device;
1566 if (flags & ATMEL_SSC_RF)
1567 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1568 if (flags & ATMEL_SSC_RK)
1569 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1570 if (flags & ATMEL_SSC_TK)
1571 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1572 if (flags & ATMEL_SSC_TF)
1573 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1574 if (flags & ATMEL_SSC_TD)
1575 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1576 if (flags & ATMEL_SSC_RD)
1577 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1580 pdev = &ssc2_device;
1581 if (flags & ATMEL_SSC_TD)
1582 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1583 if (flags & ATMEL_SSC_RD)
1584 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1585 if (flags & ATMEL_SSC_TK)
1586 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1587 if (flags & ATMEL_SSC_TF)
1588 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1589 if (flags & ATMEL_SSC_RF)
1590 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1591 if (flags & ATMEL_SSC_RK)
1592 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1598 platform_device_register(pdev);
1602 /* --------------------------------------------------------------------
1603 * USB Device Controller
1604 * -------------------------------------------------------------------- */
1605 static struct resource usba0_resource[] __initdata = {
1607 .start = 0xff300000,
1609 .flags = IORESOURCE_MEM,
1611 .start = 0xfff03000,
1613 .flags = IORESOURCE_MEM,
1617 static struct clk usba0_pclk = {
1620 .mode = pbb_clk_mode,
1621 .get_rate = pbb_clk_get_rate,
1624 static struct clk usba0_hclk = {
1627 .mode = hsb_clk_mode,
1628 .get_rate = hsb_clk_get_rate,
1632 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1636 .fifo_size = maxpkt, \
1637 .nr_banks = maxbk, \
1642 static struct usba_ep_data at32_usba_ep[] __initdata = {
1643 EP("ep0", 0, 64, 1, 0, 0),
1644 EP("ep1", 1, 512, 2, 1, 1),
1645 EP("ep2", 2, 512, 2, 1, 1),
1646 EP("ep3-int", 3, 64, 3, 1, 0),
1647 EP("ep4-int", 4, 64, 3, 1, 0),
1648 EP("ep5", 5, 1024, 3, 1, 1),
1649 EP("ep6", 6, 1024, 3, 1, 1),
1654 struct platform_device *__init
1655 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1658 * pdata doesn't have room for any endpoints, so we need to
1659 * append room for the ones we need right after it.
1662 struct usba_platform_data pdata;
1663 struct usba_ep_data ep[7];
1665 struct platform_device *pdev;
1670 pdev = platform_device_alloc("atmel_usba_udc", 0);
1674 if (platform_device_add_resources(pdev, usba0_resource,
1675 ARRAY_SIZE(usba0_resource)))
1679 usba_data.pdata.vbus_pin = data->vbus_pin;
1681 usba_data.pdata.vbus_pin = -EINVAL;
1683 data = &usba_data.pdata;
1684 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1685 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1687 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1690 if (data->vbus_pin >= 0)
1691 at32_select_gpio(data->vbus_pin, 0);
1693 usba0_pclk.dev = &pdev->dev;
1694 usba0_hclk.dev = &pdev->dev;
1696 platform_device_add(pdev);
1701 platform_device_put(pdev);
1705 /* --------------------------------------------------------------------
1706 * IDE / CompactFlash
1707 * -------------------------------------------------------------------- */
1708 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1709 static struct resource at32_smc_cs4_resource[] __initdata = {
1711 .start = 0x04000000,
1713 .flags = IORESOURCE_MEM,
1715 IRQ(~0UL), /* Magic IRQ will be overridden */
1717 static struct resource at32_smc_cs5_resource[] __initdata = {
1719 .start = 0x20000000,
1721 .flags = IORESOURCE_MEM,
1723 IRQ(~0UL), /* Magic IRQ will be overridden */
1726 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1727 unsigned int cs, unsigned int extint)
1729 static unsigned int extint_pin_map[4] __initdata = {
1735 static bool common_pins_initialized __initdata = false;
1736 unsigned int extint_pin;
1739 if (extint >= ARRAY_SIZE(extint_pin_map))
1741 extint_pin = extint_pin_map[extint];
1745 ret = platform_device_add_resources(pdev,
1746 at32_smc_cs4_resource,
1747 ARRAY_SIZE(at32_smc_cs4_resource));
1751 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1752 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1755 ret = platform_device_add_resources(pdev,
1756 at32_smc_cs5_resource,
1757 ARRAY_SIZE(at32_smc_cs5_resource));
1761 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1762 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1768 if (!common_pins_initialized) {
1769 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1770 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1771 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1772 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1773 common_pins_initialized = true;
1776 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1778 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1779 pdev->resource[1].end = pdev->resource[1].start;
1784 struct platform_device *__init
1785 at32_add_device_ide(unsigned int id, unsigned int extint,
1786 struct ide_platform_data *data)
1788 struct platform_device *pdev;
1790 pdev = platform_device_alloc("at32_ide", id);
1794 if (platform_device_add_data(pdev, data,
1795 sizeof(struct ide_platform_data)))
1798 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1801 platform_device_add(pdev);
1805 platform_device_put(pdev);
1809 struct platform_device *__init
1810 at32_add_device_cf(unsigned int id, unsigned int extint,
1811 struct cf_platform_data *data)
1813 struct platform_device *pdev;
1815 pdev = platform_device_alloc("at32_cf", id);
1819 if (platform_device_add_data(pdev, data,
1820 sizeof(struct cf_platform_data)))
1823 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1826 if (data->detect_pin != GPIO_PIN_NONE)
1827 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1828 if (data->reset_pin != GPIO_PIN_NONE)
1829 at32_select_gpio(data->reset_pin, 0);
1830 if (data->vcc_pin != GPIO_PIN_NONE)
1831 at32_select_gpio(data->vcc_pin, 0);
1832 /* READY is used as extint, so we can't select it as gpio */
1834 platform_device_add(pdev);
1838 platform_device_put(pdev);
1843 /* --------------------------------------------------------------------
1845 * -------------------------------------------------------------------- */
1846 static struct resource atmel_ac97c0_resource[] __initdata = {
1850 static struct clk atmel_ac97c0_pclk = {
1853 .mode = pbb_clk_mode,
1854 .get_rate = pbb_clk_get_rate,
1858 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1860 struct platform_device *pdev;
1865 pdev = platform_device_alloc("atmel_ac97c", id);
1869 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1870 ARRAY_SIZE(atmel_ac97c0_resource)))
1871 goto err_add_resources;
1873 select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1874 select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1875 select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1876 select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1878 atmel_ac97c0_pclk.dev = &pdev->dev;
1880 platform_device_add(pdev);
1884 platform_device_put(pdev);
1888 /* --------------------------------------------------------------------
1890 * -------------------------------------------------------------------- */
1891 static struct resource abdac0_resource[] __initdata = {
1895 static struct clk abdac0_pclk = {
1898 .mode = pbb_clk_mode,
1899 .get_rate = pbb_clk_get_rate,
1902 static struct clk abdac0_sample_clk = {
1903 .name = "sample_clk",
1904 .mode = genclk_mode,
1905 .get_rate = genclk_get_rate,
1906 .set_rate = genclk_set_rate,
1907 .set_parent = genclk_set_parent,
1911 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1913 struct platform_device *pdev;
1918 pdev = platform_device_alloc("abdac", id);
1922 if (platform_device_add_resources(pdev, abdac0_resource,
1923 ARRAY_SIZE(abdac0_resource)))
1924 goto err_add_resources;
1926 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
1927 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
1928 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
1929 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
1931 abdac0_pclk.dev = &pdev->dev;
1932 abdac0_sample_clk.dev = &pdev->dev;
1934 platform_device_add(pdev);
1938 platform_device_put(pdev);
1942 /* --------------------------------------------------------------------
1944 * -------------------------------------------------------------------- */
1945 static struct clk gclk0 = {
1947 .mode = genclk_mode,
1948 .get_rate = genclk_get_rate,
1949 .set_rate = genclk_set_rate,
1950 .set_parent = genclk_set_parent,
1953 static struct clk gclk1 = {
1955 .mode = genclk_mode,
1956 .get_rate = genclk_get_rate,
1957 .set_rate = genclk_set_rate,
1958 .set_parent = genclk_set_parent,
1961 static struct clk gclk2 = {
1963 .mode = genclk_mode,
1964 .get_rate = genclk_get_rate,
1965 .set_rate = genclk_set_rate,
1966 .set_parent = genclk_set_parent,
1969 static struct clk gclk3 = {
1971 .mode = genclk_mode,
1972 .get_rate = genclk_get_rate,
1973 .set_rate = genclk_set_rate,
1974 .set_parent = genclk_set_parent,
1977 static struct clk gclk4 = {
1979 .mode = genclk_mode,
1980 .get_rate = genclk_get_rate,
1981 .set_rate = genclk_set_rate,
1982 .set_parent = genclk_set_parent,
1986 struct clk *at32_clock_list[] = {
2016 &atmel_usart0_usart,
2017 &atmel_usart1_usart,
2018 &atmel_usart2_usart,
2019 &atmel_usart3_usart,
2021 #if defined(CONFIG_CPU_AT32AP7000)
2027 &atmel_spi0_spi_clk,
2028 &atmel_spi1_spi_clk,
2031 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2033 &atmel_lcdfb0_pixclk,
2049 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2051 void __init setup_platform(void)
2053 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2056 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2058 cpu_clk.parent = &pll0;
2061 cpu_clk.parent = &osc0;
2064 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2065 pll0.parent = &osc1;
2066 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2067 pll1.parent = &osc1;
2069 genclk_init_parent(&gclk0);
2070 genclk_init_parent(&gclk1);
2071 genclk_init_parent(&gclk2);
2072 genclk_init_parent(&gclk3);
2073 genclk_init_parent(&gclk4);
2074 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2075 genclk_init_parent(&atmel_lcdfb0_pixclk);
2077 genclk_init_parent(&abdac0_sample_clk);
2080 * Turn on all clocks that have at least one user already, and
2081 * turn off everything else. We only do this for module
2082 * clocks, and even though it isn't particularly pretty to
2083 * check the address of the mode function, it should do the
2086 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2087 struct clk *clk = at32_clock_list[i];
2089 if (clk->users == 0)
2092 if (clk->mode == &cpu_clk_mode)
2093 cpu_mask |= 1 << clk->index;
2094 else if (clk->mode == &hsb_clk_mode)
2095 hsb_mask |= 1 << clk->index;
2096 else if (clk->mode == &pba_clk_mode)
2097 pba_mask |= 1 << clk->index;
2098 else if (clk->mode == &pbb_clk_mode)
2099 pbb_mask |= 1 << clk->index;
2102 pm_writel(CPU_MASK, cpu_mask);
2103 pm_writel(HSB_MASK, hsb_mask);
2104 pm_writel(PBA_MASK, pba_mask);
2105 pm_writel(PBB_MASK, pbb_mask);
2107 /* Initialize the port muxes */
2108 at32_init_pio(&pio0_device);
2109 at32_init_pio(&pio1_device);
2110 at32_init_pio(&pio2_device);
2111 at32_init_pio(&pio3_device);
2112 at32_init_pio(&pio4_device);