arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/fb.h>
  11 #include <linux/init.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/usb/atmel_usba_udc.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19
  20 #include <asm/arch/at32ap700x.h>
  21 #include <asm/arch/board.h>
  22 #include <asm/arch/portmux.h>
  23
  24 #include <video/atmel_lcdc.h>
  25
  26 #include "clock.h"
  27 #include "hmatrix.h"
  28 #include "pio.h"
  29 #include "pm.h"
  30
  31
  32 #define PBMEM(base)                                     \
  33         {                                               \
  34                 .start          = base,                 \
  35                 .end            = base + 0x3ff,         \
  36                 .flags          = IORESOURCE_MEM,       \
  37         }
  38 #define IRQ(num)                                        \
  39         {                                               \
  40                 .start          = num,                  \
  41                 .end            = num,                  \
  42                 .flags          = IORESOURCE_IRQ,       \
  43         }
  44 #define NAMED_IRQ(num, _name)                           \
  45         {                                               \
  46                 .start          = num,                  \
  47                 .end            = num,                  \
  48                 .name           = _name,                \
  49                 .flags          = IORESOURCE_IRQ,       \
  50         }
  51
  52 /* REVISIT these assume *every* device supports DMA, but several
  53  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  54  */
  55 #define DEFINE_DEV(_name, _id)                                  \
  56 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  57 static struct platform_device _name##_id##_device = {           \
  58         .name           = #_name,                               \
  59         .id             = _id,                                  \
  60         .dev            = {                                     \
  61                 .dma_mask = &_name##_id##_dma_mask,             \
  62                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  63         },                                                      \
  64         .resource       = _name##_id##_resource,                \
  65         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  66 }
  67 #define DEFINE_DEV_DATA(_name, _id)                             \
  68 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  69 static struct platform_device _name##_id##_device = {           \
  70         .name           = #_name,                               \
  71         .id             = _id,                                  \
  72         .dev            = {                                     \
  73                 .dma_mask = &_name##_id##_dma_mask,             \
  74                 .platform_data  = &_name##_id##_data,           \
  75                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  76         },                                                      \
  77         .resource       = _name##_id##_resource,                \
  78         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  79 }
  80
  81 #define select_peripheral(pin, periph, flags)                   \
  82         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  83
  84 #define DEV_CLK(_name, devname, bus, _index)                    \
  85 static struct clk devname##_##_name = {                         \
  86         .name           = #_name,                               \
  87         .dev            = &devname##_device.dev,                \
  88         .parent         = &bus##_clk,                           \
  89         .mode           = bus##_clk_mode,                       \
  90         .get_rate       = bus##_clk_get_rate,                   \
  91         .index          = _index,                               \
  92 }
  93
  94 static DEFINE_SPINLOCK(pm_lock);
  95
  96 static struct clk osc0;
  97 static struct clk osc1;
  98
  99 static unsigned long osc_get_rate(struct clk *clk)
 100 {
 101         return at32_board_osc_rates[clk->index];
 102 }
 103
 104 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 105 {
 106         unsigned long div, mul, rate;
 107
 108         div = PM_BFEXT(PLLDIV, control) + 1;
 109         mul = PM_BFEXT(PLLMUL, control) + 1;
 110
 111         rate = clk->parent->get_rate(clk->parent);
 112         rate = (rate + div / 2) / div;
 113         rate *= mul;
 114
 115         return rate;
 116 }
 117
 118 static long pll_set_rate(struct clk *clk, unsigned long rate,
 119                          u32 *pll_ctrl)
 120 {
 121         unsigned long mul;
 122         unsigned long mul_best_fit = 0;
 123         unsigned long div;
 124         unsigned long div_min;
 125         unsigned long div_max;
 126         unsigned long div_best_fit = 0;
 127         unsigned long base;
 128         unsigned long pll_in;
 129         unsigned long actual = 0;
 130         unsigned long rate_error;
 131         unsigned long rate_error_prev = ~0UL;
 132         u32 ctrl;
 133
 134         /* Rate must be between 80 MHz and 200 Mhz. */
 135         if (rate < 80000000UL || rate > 200000000UL)
 136                 return -EINVAL;
 137
 138         ctrl = PM_BF(PLLOPT, 4);
 139         base = clk->parent->get_rate(clk->parent);
 140
 141         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 142         div_min = DIV_ROUND_UP(base, 32000000UL);
 143         div_max = base / 6000000UL;
 144
 145         if (div_max < div_min)
 146                 return -EINVAL;
 147
 148         for (div = div_min; div <= div_max; div++) {
 149                 pll_in = (base + div / 2) / div;
 150                 mul = (rate + pll_in / 2) / pll_in;
 151
 152                 if (mul == 0)
 153                         continue;
 154
 155                 actual = pll_in * mul;
 156                 rate_error = abs(actual - rate);
 157
 158                 if (rate_error < rate_error_prev) {
 159                         mul_best_fit = mul;
 160                         div_best_fit = div;
 161                         rate_error_prev = rate_error;
 162                 }
 163
 164                 if (rate_error == 0)
 165                         break;
 166         }
 167
 168         if (div_best_fit == 0)
 169                 return -EINVAL;
 170
 171         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 172         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 173         ctrl |= PM_BF(PLLCOUNT, 16);
 174
 175         if (clk->parent == &osc1)
 176                 ctrl |= PM_BIT(PLLOSC);
 177
 178         *pll_ctrl = ctrl;
 179
 180         return actual;
 181 }
 182
 183 static unsigned long pll0_get_rate(struct clk *clk)
 184 {
 185         u32 control;
 186
 187         control = pm_readl(PLL0);
 188
 189         return pll_get_rate(clk, control);
 190 }
 191
 192 static void pll1_mode(struct clk *clk, int enabled)
 193 {
 194         unsigned long timeout;
 195         u32 status;
 196         u32 ctrl;
 197
 198         ctrl = pm_readl(PLL1);
 199
 200         if (enabled) {
 201                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 202                         pr_debug("clk %s: failed to enable, rate not set\n",
 203                                         clk->name);
 204                         return;
 205                 }
 206
 207                 ctrl |= PM_BIT(PLLEN);
 208                 pm_writel(PLL1, ctrl);
 209
 210                 /* Wait for PLL lock. */
 211                 for (timeout = 10000; timeout; timeout--) {
 212                         status = pm_readl(ISR);
 213                         if (status & PM_BIT(LOCK1))
 214                                 break;
 215                         udelay(10);
 216                 }
 217
 218                 if (!(status & PM_BIT(LOCK1)))
 219                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 220                                         clk->name);
 221         } else {
 222                 ctrl &= ~PM_BIT(PLLEN);
 223                 pm_writel(PLL1, ctrl);
 224         }
 225 }
 226
 227 static unsigned long pll1_get_rate(struct clk *clk)
 228 {
 229         u32 control;
 230
 231         control = pm_readl(PLL1);
 232
 233         return pll_get_rate(clk, control);
 234 }
 235
 236 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 237 {
 238         u32 ctrl = 0;
 239         unsigned long actual_rate;
 240
 241         actual_rate = pll_set_rate(clk, rate, &ctrl);
 242
 243         if (apply) {
 244                 if (actual_rate != rate)
 245                         return -EINVAL;
 246                 if (clk->users > 0)
 247                         return -EBUSY;
 248                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 249                                 clk->name, rate, actual_rate);
 250                 pm_writel(PLL1, ctrl);
 251         }
 252
 253         return actual_rate;
 254 }
 255
 256 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 257 {
 258         u32 ctrl;
 259
 260         if (clk->users > 0)
 261                 return -EBUSY;
 262
 263         ctrl = pm_readl(PLL1);
 264         WARN_ON(ctrl & PM_BIT(PLLEN));
 265
 266         if (parent == &osc0)
 267                 ctrl &= ~PM_BIT(PLLOSC);
 268         else if (parent == &osc1)
 269                 ctrl |= PM_BIT(PLLOSC);
 270         else
 271                 return -EINVAL;
 272
 273         pm_writel(PLL1, ctrl);
 274         clk->parent = parent;
 275
 276         return 0;
 277 }
 278
 279 /*
 280  * The AT32AP7000 has five primary clock sources: One 32kHz
 281  * oscillator, two crystal oscillators and two PLLs.
 282  */
 283 static struct clk osc32k = {
 284         .name           = "osc32k",
 285         .get_rate       = osc_get_rate,
 286         .users          = 1,
 287         .index          = 0,
 288 };
 289 static struct clk osc0 = {
 290         .name           = "osc0",
 291         .get_rate       = osc_get_rate,
 292         .users          = 1,
 293         .index          = 1,
 294 };
 295 static struct clk osc1 = {
 296         .name           = "osc1",
 297         .get_rate       = osc_get_rate,
 298         .index          = 2,
 299 };
 300 static struct clk pll0 = {
 301         .name           = "pll0",
 302         .get_rate       = pll0_get_rate,
 303         .parent         = &osc0,
 304 };
 305 static struct clk pll1 = {
 306         .name           = "pll1",
 307         .mode           = pll1_mode,
 308         .get_rate       = pll1_get_rate,
 309         .set_rate       = pll1_set_rate,
 310         .set_parent     = pll1_set_parent,
 311         .parent         = &osc0,
 312 };
 313
 314 /*
 315  * The main clock can be either osc0 or pll0.  The boot loader may
 316  * have chosen one for us, so we don't really know which one until we
 317  * have a look at the SM.
 318  */
 319 static struct clk *main_clock;
 320
 321 /*
 322  * Synchronous clocks are generated from the main clock. The clocks
 323  * must satisfy the constraint
 324  *   fCPU >= fHSB >= fPB
 325  * i.e. each clock must not be faster than its parent.
 326  */
 327 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 328 {
 329         return main_clock->get_rate(main_clock) >> shift;
 330 };
 331
 332 static void cpu_clk_mode(struct clk *clk, int enabled)
 333 {
 334         unsigned long flags;
 335         u32 mask;
 336
 337         spin_lock_irqsave(&pm_lock, flags);
 338         mask = pm_readl(CPU_MASK);
 339         if (enabled)
 340                 mask |= 1 << clk->index;
 341         else
 342                 mask &= ~(1 << clk->index);
 343         pm_writel(CPU_MASK, mask);
 344         spin_unlock_irqrestore(&pm_lock, flags);
 345 }
 346
 347 static unsigned long cpu_clk_get_rate(struct clk *clk)
 348 {
 349         unsigned long cksel, shift = 0;
 350
 351         cksel = pm_readl(CKSEL);
 352         if (cksel & PM_BIT(CPUDIV))
 353                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 354
 355         return bus_clk_get_rate(clk, shift);
 356 }
 357
 358 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 359 {
 360         u32 control;
 361         unsigned long parent_rate, child_div, actual_rate, div;
 362
 363         parent_rate = clk->parent->get_rate(clk->parent);
 364         control = pm_readl(CKSEL);
 365
 366         if (control & PM_BIT(HSBDIV))
 367                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 368         else
 369                 child_div = 1;
 370
 371         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 372                 actual_rate = parent_rate;
 373                 control &= ~PM_BIT(CPUDIV);
 374         } else {
 375                 unsigned int cpusel;
 376                 div = (parent_rate + rate / 2) / rate;
 377                 if (div > child_div)
 378                         div = child_div;
 379                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 380                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 381                 actual_rate = parent_rate / (1 << (cpusel + 1));
 382         }
 383
 384         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 385                         clk->name, rate, actual_rate);
 386
 387         if (apply)
 388                 pm_writel(CKSEL, control);
 389
 390         return actual_rate;
 391 }
 392
 393 static void hsb_clk_mode(struct clk *clk, int enabled)
 394 {
 395         unsigned long flags;
 396         u32 mask;
 397
 398         spin_lock_irqsave(&pm_lock, flags);
 399         mask = pm_readl(HSB_MASK);
 400         if (enabled)
 401                 mask |= 1 << clk->index;
 402         else
 403                 mask &= ~(1 << clk->index);
 404         pm_writel(HSB_MASK, mask);
 405         spin_unlock_irqrestore(&pm_lock, flags);
 406 }
 407
 408 static unsigned long hsb_clk_get_rate(struct clk *clk)
 409 {
 410         unsigned long cksel, shift = 0;
 411
 412         cksel = pm_readl(CKSEL);
 413         if (cksel & PM_BIT(HSBDIV))
 414                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 415
 416         return bus_clk_get_rate(clk, shift);
 417 }
 418
 419 static void pba_clk_mode(struct clk *clk, int enabled)
 420 {
 421         unsigned long flags;
 422         u32 mask;
 423
 424         spin_lock_irqsave(&pm_lock, flags);
 425         mask = pm_readl(PBA_MASK);
 426         if (enabled)
 427                 mask |= 1 << clk->index;
 428         else
 429                 mask &= ~(1 << clk->index);
 430         pm_writel(PBA_MASK, mask);
 431         spin_unlock_irqrestore(&pm_lock, flags);
 432 }
 433
 434 static unsigned long pba_clk_get_rate(struct clk *clk)
 435 {
 436         unsigned long cksel, shift = 0;
 437
 438         cksel = pm_readl(CKSEL);
 439         if (cksel & PM_BIT(PBADIV))
 440                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 441
 442         return bus_clk_get_rate(clk, shift);
 443 }
 444
 445 static void pbb_clk_mode(struct clk *clk, int enabled)
 446 {
 447         unsigned long flags;
 448         u32 mask;
 449
 450         spin_lock_irqsave(&pm_lock, flags);
 451         mask = pm_readl(PBB_MASK);
 452         if (enabled)
 453                 mask |= 1 << clk->index;
 454         else
 455                 mask &= ~(1 << clk->index);
 456         pm_writel(PBB_MASK, mask);
 457         spin_unlock_irqrestore(&pm_lock, flags);
 458 }
 459
 460 static unsigned long pbb_clk_get_rate(struct clk *clk)
 461 {
 462         unsigned long cksel, shift = 0;
 463
 464         cksel = pm_readl(CKSEL);
 465         if (cksel & PM_BIT(PBBDIV))
 466                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 467
 468         return bus_clk_get_rate(clk, shift);
 469 }
 470
 471 static struct clk cpu_clk = {
 472         .name           = "cpu",
 473         .get_rate       = cpu_clk_get_rate,
 474         .set_rate       = cpu_clk_set_rate,
 475         .users          = 1,
 476 };
 477 static struct clk hsb_clk = {
 478         .name           = "hsb",
 479         .parent         = &cpu_clk,
 480         .get_rate       = hsb_clk_get_rate,
 481 };
 482 static struct clk pba_clk = {
 483         .name           = "pba",
 484         .parent         = &hsb_clk,
 485         .mode           = hsb_clk_mode,
 486         .get_rate       = pba_clk_get_rate,
 487         .index          = 1,
 488 };
 489 static struct clk pbb_clk = {
 490         .name           = "pbb",
 491         .parent         = &hsb_clk,
 492         .mode           = hsb_clk_mode,
 493         .get_rate       = pbb_clk_get_rate,
 494         .users          = 1,
 495         .index          = 2,
 496 };
 497
 498 /* --------------------------------------------------------------------
 499  *  Generic Clock operations
 500  * -------------------------------------------------------------------- */
 501
 502 static void genclk_mode(struct clk *clk, int enabled)
 503 {
 504         u32 control;
 505
 506         control = pm_readl(GCCTRL(clk->index));
 507         if (enabled)
 508                 control |= PM_BIT(CEN);
 509         else
 510                 control &= ~PM_BIT(CEN);
 511         pm_writel(GCCTRL(clk->index), control);
 512 }
 513
 514 static unsigned long genclk_get_rate(struct clk *clk)
 515 {
 516         u32 control;
 517         unsigned long div = 1;
 518
 519         control = pm_readl(GCCTRL(clk->index));
 520         if (control & PM_BIT(DIVEN))
 521                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 522
 523         return clk->parent->get_rate(clk->parent) / div;
 524 }
 525
 526 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 527 {
 528         u32 control;
 529         unsigned long parent_rate, actual_rate, div;
 530
 531         parent_rate = clk->parent->get_rate(clk->parent);
 532         control = pm_readl(GCCTRL(clk->index));
 533
 534         if (rate > 3 * parent_rate / 4) {
 535                 actual_rate = parent_rate;
 536                 control &= ~PM_BIT(DIVEN);
 537         } else {
 538                 div = (parent_rate + rate) / (2 * rate) - 1;
 539                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 540                 actual_rate = parent_rate / (2 * (div + 1));
 541         }
 542
 543         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 544                 clk->name, rate, actual_rate);
 545
 546         if (apply)
 547                 pm_writel(GCCTRL(clk->index), control);
 548
 549         return actual_rate;
 550 }
 551
 552 int genclk_set_parent(struct clk *clk, struct clk *parent)
 553 {
 554         u32 control;
 555
 556         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 557                 clk->name, parent->name, clk->parent->name);
 558
 559         control = pm_readl(GCCTRL(clk->index));
 560
 561         if (parent == &osc1 || parent == &pll1)
 562                 control |= PM_BIT(OSCSEL);
 563         else if (parent == &osc0 || parent == &pll0)
 564                 control &= ~PM_BIT(OSCSEL);
 565         else
 566                 return -EINVAL;
 567
 568         if (parent == &pll0 || parent == &pll1)
 569                 control |= PM_BIT(PLLSEL);
 570         else
 571                 control &= ~PM_BIT(PLLSEL);
 572
 573         pm_writel(GCCTRL(clk->index), control);
 574         clk->parent = parent;
 575
 576         return 0;
 577 }
 578
 579 static void __init genclk_init_parent(struct clk *clk)
 580 {
 581         u32 control;
 582         struct clk *parent;
 583
 584         BUG_ON(clk->index > 7);
 585
 586         control = pm_readl(GCCTRL(clk->index));
 587         if (control & PM_BIT(OSCSEL))
 588                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 589         else
 590                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 591
 592         clk->parent = parent;
 593 }
 594
 595 /* --------------------------------------------------------------------
 596  *  System peripherals
 597  * -------------------------------------------------------------------- */
 598 static struct resource at32_pm0_resource[] = {
 599         {
 600                 .start  = 0xfff00000,
 601                 .end    = 0xfff0007f,
 602                 .flags  = IORESOURCE_MEM,
 603         },
 604         IRQ(20),
 605 };
 606
 607 static struct resource at32ap700x_rtc0_resource[] = {
 608         {
 609                 .start  = 0xfff00080,
 610                 .end    = 0xfff000af,
 611                 .flags  = IORESOURCE_MEM,
 612         },
 613         IRQ(21),
 614 };
 615
 616 static struct resource at32_wdt0_resource[] = {
 617         {
 618                 .start  = 0xfff000b0,
 619                 .end    = 0xfff000cf,
 620                 .flags  = IORESOURCE_MEM,
 621         },
 622 };
 623
 624 static struct resource at32_eic0_resource[] = {
 625         {
 626                 .start  = 0xfff00100,
 627                 .end    = 0xfff0013f,
 628                 .flags  = IORESOURCE_MEM,
 629         },
 630         IRQ(19),
 631 };
 632
 633 DEFINE_DEV(at32_pm, 0);
 634 DEFINE_DEV(at32ap700x_rtc, 0);
 635 DEFINE_DEV(at32_wdt, 0);
 636 DEFINE_DEV(at32_eic, 0);
 637
 638 /*
 639  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 640  * is always running.
 641  */
 642 static struct clk at32_pm_pclk = {
 643         .name           = "pclk",
 644         .dev            = &at32_pm0_device.dev,
 645         .parent         = &pbb_clk,
 646         .mode           = pbb_clk_mode,
 647         .get_rate       = pbb_clk_get_rate,
 648         .users          = 1,
 649         .index          = 0,
 650 };
 651
 652 static struct resource intc0_resource[] = {
 653         PBMEM(0xfff00400),
 654 };
 655 struct platform_device at32_intc0_device = {
 656         .name           = "intc",
 657         .id             = 0,
 658         .resource       = intc0_resource,
 659         .num_resources  = ARRAY_SIZE(intc0_resource),
 660 };
 661 DEV_CLK(pclk, at32_intc0, pbb, 1);
 662
 663 static struct clk ebi_clk = {
 664         .name           = "ebi",
 665         .parent         = &hsb_clk,
 666         .mode           = hsb_clk_mode,
 667         .get_rate       = hsb_clk_get_rate,
 668         .users          = 1,
 669 };
 670 static struct clk hramc_clk = {
 671         .name           = "hramc",
 672         .parent         = &hsb_clk,
 673         .mode           = hsb_clk_mode,
 674         .get_rate       = hsb_clk_get_rate,
 675         .users          = 1,
 676         .index          = 3,
 677 };
 678
 679 static struct resource smc0_resource[] = {
 680         PBMEM(0xfff03400),
 681 };
 682 DEFINE_DEV(smc, 0);
 683 DEV_CLK(pclk, smc0, pbb, 13);
 684 DEV_CLK(mck, smc0, hsb, 0);
 685
 686 static struct platform_device pdc_device = {
 687         .name           = "pdc",
 688         .id             = 0,
 689 };
 690 DEV_CLK(hclk, pdc, hsb, 4);
 691 DEV_CLK(pclk, pdc, pba, 16);
 692
 693 static struct clk pico_clk = {
 694         .name           = "pico",
 695         .parent         = &cpu_clk,
 696         .mode           = cpu_clk_mode,
 697         .get_rate       = cpu_clk_get_rate,
 698         .users          = 1,
 699 };
 700
 701 static struct resource dmaca0_resource[] = {
 702         {
 703                 .start  = 0xff200000,
 704                 .end    = 0xff20ffff,
 705                 .flags  = IORESOURCE_MEM,
 706         },
 707         IRQ(2),
 708 };
 709 DEFINE_DEV(dmaca, 0);
 710 DEV_CLK(hclk, dmaca0, hsb, 10);
 711
 712 /* --------------------------------------------------------------------
 713  * HMATRIX
 714  * -------------------------------------------------------------------- */
 715
 716 static struct clk hmatrix_clk = {
 717         .name           = "hmatrix_clk",
 718         .parent         = &pbb_clk,
 719         .mode           = pbb_clk_mode,
 720         .get_rate       = pbb_clk_get_rate,
 721         .index          = 2,
 722         .users          = 1,
 723 };
 724 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 725
 726 #define hmatrix_readl(reg)                                      \
 727         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 728 #define hmatrix_writel(reg,value)                               \
 729         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 730
 731 /*
 732  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 733  * External Bus Interface (EBI). This can be used to enable special
 734  * features like CompactFlash support, NAND Flash support, etc. on
 735  * certain chipselects.
 736  */
 737 static inline void set_ebi_sfr_bits(u32 mask)
 738 {
 739         u32 sfr;
 740
 741         clk_enable(&hmatrix_clk);
 742         sfr = hmatrix_readl(SFR4);
 743         sfr |= mask;
 744         hmatrix_writel(SFR4, sfr);
 745         clk_disable(&hmatrix_clk);
 746 }
 747
 748 /* --------------------------------------------------------------------
 749  *  Timer/Counter (TC)
 750  * -------------------------------------------------------------------- */
 751
 752 static struct resource at32_tcb0_resource[] = {
 753         PBMEM(0xfff00c00),
 754         IRQ(22),
 755 };
 756 static struct platform_device at32_tcb0_device = {
 757         .name           = "atmel_tcb",
 758         .id             = 0,
 759         .resource       = at32_tcb0_resource,
 760         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 761 };
 762 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 763
 764 static struct resource at32_tcb1_resource[] = {
 765         PBMEM(0xfff01000),
 766         IRQ(23),
 767 };
 768 static struct platform_device at32_tcb1_device = {
 769         .name           = "atmel_tcb",
 770         .id             = 1,
 771         .resource       = at32_tcb1_resource,
 772         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 773 };
 774 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 775
 776 /* --------------------------------------------------------------------
 777  *  PIO
 778  * -------------------------------------------------------------------- */
 779
 780 static struct resource pio0_resource[] = {
 781         PBMEM(0xffe02800),
 782         IRQ(13),
 783 };
 784 DEFINE_DEV(pio, 0);
 785 DEV_CLK(mck, pio0, pba, 10);
 786
 787 static struct resource pio1_resource[] = {
 788         PBMEM(0xffe02c00),
 789         IRQ(14),
 790 };
 791 DEFINE_DEV(pio, 1);
 792 DEV_CLK(mck, pio1, pba, 11);
 793
 794 static struct resource pio2_resource[] = {
 795         PBMEM(0xffe03000),
 796         IRQ(15),
 797 };
 798 DEFINE_DEV(pio, 2);
 799 DEV_CLK(mck, pio2, pba, 12);
 800
 801 static struct resource pio3_resource[] = {
 802         PBMEM(0xffe03400),
 803         IRQ(16),
 804 };
 805 DEFINE_DEV(pio, 3);
 806 DEV_CLK(mck, pio3, pba, 13);
 807
 808 static struct resource pio4_resource[] = {
 809         PBMEM(0xffe03800),
 810         IRQ(17),
 811 };
 812 DEFINE_DEV(pio, 4);
 813 DEV_CLK(mck, pio4, pba, 14);
 814
 815 void __init at32_add_system_devices(void)
 816 {
 817         platform_device_register(&at32_pm0_device);
 818         platform_device_register(&at32_intc0_device);
 819         platform_device_register(&at32ap700x_rtc0_device);
 820         platform_device_register(&at32_wdt0_device);
 821         platform_device_register(&at32_eic0_device);
 822         platform_device_register(&smc0_device);
 823         platform_device_register(&pdc_device);
 824         platform_device_register(&dmaca0_device);
 825
 826         platform_device_register(&at32_tcb0_device);
 827         platform_device_register(&at32_tcb1_device);
 828
 829         platform_device_register(&pio0_device);
 830         platform_device_register(&pio1_device);
 831         platform_device_register(&pio2_device);
 832         platform_device_register(&pio3_device);
 833         platform_device_register(&pio4_device);
 834 }
 835
 836 /* --------------------------------------------------------------------
 837  *  USART
 838  * -------------------------------------------------------------------- */
 839
 840 static struct atmel_uart_data atmel_usart0_data = {
 841         .use_dma_tx     = 1,
 842         .use_dma_rx     = 1,
 843 };
 844 static struct resource atmel_usart0_resource[] = {
 845         PBMEM(0xffe00c00),
 846         IRQ(6),
 847 };
 848 DEFINE_DEV_DATA(atmel_usart, 0);
 849 DEV_CLK(usart, atmel_usart0, pba, 3);
 850
 851 static struct atmel_uart_data atmel_usart1_data = {
 852         .use_dma_tx     = 1,
 853         .use_dma_rx     = 1,
 854 };
 855 static struct resource atmel_usart1_resource[] = {
 856         PBMEM(0xffe01000),
 857         IRQ(7),
 858 };
 859 DEFINE_DEV_DATA(atmel_usart, 1);
 860 DEV_CLK(usart, atmel_usart1, pba, 4);
 861
 862 static struct atmel_uart_data atmel_usart2_data = {
 863         .use_dma_tx     = 1,
 864         .use_dma_rx     = 1,
 865 };
 866 static struct resource atmel_usart2_resource[] = {
 867         PBMEM(0xffe01400),
 868         IRQ(8),
 869 };
 870 DEFINE_DEV_DATA(atmel_usart, 2);
 871 DEV_CLK(usart, atmel_usart2, pba, 5);
 872
 873 static struct atmel_uart_data atmel_usart3_data = {
 874         .use_dma_tx     = 1,
 875         .use_dma_rx     = 1,
 876 };
 877 static struct resource atmel_usart3_resource[] = {
 878         PBMEM(0xffe01800),
 879         IRQ(9),
 880 };
 881 DEFINE_DEV_DATA(atmel_usart, 3);
 882 DEV_CLK(usart, atmel_usart3, pba, 6);
 883
 884 static inline void configure_usart0_pins(void)
 885 {
 886         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 887         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 888 }
 889
 890 static inline void configure_usart1_pins(void)
 891 {
 892         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 893         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 894 }
 895
 896 static inline void configure_usart2_pins(void)
 897 {
 898         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 899         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 900 }
 901
 902 static inline void configure_usart3_pins(void)
 903 {
 904         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 905         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 906 }
 907
 908 static struct platform_device *__initdata at32_usarts[4];
 909
 910 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 911 {
 912         struct platform_device *pdev;
 913
 914         switch (hw_id) {
 915         case 0:
 916                 pdev = &atmel_usart0_device;
 917                 configure_usart0_pins();
 918                 break;
 919         case 1:
 920                 pdev = &atmel_usart1_device;
 921                 configure_usart1_pins();
 922                 break;
 923         case 2:
 924                 pdev = &atmel_usart2_device;
 925                 configure_usart2_pins();
 926                 break;
 927         case 3:
 928                 pdev = &atmel_usart3_device;
 929                 configure_usart3_pins();
 930                 break;
 931         default:
 932                 return;
 933         }
 934
 935         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 936                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 937                 struct atmel_uart_data *data = pdev->dev.platform_data;
 938                 data->regs = (void __iomem *)pdev->resource[0].start;
 939         }
 940
 941         pdev->id = line;
 942         at32_usarts[line] = pdev;
 943 }
 944
 945 struct platform_device *__init at32_add_device_usart(unsigned int id)
 946 {
 947         platform_device_register(at32_usarts[id]);
 948         return at32_usarts[id];
 949 }
 950
 951 struct platform_device *atmel_default_console_device;
 952
 953 void __init at32_setup_serial_console(unsigned int usart_id)
 954 {
 955         atmel_default_console_device = at32_usarts[usart_id];
 956 }
 957
 958 /* --------------------------------------------------------------------
 959  *  Ethernet
 960  * -------------------------------------------------------------------- */
 961
 962 #ifdef CONFIG_CPU_AT32AP7000
 963 static struct eth_platform_data macb0_data;
 964 static struct resource macb0_resource[] = {
 965         PBMEM(0xfff01800),
 966         IRQ(25),
 967 };
 968 DEFINE_DEV_DATA(macb, 0);
 969 DEV_CLK(hclk, macb0, hsb, 8);
 970 DEV_CLK(pclk, macb0, pbb, 6);
 971
 972 static struct eth_platform_data macb1_data;
 973 static struct resource macb1_resource[] = {
 974         PBMEM(0xfff01c00),
 975         IRQ(26),
 976 };
 977 DEFINE_DEV_DATA(macb, 1);
 978 DEV_CLK(hclk, macb1, hsb, 9);
 979 DEV_CLK(pclk, macb1, pbb, 7);
 980
 981 struct platform_device *__init
 982 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 983 {
 984         struct platform_device *pdev;
 985
 986         switch (id) {
 987         case 0:
 988                 pdev = &macb0_device;
 989
 990                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 991                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 992                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 993                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 994                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 995                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 996                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 997                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 998                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 999                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1000
1001                 if (!data->is_rmii) {
1002                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1003                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1004                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1005                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1006                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1007                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1008                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1009                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1010                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1011                 }
1012                 break;
1013
1014         case 1:
1015                 pdev = &macb1_device;
1016
1017                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1018                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1019                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1020                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1021                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1022                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1023                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1024                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1025                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1026                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1027
1028                 if (!data->is_rmii) {
1029                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1030                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1031                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1032                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1033                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1034                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1035                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1036                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1037                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1038                 }
1039                 break;
1040
1041         default:
1042                 return NULL;
1043         }
1044
1045         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1046         platform_device_register(pdev);
1047
1048         return pdev;
1049 }
1050 #endif
1051
1052 /* --------------------------------------------------------------------
1053  *  SPI
1054  * -------------------------------------------------------------------- */
1055 static struct resource atmel_spi0_resource[] = {
1056         PBMEM(0xffe00000),
1057         IRQ(3),
1058 };
1059 DEFINE_DEV(atmel_spi, 0);
1060 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1061
1062 static struct resource atmel_spi1_resource[] = {
1063         PBMEM(0xffe00400),
1064         IRQ(4),
1065 };
1066 DEFINE_DEV(atmel_spi, 1);
1067 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1068
1069 static void __init
1070 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1071                       unsigned int n, const u8 *pins)
1072 {
1073         unsigned int pin, mode;
1074
1075         for (; n; n--, b++) {
1076                 b->bus_num = bus_num;
1077                 if (b->chip_select >= 4)
1078                         continue;
1079                 pin = (unsigned)b->controller_data;
1080                 if (!pin) {
1081                         pin = pins[b->chip_select];
1082                         b->controller_data = (void *)pin;
1083                 }
1084                 mode = AT32_GPIOF_OUTPUT;
1085                 if (!(b->mode & SPI_CS_HIGH))
1086                         mode |= AT32_GPIOF_HIGH;
1087                 at32_select_gpio(pin, mode);
1088         }
1089 }
1090
1091 struct platform_device *__init
1092 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1093 {
1094         /*
1095          * Manage the chipselects as GPIOs, normally using the same pins
1096          * the SPI controller expects; but boards can use other pins.
1097          */
1098         static u8 __initdata spi0_pins[] =
1099                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1100                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1101         static u8 __initdata spi1_pins[] =
1102                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1103                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1104         struct platform_device *pdev;
1105
1106         switch (id) {
1107         case 0:
1108                 pdev = &atmel_spi0_device;
1109                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
1110                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1111                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1112                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1113                 break;
1114
1115         case 1:
1116                 pdev = &atmel_spi1_device;
1117                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
1118                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1119                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1120                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1121                 break;
1122
1123         default:
1124                 return NULL;
1125         }
1126
1127         spi_register_board_info(b, n);
1128         platform_device_register(pdev);
1129         return pdev;
1130 }
1131
1132 /* --------------------------------------------------------------------
1133  *  TWI
1134  * -------------------------------------------------------------------- */
1135 static struct resource atmel_twi0_resource[] __initdata = {
1136         PBMEM(0xffe00800),
1137         IRQ(5),
1138 };
1139 static struct clk atmel_twi0_pclk = {
1140         .name           = "twi_pclk",
1141         .parent         = &pba_clk,
1142         .mode           = pba_clk_mode,
1143         .get_rate       = pba_clk_get_rate,
1144         .index          = 2,
1145 };
1146
1147 struct platform_device *__init at32_add_device_twi(unsigned int id,
1148                                                     struct i2c_board_info *b,
1149                                                     unsigned int n)
1150 {
1151         struct platform_device *pdev;
1152
1153         if (id != 0)
1154                 return NULL;
1155
1156         pdev = platform_device_alloc("atmel_twi", id);
1157         if (!pdev)
1158                 return NULL;
1159
1160         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1161                                 ARRAY_SIZE(atmel_twi0_resource)))
1162                 goto err_add_resources;
1163
1164         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1165         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1166
1167         atmel_twi0_pclk.dev = &pdev->dev;
1168
1169         if (b)
1170                 i2c_register_board_info(id, b, n);
1171
1172         platform_device_add(pdev);
1173         return pdev;
1174
1175 err_add_resources:
1176         platform_device_put(pdev);
1177         return NULL;
1178 }
1179
1180 /* --------------------------------------------------------------------
1181  * MMC
1182  * -------------------------------------------------------------------- */
1183 static struct resource atmel_mci0_resource[] __initdata = {
1184         PBMEM(0xfff02400),
1185         IRQ(28),
1186 };
1187 static struct clk atmel_mci0_pclk = {
1188         .name           = "mci_clk",
1189         .parent         = &pbb_clk,
1190         .mode           = pbb_clk_mode,
1191         .get_rate       = pbb_clk_get_rate,
1192         .index          = 9,
1193 };
1194
1195 struct platform_device *__init at32_add_device_mci(unsigned int id)
1196 {
1197         struct platform_device *pdev;
1198
1199         if (id != 0)
1200                 return NULL;
1201
1202         pdev = platform_device_alloc("atmel_mci", id);
1203         if (!pdev)
1204                 return NULL;
1205
1206         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1207                                 ARRAY_SIZE(atmel_mci0_resource)))
1208                 goto err_add_resources;
1209
1210         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1211         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1212         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1213         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1214         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1215         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1216
1217         atmel_mci0_pclk.dev = &pdev->dev;
1218
1219         platform_device_add(pdev);
1220         return pdev;
1221
1222 err_add_resources:
1223         platform_device_put(pdev);
1224         return NULL;
1225 }
1226
1227 /* --------------------------------------------------------------------
1228  *  LCDC
1229  * -------------------------------------------------------------------- */
1230 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1231 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1232 static struct resource atmel_lcdfb0_resource[] = {
1233         {
1234                 .start          = 0xff000000,
1235                 .end            = 0xff000fff,
1236                 .flags          = IORESOURCE_MEM,
1237         },
1238         IRQ(1),
1239         {
1240                 /* Placeholder for pre-allocated fb memory */
1241                 .start          = 0x00000000,
1242                 .end            = 0x00000000,
1243                 .flags          = 0,
1244         },
1245 };
1246 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1247 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1248 static struct clk atmel_lcdfb0_pixclk = {
1249         .name           = "lcdc_clk",
1250         .dev            = &atmel_lcdfb0_device.dev,
1251         .mode           = genclk_mode,
1252         .get_rate       = genclk_get_rate,
1253         .set_rate       = genclk_set_rate,
1254         .set_parent     = genclk_set_parent,
1255         .index          = 7,
1256 };
1257
1258 struct platform_device *__init
1259 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1260                      unsigned long fbmem_start, unsigned long fbmem_len,
1261                      unsigned int pin_config)
1262 {
1263         struct platform_device *pdev;
1264         struct atmel_lcdfb_info *info;
1265         struct fb_monspecs *monspecs;
1266         struct fb_videomode *modedb;
1267         unsigned int modedb_size;
1268
1269         /*
1270          * Do a deep copy of the fb data, monspecs and modedb. Make
1271          * sure all allocations are done before setting up the
1272          * portmux.
1273          */
1274         monspecs = kmemdup(data->default_monspecs,
1275                            sizeof(struct fb_monspecs), GFP_KERNEL);
1276         if (!monspecs)
1277                 return NULL;
1278
1279         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1280         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1281         if (!modedb)
1282                 goto err_dup_modedb;
1283         monspecs->modedb = modedb;
1284
1285         switch (id) {
1286         case 0:
1287                 pdev = &atmel_lcdfb0_device;
1288
1289                 switch (pin_config) {
1290                 case 0:
1291                         select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1292                         select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1293                         select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1294                         select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1295                         select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1296                         select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1297                         select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1298                         select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1299                         select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1300                         select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1301                         select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1302                         select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1303                         select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1304                         select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1305                         select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1306                         select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1307                         select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1308                         select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1309                         select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1310                         select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1311                         select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1312                         select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1313                         select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1314                         select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1315                         select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1316                         select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1317                         select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1318                         select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1319                         select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1320                         select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1321                         select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1322                         break;
1323                 case 1:
1324                         select_peripheral(PE(0),  PERIPH_B, 0); /* CC     */
1325                         select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1326                         select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1327                         select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1328                         select_peripheral(PE(1),  PERIPH_B, 0); /* DVAL   */
1329                         select_peripheral(PE(2),  PERIPH_B, 0); /* MODE   */
1330                         select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1331                         select_peripheral(PE(3),  PERIPH_B, 0); /* DATA0  */
1332                         select_peripheral(PE(4),  PERIPH_B, 0); /* DATA1  */
1333                         select_peripheral(PE(5),  PERIPH_B, 0); /* DATA2  */
1334                         select_peripheral(PE(6),  PERIPH_B, 0); /* DATA3  */
1335                         select_peripheral(PE(7),  PERIPH_B, 0); /* DATA4  */
1336                         select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1337                         select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1338                         select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1339                         select_peripheral(PE(8),  PERIPH_B, 0); /* DATA8  */
1340                         select_peripheral(PE(9),  PERIPH_B, 0); /* DATA9  */
1341                         select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1342                         select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1343                         select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1344                         select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1345                         select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1346                         select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1347                         select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1348                         select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1349                         select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1350                         select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1351                         select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1352                         select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1353                         select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1354                         select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1355                         break;
1356                 default:
1357                         goto err_invalid_id;
1358                 }
1359
1360                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1361                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1362                 break;
1363
1364         default:
1365                 goto err_invalid_id;
1366         }
1367
1368         if (fbmem_len) {
1369                 pdev->resource[2].start = fbmem_start;
1370                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1371                 pdev->resource[2].flags = IORESOURCE_MEM;
1372         }
1373
1374         info = pdev->dev.platform_data;
1375         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1376         info->default_monspecs = monspecs;
1377
1378         platform_device_register(pdev);
1379         return pdev;
1380
1381 err_invalid_id:
1382         kfree(modedb);
1383 err_dup_modedb:
1384         kfree(monspecs);
1385         return NULL;
1386 }
1387 #endif
1388
1389 /* --------------------------------------------------------------------
1390  *  PWM
1391  * -------------------------------------------------------------------- */
1392 static struct resource atmel_pwm0_resource[] __initdata = {
1393         PBMEM(0xfff01400),
1394         IRQ(24),
1395 };
1396 static struct clk atmel_pwm0_mck = {
1397         .name           = "mck",
1398         .parent         = &pbb_clk,
1399         .mode           = pbb_clk_mode,
1400         .get_rate       = pbb_clk_get_rate,
1401         .index          = 5,
1402 };
1403
1404 struct platform_device *__init at32_add_device_pwm(u32 mask)
1405 {
1406         struct platform_device *pdev;
1407
1408         if (!mask)
1409                 return NULL;
1410
1411         pdev = platform_device_alloc("atmel_pwm", 0);
1412         if (!pdev)
1413                 return NULL;
1414
1415         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1416                                 ARRAY_SIZE(atmel_pwm0_resource)))
1417                 goto out_free_pdev;
1418
1419         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1420                 goto out_free_pdev;
1421
1422         if (mask & (1 << 0))
1423                 select_peripheral(PA(28), PERIPH_A, 0);
1424         if (mask & (1 << 1))
1425                 select_peripheral(PA(29), PERIPH_A, 0);
1426         if (mask & (1 << 2))
1427                 select_peripheral(PA(21), PERIPH_B, 0);
1428         if (mask & (1 << 3))
1429                 select_peripheral(PA(22), PERIPH_B, 0);
1430
1431         atmel_pwm0_mck.dev = &pdev->dev;
1432
1433         platform_device_add(pdev);
1434
1435         return pdev;
1436
1437 out_free_pdev:
1438         platform_device_put(pdev);
1439         return NULL;
1440 }
1441
1442 /* --------------------------------------------------------------------
1443  *  SSC
1444  * -------------------------------------------------------------------- */
1445 static struct resource ssc0_resource[] = {
1446         PBMEM(0xffe01c00),
1447         IRQ(10),
1448 };
1449 DEFINE_DEV(ssc, 0);
1450 DEV_CLK(pclk, ssc0, pba, 7);
1451
1452 static struct resource ssc1_resource[] = {
1453         PBMEM(0xffe02000),
1454         IRQ(11),
1455 };
1456 DEFINE_DEV(ssc, 1);
1457 DEV_CLK(pclk, ssc1, pba, 8);
1458
1459 static struct resource ssc2_resource[] = {
1460         PBMEM(0xffe02400),
1461         IRQ(12),
1462 };
1463 DEFINE_DEV(ssc, 2);
1464 DEV_CLK(pclk, ssc2, pba, 9);
1465
1466 struct platform_device *__init
1467 at32_add_device_ssc(unsigned int id, unsigned int flags)
1468 {
1469         struct platform_device *pdev;
1470
1471         switch (id) {
1472         case 0:
1473                 pdev = &ssc0_device;
1474                 if (flags & ATMEL_SSC_RF)
1475                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1476                 if (flags & ATMEL_SSC_RK)
1477                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1478                 if (flags & ATMEL_SSC_TK)
1479                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1480                 if (flags & ATMEL_SSC_TF)
1481                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1482                 if (flags & ATMEL_SSC_TD)
1483                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1484                 if (flags & ATMEL_SSC_RD)
1485                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1486                 break;
1487         case 1:
1488                 pdev = &ssc1_device;
1489                 if (flags & ATMEL_SSC_RF)
1490                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1491                 if (flags & ATMEL_SSC_RK)
1492                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1493                 if (flags & ATMEL_SSC_TK)
1494                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1495                 if (flags & ATMEL_SSC_TF)
1496                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1497                 if (flags & ATMEL_SSC_TD)
1498                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1499                 if (flags & ATMEL_SSC_RD)
1500                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1501                 break;
1502         case 2:
1503                 pdev = &ssc2_device;
1504                 if (flags & ATMEL_SSC_TD)
1505                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1506                 if (flags & ATMEL_SSC_RD)
1507                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1508                 if (flags & ATMEL_SSC_TK)
1509                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1510                 if (flags & ATMEL_SSC_TF)
1511                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1512                 if (flags & ATMEL_SSC_RF)
1513                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1514                 if (flags & ATMEL_SSC_RK)
1515                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1516                 break;
1517         default:
1518                 return NULL;
1519         }
1520
1521         platform_device_register(pdev);
1522         return pdev;
1523 }
1524
1525 /* --------------------------------------------------------------------
1526  *  USB Device Controller
1527  * -------------------------------------------------------------------- */
1528 static struct resource usba0_resource[] __initdata = {
1529         {
1530                 .start          = 0xff300000,
1531                 .end            = 0xff3fffff,
1532                 .flags          = IORESOURCE_MEM,
1533         }, {
1534                 .start          = 0xfff03000,
1535                 .end            = 0xfff033ff,
1536                 .flags          = IORESOURCE_MEM,
1537         },
1538         IRQ(31),
1539 };
1540 static struct clk usba0_pclk = {
1541         .name           = "pclk",
1542         .parent         = &pbb_clk,
1543         .mode           = pbb_clk_mode,
1544         .get_rate       = pbb_clk_get_rate,
1545         .index          = 12,
1546 };
1547 static struct clk usba0_hclk = {
1548         .name           = "hclk",
1549         .parent         = &hsb_clk,
1550         .mode           = hsb_clk_mode,
1551         .get_rate       = hsb_clk_get_rate,
1552         .index          = 6,
1553 };
1554
1555 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1556         [idx] = {                                               \
1557                 .name           = nam,                          \
1558                 .index          = idx,                          \
1559                 .fifo_size      = maxpkt,                       \
1560                 .nr_banks       = maxbk,                        \
1561                 .can_dma        = dma,                          \
1562                 .can_isoc       = isoc,                         \
1563         }
1564
1565 static struct usba_ep_data at32_usba_ep[] __initdata = {
1566         EP("ep0",     0,   64, 1, 0, 0),
1567         EP("ep1",     1,  512, 2, 1, 1),
1568         EP("ep2",     2,  512, 2, 1, 1),
1569         EP("ep3-int", 3,   64, 3, 1, 0),
1570         EP("ep4-int", 4,   64, 3, 1, 0),
1571         EP("ep5",     5, 1024, 3, 1, 1),
1572         EP("ep6",     6, 1024, 3, 1, 1),
1573 };
1574
1575 #undef EP
1576
1577 struct platform_device *__init
1578 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1579 {
1580         /*
1581          * pdata doesn't have room for any endpoints, so we need to
1582          * append room for the ones we need right after it.
1583          */
1584         struct {
1585                 struct usba_platform_data pdata;
1586                 struct usba_ep_data ep[7];
1587         } usba_data;
1588         struct platform_device *pdev;
1589
1590         if (id != 0)
1591                 return NULL;
1592
1593         pdev = platform_device_alloc("atmel_usba_udc", 0);
1594         if (!pdev)
1595                 return NULL;
1596
1597         if (platform_device_add_resources(pdev, usba0_resource,
1598                                           ARRAY_SIZE(usba0_resource)))
1599                 goto out_free_pdev;
1600
1601         if (data)
1602                 usba_data.pdata.vbus_pin = data->vbus_pin;
1603         else
1604                 usba_data.pdata.vbus_pin = -EINVAL;
1605
1606         data = &usba_data.pdata;
1607         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1608         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1609
1610         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1611                 goto out_free_pdev;
1612
1613         if (data->vbus_pin >= 0)
1614                 at32_select_gpio(data->vbus_pin, 0);
1615
1616         usba0_pclk.dev = &pdev->dev;
1617         usba0_hclk.dev = &pdev->dev;
1618
1619         platform_device_add(pdev);
1620
1621         return pdev;
1622
1623 out_free_pdev:
1624         platform_device_put(pdev);
1625         return NULL;
1626 }
1627
1628 /* --------------------------------------------------------------------
1629  * IDE / CompactFlash
1630  * -------------------------------------------------------------------- */
1631 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1632 static struct resource at32_smc_cs4_resource[] __initdata = {
1633         {
1634                 .start  = 0x04000000,
1635                 .end    = 0x07ffffff,
1636                 .flags  = IORESOURCE_MEM,
1637         },
1638         IRQ(~0UL), /* Magic IRQ will be overridden */
1639 };
1640 static struct resource at32_smc_cs5_resource[] __initdata = {
1641         {
1642                 .start  = 0x20000000,
1643                 .end    = 0x23ffffff,
1644                 .flags  = IORESOURCE_MEM,
1645         },
1646         IRQ(~0UL), /* Magic IRQ will be overridden */
1647 };
1648
1649 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1650                 unsigned int cs, unsigned int extint)
1651 {
1652         static unsigned int extint_pin_map[4] __initdata = {
1653                 GPIO_PIN_PB(25),
1654                 GPIO_PIN_PB(26),
1655                 GPIO_PIN_PB(27),
1656                 GPIO_PIN_PB(28),
1657         };
1658         static bool common_pins_initialized __initdata = false;
1659         unsigned int extint_pin;
1660         int ret;
1661
1662         if (extint >= ARRAY_SIZE(extint_pin_map))
1663                 return -EINVAL;
1664         extint_pin = extint_pin_map[extint];
1665
1666         switch (cs) {
1667         case 4:
1668                 ret = platform_device_add_resources(pdev,
1669                                 at32_smc_cs4_resource,
1670                                 ARRAY_SIZE(at32_smc_cs4_resource));
1671                 if (ret)
1672                         return ret;
1673
1674                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1675                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1676                 break;
1677         case 5:
1678                 ret = platform_device_add_resources(pdev,
1679                                 at32_smc_cs5_resource,
1680                                 ARRAY_SIZE(at32_smc_cs5_resource));
1681                 if (ret)
1682                         return ret;
1683
1684                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1685                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1686                 break;
1687         default:
1688                 return -EINVAL;
1689         }
1690
1691         if (!common_pins_initialized) {
1692                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1693                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1694                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1695                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1696                 common_pins_initialized = true;
1697         }
1698
1699         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1700
1701         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1702         pdev->resource[1].end = pdev->resource[1].start;
1703
1704         return 0;
1705 }
1706
1707 struct platform_device *__init
1708 at32_add_device_ide(unsigned int id, unsigned int extint,
1709                     struct ide_platform_data *data)
1710 {
1711         struct platform_device *pdev;
1712
1713         pdev = platform_device_alloc("at32_ide", id);
1714         if (!pdev)
1715                 goto fail;
1716
1717         if (platform_device_add_data(pdev, data,
1718                                 sizeof(struct ide_platform_data)))
1719                 goto fail;
1720
1721         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1722                 goto fail;
1723
1724         platform_device_add(pdev);
1725         return pdev;
1726
1727 fail:
1728         platform_device_put(pdev);
1729         return NULL;
1730 }
1731
1732 struct platform_device *__init
1733 at32_add_device_cf(unsigned int id, unsigned int extint,
1734                     struct cf_platform_data *data)
1735 {
1736         struct platform_device *pdev;
1737
1738         pdev = platform_device_alloc("at32_cf", id);
1739         if (!pdev)
1740                 goto fail;
1741
1742         if (platform_device_add_data(pdev, data,
1743                                 sizeof(struct cf_platform_data)))
1744                 goto fail;
1745
1746         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1747                 goto fail;
1748
1749         if (data->detect_pin != GPIO_PIN_NONE)
1750                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1751         if (data->reset_pin != GPIO_PIN_NONE)
1752                 at32_select_gpio(data->reset_pin, 0);
1753         if (data->vcc_pin != GPIO_PIN_NONE)
1754                 at32_select_gpio(data->vcc_pin, 0);
1755         /* READY is used as extint, so we can't select it as gpio */
1756
1757         platform_device_add(pdev);
1758         return pdev;
1759
1760 fail:
1761         platform_device_put(pdev);
1762         return NULL;
1763 }
1764 #endif
1765
1766 /* --------------------------------------------------------------------
1767  * AC97C
1768  * -------------------------------------------------------------------- */
1769 static struct resource atmel_ac97c0_resource[] __initdata = {
1770         PBMEM(0xfff02800),
1771         IRQ(29),
1772 };
1773 static struct clk atmel_ac97c0_pclk = {
1774         .name           = "pclk",
1775         .parent         = &pbb_clk,
1776         .mode           = pbb_clk_mode,
1777         .get_rate       = pbb_clk_get_rate,
1778         .index          = 10,
1779 };
1780
1781 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1782 {
1783         struct platform_device *pdev;
1784
1785         if (id != 0)
1786                 return NULL;
1787
1788         pdev = platform_device_alloc("atmel_ac97c", id);
1789         if (!pdev)
1790                 return NULL;
1791
1792         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1793                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1794                 goto err_add_resources;
1795
1796         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1797         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1798         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1799         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1800
1801         atmel_ac97c0_pclk.dev = &pdev->dev;
1802
1803         platform_device_add(pdev);
1804         return pdev;
1805
1806 err_add_resources:
1807         platform_device_put(pdev);
1808         return NULL;
1809 }
1810
1811 /* --------------------------------------------------------------------
1812  * ABDAC
1813  * -------------------------------------------------------------------- */
1814 static struct resource abdac0_resource[] __initdata = {
1815         PBMEM(0xfff02000),
1816         IRQ(27),
1817 };
1818 static struct clk abdac0_pclk = {
1819         .name           = "pclk",
1820         .parent         = &pbb_clk,
1821         .mode           = pbb_clk_mode,
1822         .get_rate       = pbb_clk_get_rate,
1823         .index          = 8,
1824 };
1825 static struct clk abdac0_sample_clk = {
1826         .name           = "sample_clk",
1827         .mode           = genclk_mode,
1828         .get_rate       = genclk_get_rate,
1829         .set_rate       = genclk_set_rate,
1830         .set_parent     = genclk_set_parent,
1831         .index          = 6,
1832 };
1833
1834 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1835 {
1836         struct platform_device *pdev;
1837
1838         if (id != 0)
1839                 return NULL;
1840
1841         pdev = platform_device_alloc("abdac", id);
1842         if (!pdev)
1843                 return NULL;
1844
1845         if (platform_device_add_resources(pdev, abdac0_resource,
1846                                 ARRAY_SIZE(abdac0_resource)))
1847                 goto err_add_resources;
1848
1849         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1850         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1851         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1852         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1853
1854         abdac0_pclk.dev = &pdev->dev;
1855         abdac0_sample_clk.dev = &pdev->dev;
1856
1857         platform_device_add(pdev);
1858         return pdev;
1859
1860 err_add_resources:
1861         platform_device_put(pdev);
1862         return NULL;
1863 }
1864
1865 /* --------------------------------------------------------------------
1866  *  GCLK
1867  * -------------------------------------------------------------------- */
1868 static struct clk gclk0 = {
1869         .name           = "gclk0",
1870         .mode           = genclk_mode,
1871         .get_rate       = genclk_get_rate,
1872         .set_rate       = genclk_set_rate,
1873         .set_parent     = genclk_set_parent,
1874         .index          = 0,
1875 };
1876 static struct clk gclk1 = {
1877         .name           = "gclk1",
1878         .mode           = genclk_mode,
1879         .get_rate       = genclk_get_rate,
1880         .set_rate       = genclk_set_rate,
1881         .set_parent     = genclk_set_parent,
1882         .index          = 1,
1883 };
1884 static struct clk gclk2 = {
1885         .name           = "gclk2",
1886         .mode           = genclk_mode,
1887         .get_rate       = genclk_get_rate,
1888         .set_rate       = genclk_set_rate,
1889         .set_parent     = genclk_set_parent,
1890         .index          = 2,
1891 };
1892 static struct clk gclk3 = {
1893         .name           = "gclk3",
1894         .mode           = genclk_mode,
1895         .get_rate       = genclk_get_rate,
1896         .set_rate       = genclk_set_rate,
1897         .set_parent     = genclk_set_parent,
1898         .index          = 3,
1899 };
1900 static struct clk gclk4 = {
1901         .name           = "gclk4",
1902         .mode           = genclk_mode,
1903         .get_rate       = genclk_get_rate,
1904         .set_rate       = genclk_set_rate,
1905         .set_parent     = genclk_set_parent,
1906         .index          = 4,
1907 };
1908
1909 struct clk *at32_clock_list[] = {
1910         &osc32k,
1911         &osc0,
1912         &osc1,
1913         &pll0,
1914         &pll1,
1915         &cpu_clk,
1916         &hsb_clk,
1917         &pba_clk,
1918         &pbb_clk,
1919         &at32_pm_pclk,
1920         &at32_intc0_pclk,
1921         &hmatrix_clk,
1922         &ebi_clk,
1923         &hramc_clk,
1924         &smc0_pclk,
1925         &smc0_mck,
1926         &pdc_hclk,
1927         &pdc_pclk,
1928         &dmaca0_hclk,
1929         &pico_clk,
1930         &pio0_mck,
1931         &pio1_mck,
1932         &pio2_mck,
1933         &pio3_mck,
1934         &pio4_mck,
1935         &at32_tcb0_t0_clk,
1936         &at32_tcb1_t0_clk,
1937         &atmel_usart0_usart,
1938         &atmel_usart1_usart,
1939         &atmel_usart2_usart,
1940         &atmel_usart3_usart,
1941         &atmel_pwm0_mck,
1942 #if defined(CONFIG_CPU_AT32AP7000)
1943         &macb0_hclk,
1944         &macb0_pclk,
1945         &macb1_hclk,
1946         &macb1_pclk,
1947 #endif
1948         &atmel_spi0_spi_clk,
1949         &atmel_spi1_spi_clk,
1950         &atmel_twi0_pclk,
1951         &atmel_mci0_pclk,
1952 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1953         &atmel_lcdfb0_hck1,
1954         &atmel_lcdfb0_pixclk,
1955 #endif
1956         &ssc0_pclk,
1957         &ssc1_pclk,
1958         &ssc2_pclk,
1959         &usba0_hclk,
1960         &usba0_pclk,
1961         &atmel_ac97c0_pclk,
1962         &abdac0_pclk,
1963         &abdac0_sample_clk,
1964         &gclk0,
1965         &gclk1,
1966         &gclk2,
1967         &gclk3,
1968         &gclk4,
1969 };
1970 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1971
1972 void __init at32_portmux_init(void)
1973 {
1974         at32_init_pio(&pio0_device);
1975         at32_init_pio(&pio1_device);
1976         at32_init_pio(&pio2_device);
1977         at32_init_pio(&pio3_device);
1978         at32_init_pio(&pio4_device);
1979 }
1980
1981 void __init at32_clock_init(void)
1982 {
1983         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1984         int i;
1985
1986         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1987                 main_clock = &pll0;
1988                 cpu_clk.parent = &pll0;
1989         } else {
1990                 main_clock = &osc0;
1991                 cpu_clk.parent = &osc0;
1992         }
1993
1994         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1995                 pll0.parent = &osc1;
1996         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1997                 pll1.parent = &osc1;
1998
1999         genclk_init_parent(&gclk0);
2000         genclk_init_parent(&gclk1);
2001         genclk_init_parent(&gclk2);
2002         genclk_init_parent(&gclk3);
2003         genclk_init_parent(&gclk4);
2004 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2005         genclk_init_parent(&atmel_lcdfb0_pixclk);
2006 #endif
2007         genclk_init_parent(&abdac0_sample_clk);
2008
2009         /*
2010          * Turn on all clocks that have at least one user already, and
2011          * turn off everything else. We only do this for module
2012          * clocks, and even though it isn't particularly pretty to
2013          * check the address of the mode function, it should do the
2014          * trick...
2015          */
2016         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2017                 struct clk *clk = at32_clock_list[i];
2018
2019                 if (clk->users == 0)
2020                         continue;
2021
2022                 if (clk->mode == &cpu_clk_mode)
2023                         cpu_mask |= 1 << clk->index;
2024                 else if (clk->mode == &hsb_clk_mode)
2025                         hsb_mask |= 1 << clk->index;
2026                 else if (clk->mode == &pba_clk_mode)
2027                         pba_mask |= 1 << clk->index;
2028                 else if (clk->mode == &pbb_clk_mode)
2029                         pbb_mask |= 1 << clk->index;
2030         }
2031
2032         pm_writel(CPU_MASK, cpu_mask);
2033         pm_writel(HSB_MASK, hsb_mask);
2034         pm_writel(PBA_MASK, pba_mask);
2035         pm_writel(PBB_MASK, pbb_mask);
2036 }