arch/avr32/mach-at32ap/at32ap7000.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/fb.h>
  10 #include <linux/init.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/spi/spi.h>
  14
  15 #include <asm/io.h>
  16
  17 #include <asm/arch/at32ap7000.h>
  18 #include <asm/arch/board.h>
  19 #include <asm/arch/portmux.h>
  20
  21 #include <video/atmel_lcdc.h>
  22
  23 #include "clock.h"
  24 #include "hmatrix.h"
  25 #include "pio.h"
  26 #include "pm.h"
  27
  28 /*
  29  * We can reduce the code size a bit by using a constant here. Since
  30  * this file is completely chip-specific, it's safe to not use
  31  * ioremap. Generic drivers should of course never do this.
  32  */
  33 #define AT32_PM_BASE    0xfff00000
  34
  35 #define PBMEM(base)                                     \
  36         {                                               \
  37                 .start          = base,                 \
  38                 .end            = base + 0x3ff,         \
  39                 .flags          = IORESOURCE_MEM,       \
  40         }
  41 #define IRQ(num)                                        \
  42         {                                               \
  43                 .start          = num,                  \
  44                 .end            = num,                  \
  45                 .flags          = IORESOURCE_IRQ,       \
  46         }
  47 #define NAMED_IRQ(num, _name)                           \
  48         {                                               \
  49                 .start          = num,                  \
  50                 .end            = num,                  \
  51                 .name           = _name,                \
  52                 .flags          = IORESOURCE_IRQ,       \
  53         }
  54
  55 /* REVISIT these assume *every* device supports DMA, but several
  56  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  57  */
  58 #define DEFINE_DEV(_name, _id)                                  \
  59 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  60 static struct platform_device _name##_id##_device = {           \
  61         .name           = #_name,                               \
  62         .id             = _id,                                  \
  63         .dev            = {                                     \
  64                 .dma_mask = &_name##_id##_dma_mask,             \
  65                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  66         },                                                      \
  67         .resource       = _name##_id##_resource,                \
  68         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  69 }
  70 #define DEFINE_DEV_DATA(_name, _id)                             \
  71 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  72 static struct platform_device _name##_id##_device = {           \
  73         .name           = #_name,                               \
  74         .id             = _id,                                  \
  75         .dev            = {                                     \
  76                 .dma_mask = &_name##_id##_dma_mask,             \
  77                 .platform_data  = &_name##_id##_data,           \
  78                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  79         },                                                      \
  80         .resource       = _name##_id##_resource,                \
  81         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  82 }
  83
  84 #define select_peripheral(pin, periph, flags)                   \
  85         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  86
  87 #define DEV_CLK(_name, devname, bus, _index)                    \
  88 static struct clk devname##_##_name = {                         \
  89         .name           = #_name,                               \
  90         .dev            = &devname##_device.dev,                \
  91         .parent         = &bus##_clk,                           \
  92         .mode           = bus##_clk_mode,                       \
  93         .get_rate       = bus##_clk_get_rate,                   \
  94         .index          = _index,                               \
  95 }
  96
  97 static DEFINE_SPINLOCK(pm_lock);
  98
  99 unsigned long at32ap7000_osc_rates[3] = {
 100         [0] = 32768,
 101         /* FIXME: these are ATSTK1002-specific */
 102         [1] = 20000000,
 103         [2] = 12000000,
 104 };
 105
 106 static unsigned long osc_get_rate(struct clk *clk)
 107 {
 108         return at32ap7000_osc_rates[clk->index];
 109 }
 110
 111 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 112 {
 113         unsigned long div, mul, rate;
 114
 115         if (!(control & PM_BIT(PLLEN)))
 116                 return 0;
 117
 118         div = PM_BFEXT(PLLDIV, control) + 1;
 119         mul = PM_BFEXT(PLLMUL, control) + 1;
 120
 121         rate = clk->parent->get_rate(clk->parent);
 122         rate = (rate + div / 2) / div;
 123         rate *= mul;
 124
 125         return rate;
 126 }
 127
 128 static unsigned long pll0_get_rate(struct clk *clk)
 129 {
 130         u32 control;
 131
 132         control = pm_readl(PLL0);
 133
 134         return pll_get_rate(clk, control);
 135 }
 136
 137 static unsigned long pll1_get_rate(struct clk *clk)
 138 {
 139         u32 control;
 140
 141         control = pm_readl(PLL1);
 142
 143         return pll_get_rate(clk, control);
 144 }
 145
 146 /*
 147  * The AT32AP7000 has five primary clock sources: One 32kHz
 148  * oscillator, two crystal oscillators and two PLLs.
 149  */
 150 static struct clk osc32k = {
 151         .name           = "osc32k",
 152         .get_rate       = osc_get_rate,
 153         .users          = 1,
 154         .index          = 0,
 155 };
 156 static struct clk osc0 = {
 157         .name           = "osc0",
 158         .get_rate       = osc_get_rate,
 159         .users          = 1,
 160         .index          = 1,
 161 };
 162 static struct clk osc1 = {
 163         .name           = "osc1",
 164         .get_rate       = osc_get_rate,
 165         .index          = 2,
 166 };
 167 static struct clk pll0 = {
 168         .name           = "pll0",
 169         .get_rate       = pll0_get_rate,
 170         .parent         = &osc0,
 171 };
 172 static struct clk pll1 = {
 173         .name           = "pll1",
 174         .get_rate       = pll1_get_rate,
 175         .parent         = &osc0,
 176 };
 177
 178 /*
 179  * The main clock can be either osc0 or pll0.  The boot loader may
 180  * have chosen one for us, so we don't really know which one until we
 181  * have a look at the SM.
 182  */
 183 static struct clk *main_clock;
 184
 185 /*
 186  * Synchronous clocks are generated from the main clock. The clocks
 187  * must satisfy the constraint
 188  *   fCPU >= fHSB >= fPB
 189  * i.e. each clock must not be faster than its parent.
 190  */
 191 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 192 {
 193         return main_clock->get_rate(main_clock) >> shift;
 194 };
 195
 196 static void cpu_clk_mode(struct clk *clk, int enabled)
 197 {
 198         unsigned long flags;
 199         u32 mask;
 200
 201         spin_lock_irqsave(&pm_lock, flags);
 202         mask = pm_readl(CPU_MASK);
 203         if (enabled)
 204                 mask |= 1 << clk->index;
 205         else
 206                 mask &= ~(1 << clk->index);
 207         pm_writel(CPU_MASK, mask);
 208         spin_unlock_irqrestore(&pm_lock, flags);
 209 }
 210
 211 static unsigned long cpu_clk_get_rate(struct clk *clk)
 212 {
 213         unsigned long cksel, shift = 0;
 214
 215         cksel = pm_readl(CKSEL);
 216         if (cksel & PM_BIT(CPUDIV))
 217                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 218
 219         return bus_clk_get_rate(clk, shift);
 220 }
 221
 222 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 223 {
 224         u32 control;
 225         unsigned long parent_rate, child_div, actual_rate, div;
 226
 227         parent_rate = clk->parent->get_rate(clk->parent);
 228         control = pm_readl(CKSEL);
 229
 230         if (control & PM_BIT(HSBDIV))
 231                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 232         else
 233                 child_div = 1;
 234
 235         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 236                 actual_rate = parent_rate;
 237                 control &= ~PM_BIT(CPUDIV);
 238         } else {
 239                 unsigned int cpusel;
 240                 div = (parent_rate + rate / 2) / rate;
 241                 if (div > child_div)
 242                         div = child_div;
 243                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 244                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 245                 actual_rate = parent_rate / (1 << (cpusel + 1));
 246         }
 247
 248         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 249                         clk->name, rate, actual_rate);
 250
 251         if (apply)
 252                 pm_writel(CKSEL, control);
 253
 254         return actual_rate;
 255 }
 256
 257 static void hsb_clk_mode(struct clk *clk, int enabled)
 258 {
 259         unsigned long flags;
 260         u32 mask;
 261
 262         spin_lock_irqsave(&pm_lock, flags);
 263         mask = pm_readl(HSB_MASK);
 264         if (enabled)
 265                 mask |= 1 << clk->index;
 266         else
 267                 mask &= ~(1 << clk->index);
 268         pm_writel(HSB_MASK, mask);
 269         spin_unlock_irqrestore(&pm_lock, flags);
 270 }
 271
 272 static unsigned long hsb_clk_get_rate(struct clk *clk)
 273 {
 274         unsigned long cksel, shift = 0;
 275
 276         cksel = pm_readl(CKSEL);
 277         if (cksel & PM_BIT(HSBDIV))
 278                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 279
 280         return bus_clk_get_rate(clk, shift);
 281 }
 282
 283 static void pba_clk_mode(struct clk *clk, int enabled)
 284 {
 285         unsigned long flags;
 286         u32 mask;
 287
 288         spin_lock_irqsave(&pm_lock, flags);
 289         mask = pm_readl(PBA_MASK);
 290         if (enabled)
 291                 mask |= 1 << clk->index;
 292         else
 293                 mask &= ~(1 << clk->index);
 294         pm_writel(PBA_MASK, mask);
 295         spin_unlock_irqrestore(&pm_lock, flags);
 296 }
 297
 298 static unsigned long pba_clk_get_rate(struct clk *clk)
 299 {
 300         unsigned long cksel, shift = 0;
 301
 302         cksel = pm_readl(CKSEL);
 303         if (cksel & PM_BIT(PBADIV))
 304                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 305
 306         return bus_clk_get_rate(clk, shift);
 307 }
 308
 309 static void pbb_clk_mode(struct clk *clk, int enabled)
 310 {
 311         unsigned long flags;
 312         u32 mask;
 313
 314         spin_lock_irqsave(&pm_lock, flags);
 315         mask = pm_readl(PBB_MASK);
 316         if (enabled)
 317                 mask |= 1 << clk->index;
 318         else
 319                 mask &= ~(1 << clk->index);
 320         pm_writel(PBB_MASK, mask);
 321         spin_unlock_irqrestore(&pm_lock, flags);
 322 }
 323
 324 static unsigned long pbb_clk_get_rate(struct clk *clk)
 325 {
 326         unsigned long cksel, shift = 0;
 327
 328         cksel = pm_readl(CKSEL);
 329         if (cksel & PM_BIT(PBBDIV))
 330                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 331
 332         return bus_clk_get_rate(clk, shift);
 333 }
 334
 335 static struct clk cpu_clk = {
 336         .name           = "cpu",
 337         .get_rate       = cpu_clk_get_rate,
 338         .set_rate       = cpu_clk_set_rate,
 339         .users          = 1,
 340 };
 341 static struct clk hsb_clk = {
 342         .name           = "hsb",
 343         .parent         = &cpu_clk,
 344         .get_rate       = hsb_clk_get_rate,
 345 };
 346 static struct clk pba_clk = {
 347         .name           = "pba",
 348         .parent         = &hsb_clk,
 349         .mode           = hsb_clk_mode,
 350         .get_rate       = pba_clk_get_rate,
 351         .index          = 1,
 352 };
 353 static struct clk pbb_clk = {
 354         .name           = "pbb",
 355         .parent         = &hsb_clk,
 356         .mode           = hsb_clk_mode,
 357         .get_rate       = pbb_clk_get_rate,
 358         .users          = 1,
 359         .index          = 2,
 360 };
 361
 362 /* --------------------------------------------------------------------
 363  *  Generic Clock operations
 364  * -------------------------------------------------------------------- */
 365
 366 static void genclk_mode(struct clk *clk, int enabled)
 367 {
 368         u32 control;
 369
 370         control = pm_readl(GCCTRL(clk->index));
 371         if (enabled)
 372                 control |= PM_BIT(CEN);
 373         else
 374                 control &= ~PM_BIT(CEN);
 375         pm_writel(GCCTRL(clk->index), control);
 376 }
 377
 378 static unsigned long genclk_get_rate(struct clk *clk)
 379 {
 380         u32 control;
 381         unsigned long div = 1;
 382
 383         control = pm_readl(GCCTRL(clk->index));
 384         if (control & PM_BIT(DIVEN))
 385                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 386
 387         return clk->parent->get_rate(clk->parent) / div;
 388 }
 389
 390 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 391 {
 392         u32 control;
 393         unsigned long parent_rate, actual_rate, div;
 394
 395         parent_rate = clk->parent->get_rate(clk->parent);
 396         control = pm_readl(GCCTRL(clk->index));
 397
 398         if (rate > 3 * parent_rate / 4) {
 399                 actual_rate = parent_rate;
 400                 control &= ~PM_BIT(DIVEN);
 401         } else {
 402                 div = (parent_rate + rate) / (2 * rate) - 1;
 403                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 404                 actual_rate = parent_rate / (2 * (div + 1));
 405         }
 406
 407         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 408                 clk->name, rate, actual_rate);
 409
 410         if (apply)
 411                 pm_writel(GCCTRL(clk->index), control);
 412
 413         return actual_rate;
 414 }
 415
 416 int genclk_set_parent(struct clk *clk, struct clk *parent)
 417 {
 418         u32 control;
 419
 420         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 421                 clk->name, parent->name, clk->parent->name);
 422
 423         control = pm_readl(GCCTRL(clk->index));
 424
 425         if (parent == &osc1 || parent == &pll1)
 426                 control |= PM_BIT(OSCSEL);
 427         else if (parent == &osc0 || parent == &pll0)
 428                 control &= ~PM_BIT(OSCSEL);
 429         else
 430                 return -EINVAL;
 431
 432         if (parent == &pll0 || parent == &pll1)
 433                 control |= PM_BIT(PLLSEL);
 434         else
 435                 control &= ~PM_BIT(PLLSEL);
 436
 437         pm_writel(GCCTRL(clk->index), control);
 438         clk->parent = parent;
 439
 440         return 0;
 441 }
 442
 443 static void __init genclk_init_parent(struct clk *clk)
 444 {
 445         u32 control;
 446         struct clk *parent;
 447
 448         BUG_ON(clk->index > 7);
 449
 450         control = pm_readl(GCCTRL(clk->index));
 451         if (control & PM_BIT(OSCSEL))
 452                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 453         else
 454                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 455
 456         clk->parent = parent;
 457 }
 458
 459 /* --------------------------------------------------------------------
 460  *  System peripherals
 461  * -------------------------------------------------------------------- */
 462 static struct resource at32_pm0_resource[] = {
 463         {
 464                 .start  = 0xfff00000,
 465                 .end    = 0xfff0007f,
 466                 .flags  = IORESOURCE_MEM,
 467         },
 468         IRQ(20),
 469 };
 470
 471 static struct resource at32ap700x_rtc0_resource[] = {
 472         {
 473                 .start  = 0xfff00080,
 474                 .end    = 0xfff000af,
 475                 .flags  = IORESOURCE_MEM,
 476         },
 477         IRQ(21),
 478 };
 479
 480 static struct resource at32_wdt0_resource[] = {
 481         {
 482                 .start  = 0xfff000b0,
 483                 .end    = 0xfff000bf,
 484                 .flags  = IORESOURCE_MEM,
 485         },
 486 };
 487
 488 static struct resource at32_eic0_resource[] = {
 489         {
 490                 .start  = 0xfff00100,
 491                 .end    = 0xfff0013f,
 492                 .flags  = IORESOURCE_MEM,
 493         },
 494         IRQ(19),
 495 };
 496
 497 DEFINE_DEV(at32_pm, 0);
 498 DEFINE_DEV(at32ap700x_rtc, 0);
 499 DEFINE_DEV(at32_wdt, 0);
 500 DEFINE_DEV(at32_eic, 0);
 501
 502 /*
 503  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 504  * is always running.
 505  */
 506 static struct clk at32_pm_pclk = {
 507         .name           = "pclk",
 508         .dev            = &at32_pm0_device.dev,
 509         .parent         = &pbb_clk,
 510         .mode           = pbb_clk_mode,
 511         .get_rate       = pbb_clk_get_rate,
 512         .users          = 1,
 513         .index          = 0,
 514 };
 515
 516 static struct resource intc0_resource[] = {
 517         PBMEM(0xfff00400),
 518 };
 519 struct platform_device at32_intc0_device = {
 520         .name           = "intc",
 521         .id             = 0,
 522         .resource       = intc0_resource,
 523         .num_resources  = ARRAY_SIZE(intc0_resource),
 524 };
 525 DEV_CLK(pclk, at32_intc0, pbb, 1);
 526
 527 static struct clk ebi_clk = {
 528         .name           = "ebi",
 529         .parent         = &hsb_clk,
 530         .mode           = hsb_clk_mode,
 531         .get_rate       = hsb_clk_get_rate,
 532         .users          = 1,
 533 };
 534 static struct clk hramc_clk = {
 535         .name           = "hramc",
 536         .parent         = &hsb_clk,
 537         .mode           = hsb_clk_mode,
 538         .get_rate       = hsb_clk_get_rate,
 539         .users          = 1,
 540         .index          = 3,
 541 };
 542
 543 static struct resource smc0_resource[] = {
 544         PBMEM(0xfff03400),
 545 };
 546 DEFINE_DEV(smc, 0);
 547 DEV_CLK(pclk, smc0, pbb, 13);
 548 DEV_CLK(mck, smc0, hsb, 0);
 549
 550 static struct platform_device pdc_device = {
 551         .name           = "pdc",
 552         .id             = 0,
 553 };
 554 DEV_CLK(hclk, pdc, hsb, 4);
 555 DEV_CLK(pclk, pdc, pba, 16);
 556
 557 static struct clk pico_clk = {
 558         .name           = "pico",
 559         .parent         = &cpu_clk,
 560         .mode           = cpu_clk_mode,
 561         .get_rate       = cpu_clk_get_rate,
 562         .users          = 1,
 563 };
 564
 565 /* --------------------------------------------------------------------
 566  * HMATRIX
 567  * -------------------------------------------------------------------- */
 568
 569 static struct clk hmatrix_clk = {
 570         .name           = "hmatrix_clk",
 571         .parent         = &pbb_clk,
 572         .mode           = pbb_clk_mode,
 573         .get_rate       = pbb_clk_get_rate,
 574         .index          = 2,
 575         .users          = 1,
 576 };
 577 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 578
 579 #define hmatrix_readl(reg)                                      \
 580         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 581 #define hmatrix_writel(reg,value)                               \
 582         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 583
 584 /*
 585  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 586  * External Bus Interface (EBI). This can be used to enable special
 587  * features like CompactFlash support, NAND Flash support, etc. on
 588  * certain chipselects.
 589  */
 590 static inline void set_ebi_sfr_bits(u32 mask)
 591 {
 592         u32 sfr;
 593
 594         clk_enable(&hmatrix_clk);
 595         sfr = hmatrix_readl(SFR4);
 596         sfr |= mask;
 597         hmatrix_writel(SFR4, sfr);
 598         clk_disable(&hmatrix_clk);
 599 }
 600
 601 /* --------------------------------------------------------------------
 602  *  System Timer/Counter (TC)
 603  * -------------------------------------------------------------------- */
 604 static struct resource at32_systc0_resource[] = {
 605         PBMEM(0xfff00c00),
 606         IRQ(22),
 607 };
 608 struct platform_device at32_systc0_device = {
 609         .name           = "systc",
 610         .id             = 0,
 611         .resource       = at32_systc0_resource,
 612         .num_resources  = ARRAY_SIZE(at32_systc0_resource),
 613 };
 614 DEV_CLK(pclk, at32_systc0, pbb, 3);
 615
 616 /* --------------------------------------------------------------------
 617  *  PIO
 618  * -------------------------------------------------------------------- */
 619
 620 static struct resource pio0_resource[] = {
 621         PBMEM(0xffe02800),
 622         IRQ(13),
 623 };
 624 DEFINE_DEV(pio, 0);
 625 DEV_CLK(mck, pio0, pba, 10);
 626
 627 static struct resource pio1_resource[] = {
 628         PBMEM(0xffe02c00),
 629         IRQ(14),
 630 };
 631 DEFINE_DEV(pio, 1);
 632 DEV_CLK(mck, pio1, pba, 11);
 633
 634 static struct resource pio2_resource[] = {
 635         PBMEM(0xffe03000),
 636         IRQ(15),
 637 };
 638 DEFINE_DEV(pio, 2);
 639 DEV_CLK(mck, pio2, pba, 12);
 640
 641 static struct resource pio3_resource[] = {
 642         PBMEM(0xffe03400),
 643         IRQ(16),
 644 };
 645 DEFINE_DEV(pio, 3);
 646 DEV_CLK(mck, pio3, pba, 13);
 647
 648 static struct resource pio4_resource[] = {
 649         PBMEM(0xffe03800),
 650         IRQ(17),
 651 };
 652 DEFINE_DEV(pio, 4);
 653 DEV_CLK(mck, pio4, pba, 14);
 654
 655 void __init at32_add_system_devices(void)
 656 {
 657         platform_device_register(&at32_pm0_device);
 658         platform_device_register(&at32_intc0_device);
 659         platform_device_register(&at32ap700x_rtc0_device);
 660         platform_device_register(&at32_wdt0_device);
 661         platform_device_register(&at32_eic0_device);
 662         platform_device_register(&smc0_device);
 663         platform_device_register(&pdc_device);
 664
 665         platform_device_register(&at32_systc0_device);
 666
 667         platform_device_register(&pio0_device);
 668         platform_device_register(&pio1_device);
 669         platform_device_register(&pio2_device);
 670         platform_device_register(&pio3_device);
 671         platform_device_register(&pio4_device);
 672 }
 673
 674 /* --------------------------------------------------------------------
 675  *  USART
 676  * -------------------------------------------------------------------- */
 677
 678 static struct atmel_uart_data atmel_usart0_data = {
 679         .use_dma_tx     = 1,
 680         .use_dma_rx     = 1,
 681 };
 682 static struct resource atmel_usart0_resource[] = {
 683         PBMEM(0xffe00c00),
 684         IRQ(6),
 685 };
 686 DEFINE_DEV_DATA(atmel_usart, 0);
 687 DEV_CLK(usart, atmel_usart0, pba, 4);
 688
 689 static struct atmel_uart_data atmel_usart1_data = {
 690         .use_dma_tx     = 1,
 691         .use_dma_rx     = 1,
 692 };
 693 static struct resource atmel_usart1_resource[] = {
 694         PBMEM(0xffe01000),
 695         IRQ(7),
 696 };
 697 DEFINE_DEV_DATA(atmel_usart, 1);
 698 DEV_CLK(usart, atmel_usart1, pba, 4);
 699
 700 static struct atmel_uart_data atmel_usart2_data = {
 701         .use_dma_tx     = 1,
 702         .use_dma_rx     = 1,
 703 };
 704 static struct resource atmel_usart2_resource[] = {
 705         PBMEM(0xffe01400),
 706         IRQ(8),
 707 };
 708 DEFINE_DEV_DATA(atmel_usart, 2);
 709 DEV_CLK(usart, atmel_usart2, pba, 5);
 710
 711 static struct atmel_uart_data atmel_usart3_data = {
 712         .use_dma_tx     = 1,
 713         .use_dma_rx     = 1,
 714 };
 715 static struct resource atmel_usart3_resource[] = {
 716         PBMEM(0xffe01800),
 717         IRQ(9),
 718 };
 719 DEFINE_DEV_DATA(atmel_usart, 3);
 720 DEV_CLK(usart, atmel_usart3, pba, 6);
 721
 722 static inline void configure_usart0_pins(void)
 723 {
 724         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 725         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 726 }
 727
 728 static inline void configure_usart1_pins(void)
 729 {
 730         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 731         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 732 }
 733
 734 static inline void configure_usart2_pins(void)
 735 {
 736         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 737         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 738 }
 739
 740 static inline void configure_usart3_pins(void)
 741 {
 742         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 743         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 744 }
 745
 746 static struct platform_device *__initdata at32_usarts[4];
 747
 748 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 749 {
 750         struct platform_device *pdev;
 751
 752         switch (hw_id) {
 753         case 0:
 754                 pdev = &atmel_usart0_device;
 755                 configure_usart0_pins();
 756                 break;
 757         case 1:
 758                 pdev = &atmel_usart1_device;
 759                 configure_usart1_pins();
 760                 break;
 761         case 2:
 762                 pdev = &atmel_usart2_device;
 763                 configure_usart2_pins();
 764                 break;
 765         case 3:
 766                 pdev = &atmel_usart3_device;
 767                 configure_usart3_pins();
 768                 break;
 769         default:
 770                 return;
 771         }
 772
 773         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 774                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 775                 struct atmel_uart_data *data = pdev->dev.platform_data;
 776                 data->regs = (void __iomem *)pdev->resource[0].start;
 777         }
 778
 779         pdev->id = line;
 780         at32_usarts[line] = pdev;
 781 }
 782
 783 struct platform_device *__init at32_add_device_usart(unsigned int id)
 784 {
 785         platform_device_register(at32_usarts[id]);
 786         return at32_usarts[id];
 787 }
 788
 789 struct platform_device *atmel_default_console_device;
 790
 791 void __init at32_setup_serial_console(unsigned int usart_id)
 792 {
 793         atmel_default_console_device = at32_usarts[usart_id];
 794 }
 795
 796 /* --------------------------------------------------------------------
 797  *  Ethernet
 798  * -------------------------------------------------------------------- */
 799
 800 static struct eth_platform_data macb0_data;
 801 static struct resource macb0_resource[] = {
 802         PBMEM(0xfff01800),
 803         IRQ(25),
 804 };
 805 DEFINE_DEV_DATA(macb, 0);
 806 DEV_CLK(hclk, macb0, hsb, 8);
 807 DEV_CLK(pclk, macb0, pbb, 6);
 808
 809 static struct eth_platform_data macb1_data;
 810 static struct resource macb1_resource[] = {
 811         PBMEM(0xfff01c00),
 812         IRQ(26),
 813 };
 814 DEFINE_DEV_DATA(macb, 1);
 815 DEV_CLK(hclk, macb1, hsb, 9);
 816 DEV_CLK(pclk, macb1, pbb, 7);
 817
 818 struct platform_device *__init
 819 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 820 {
 821         struct platform_device *pdev;
 822
 823         switch (id) {
 824         case 0:
 825                 pdev = &macb0_device;
 826
 827                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 828                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 829                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 830                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 831                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 832                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 833                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 834                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 835                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 836                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 837
 838                 if (!data->is_rmii) {
 839                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 840                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 841                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 842                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 843                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 844                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 845                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 846                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 847                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 848                 }
 849                 break;
 850
 851         case 1:
 852                 pdev = &macb1_device;
 853
 854                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 855                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 856                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 857                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 858                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 859                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 860                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 861                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 862                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 863                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 864
 865                 if (!data->is_rmii) {
 866                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 867                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 868                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 869                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 870                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 871                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 872                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 873                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 874                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 875                 }
 876                 break;
 877
 878         default:
 879                 return NULL;
 880         }
 881
 882         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 883         platform_device_register(pdev);
 884
 885         return pdev;
 886 }
 887
 888 /* --------------------------------------------------------------------
 889  *  SPI
 890  * -------------------------------------------------------------------- */
 891 static struct resource atmel_spi0_resource[] = {
 892         PBMEM(0xffe00000),
 893         IRQ(3),
 894 };
 895 DEFINE_DEV(atmel_spi, 0);
 896 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 897
 898 static struct resource atmel_spi1_resource[] = {
 899         PBMEM(0xffe00400),
 900         IRQ(4),
 901 };
 902 DEFINE_DEV(atmel_spi, 1);
 903 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 904
 905 static void __init
 906 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 907                       unsigned int n, const u8 *pins)
 908 {
 909         unsigned int pin, mode;
 910
 911         for (; n; n--, b++) {
 912                 b->bus_num = bus_num;
 913                 if (b->chip_select >= 4)
 914                         continue;
 915                 pin = (unsigned)b->controller_data;
 916                 if (!pin) {
 917                         pin = pins[b->chip_select];
 918                         b->controller_data = (void *)pin;
 919                 }
 920                 mode = AT32_GPIOF_OUTPUT;
 921                 if (!(b->mode & SPI_CS_HIGH))
 922                         mode |= AT32_GPIOF_HIGH;
 923                 at32_select_gpio(pin, mode);
 924         }
 925 }
 926
 927 struct platform_device *__init
 928 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 929 {
 930         /*
 931          * Manage the chipselects as GPIOs, normally using the same pins
 932          * the SPI controller expects; but boards can use other pins.
 933          */
 934         static u8 __initdata spi0_pins[] =
 935                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 936                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 937         static u8 __initdata spi1_pins[] =
 938                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 939                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 940         struct platform_device *pdev;
 941
 942         switch (id) {
 943         case 0:
 944                 pdev = &atmel_spi0_device;
 945                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 946                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 947                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 948                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 949                 break;
 950
 951         case 1:
 952                 pdev = &atmel_spi1_device;
 953                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 954                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 955                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 956                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 957                 break;
 958
 959         default:
 960                 return NULL;
 961         }
 962
 963         spi_register_board_info(b, n);
 964         platform_device_register(pdev);
 965         return pdev;
 966 }
 967
 968 /* --------------------------------------------------------------------
 969  *  LCDC
 970  * -------------------------------------------------------------------- */
 971 static struct atmel_lcdfb_info atmel_lcdfb0_data;
 972 static struct resource atmel_lcdfb0_resource[] = {
 973         {
 974                 .start          = 0xff000000,
 975                 .end            = 0xff000fff,
 976                 .flags          = IORESOURCE_MEM,
 977         },
 978         IRQ(1),
 979         {
 980                 /* Placeholder for pre-allocated fb memory */
 981                 .start          = 0x00000000,
 982                 .end            = 0x00000000,
 983                 .flags          = 0,
 984         },
 985 };
 986 DEFINE_DEV_DATA(atmel_lcdfb, 0);
 987 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
 988 static struct clk atmel_lcdfb0_pixclk = {
 989         .name           = "lcdc_clk",
 990         .dev            = &atmel_lcdfb0_device.dev,
 991         .mode           = genclk_mode,
 992         .get_rate       = genclk_get_rate,
 993         .set_rate       = genclk_set_rate,
 994         .set_parent     = genclk_set_parent,
 995         .index          = 7,
 996 };
 997
 998 struct platform_device *__init
 999 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1000                      unsigned long fbmem_start, unsigned long fbmem_len)
1001 {
1002         struct platform_device *pdev;
1003         struct atmel_lcdfb_info *info;
1004         struct fb_monspecs *monspecs;
1005         struct fb_videomode *modedb;
1006         unsigned int modedb_size;
1007
1008         /*
1009          * Do a deep copy of the fb data, monspecs and modedb. Make
1010          * sure all allocations are done before setting up the
1011          * portmux.
1012          */
1013         monspecs = kmemdup(data->default_monspecs,
1014                            sizeof(struct fb_monspecs), GFP_KERNEL);
1015         if (!monspecs)
1016                 return NULL;
1017
1018         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1019         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1020         if (!modedb)
1021                 goto err_dup_modedb;
1022         monspecs->modedb = modedb;
1023
1024         switch (id) {
1025         case 0:
1026                 pdev = &atmel_lcdfb0_device;
1027                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1028                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1029                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1030                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1031                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1032                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1033                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1034                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1035                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1036                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1037                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1038                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1039                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1040                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1041                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1042                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1043                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1044                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1045                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1046                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1047                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1048                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1049                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1050                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1051                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1052                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1053                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1054                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1055                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1056                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1057                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1058
1059                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1060                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1061                 break;
1062
1063         default:
1064                 goto err_invalid_id;
1065         }
1066
1067         if (fbmem_len) {
1068                 pdev->resource[2].start = fbmem_start;
1069                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1070                 pdev->resource[2].flags = IORESOURCE_MEM;
1071         }
1072
1073         info = pdev->dev.platform_data;
1074         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1075         info->default_monspecs = monspecs;
1076
1077         platform_device_register(pdev);
1078         return pdev;
1079
1080 err_invalid_id:
1081         kfree(modedb);
1082 err_dup_modedb:
1083         kfree(monspecs);
1084         return NULL;
1085 }
1086
1087 /* --------------------------------------------------------------------
1088  *  GCLK
1089  * -------------------------------------------------------------------- */
1090 static struct clk gclk0 = {
1091         .name           = "gclk0",
1092         .mode           = genclk_mode,
1093         .get_rate       = genclk_get_rate,
1094         .set_rate       = genclk_set_rate,
1095         .set_parent     = genclk_set_parent,
1096         .index          = 0,
1097 };
1098 static struct clk gclk1 = {
1099         .name           = "gclk1",
1100         .mode           = genclk_mode,
1101         .get_rate       = genclk_get_rate,
1102         .set_rate       = genclk_set_rate,
1103         .set_parent     = genclk_set_parent,
1104         .index          = 1,
1105 };
1106 static struct clk gclk2 = {
1107         .name           = "gclk2",
1108         .mode           = genclk_mode,
1109         .get_rate       = genclk_get_rate,
1110         .set_rate       = genclk_set_rate,
1111         .set_parent     = genclk_set_parent,
1112         .index          = 2,
1113 };
1114 static struct clk gclk3 = {
1115         .name           = "gclk3",
1116         .mode           = genclk_mode,
1117         .get_rate       = genclk_get_rate,
1118         .set_rate       = genclk_set_rate,
1119         .set_parent     = genclk_set_parent,
1120         .index          = 3,
1121 };
1122 static struct clk gclk4 = {
1123         .name           = "gclk4",
1124         .mode           = genclk_mode,
1125         .get_rate       = genclk_get_rate,
1126         .set_rate       = genclk_set_rate,
1127         .set_parent     = genclk_set_parent,
1128         .index          = 4,
1129 };
1130
1131 struct clk *at32_clock_list[] = {
1132         &osc32k,
1133         &osc0,
1134         &osc1,
1135         &pll0,
1136         &pll1,
1137         &cpu_clk,
1138         &hsb_clk,
1139         &pba_clk,
1140         &pbb_clk,
1141         &at32_pm_pclk,
1142         &at32_intc0_pclk,
1143         &hmatrix_clk,
1144         &ebi_clk,
1145         &hramc_clk,
1146         &smc0_pclk,
1147         &smc0_mck,
1148         &pdc_hclk,
1149         &pdc_pclk,
1150         &pico_clk,
1151         &pio0_mck,
1152         &pio1_mck,
1153         &pio2_mck,
1154         &pio3_mck,
1155         &pio4_mck,
1156         &at32_systc0_pclk,
1157         &atmel_usart0_usart,
1158         &atmel_usart1_usart,
1159         &atmel_usart2_usart,
1160         &atmel_usart3_usart,
1161         &macb0_hclk,
1162         &macb0_pclk,
1163         &macb1_hclk,
1164         &macb1_pclk,
1165         &atmel_spi0_spi_clk,
1166         &atmel_spi1_spi_clk,
1167         &atmel_lcdfb0_hck1,
1168         &atmel_lcdfb0_pixclk,
1169         &gclk0,
1170         &gclk1,
1171         &gclk2,
1172         &gclk3,
1173         &gclk4,
1174 };
1175 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1176
1177 void __init at32_portmux_init(void)
1178 {
1179         at32_init_pio(&pio0_device);
1180         at32_init_pio(&pio1_device);
1181         at32_init_pio(&pio2_device);
1182         at32_init_pio(&pio3_device);
1183         at32_init_pio(&pio4_device);
1184 }
1185
1186 void __init at32_clock_init(void)
1187 {
1188         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1189         int i;
1190
1191         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1192                 main_clock = &pll0;
1193                 cpu_clk.parent = &pll0;
1194         } else {
1195                 main_clock = &osc0;
1196                 cpu_clk.parent = &osc0;
1197         }
1198
1199         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1200                 pll0.parent = &osc1;
1201         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1202                 pll1.parent = &osc1;
1203
1204         genclk_init_parent(&gclk0);
1205         genclk_init_parent(&gclk1);
1206         genclk_init_parent(&gclk2);
1207         genclk_init_parent(&gclk3);
1208         genclk_init_parent(&gclk4);
1209         genclk_init_parent(&atmel_lcdfb0_pixclk);
1210
1211         /*
1212          * Turn on all clocks that have at least one user already, and
1213          * turn off everything else. We only do this for module
1214          * clocks, and even though it isn't particularly pretty to
1215          * check the address of the mode function, it should do the
1216          * trick...
1217          */
1218         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1219                 struct clk *clk = at32_clock_list[i];
1220
1221                 if (clk->users == 0)
1222                         continue;
1223
1224                 if (clk->mode == &cpu_clk_mode)
1225                         cpu_mask |= 1 << clk->index;
1226                 else if (clk->mode == &hsb_clk_mode)
1227                         hsb_mask |= 1 << clk->index;
1228                 else if (clk->mode == &pba_clk_mode)
1229                         pba_mask |= 1 << clk->index;
1230                 else if (clk->mode == &pbb_clk_mode)
1231                         pbb_mask |= 1 << clk->index;
1232         }
1233
1234         pm_writel(CPU_MASK, cpu_mask);
1235         pm_writel(HSB_MASK, hsb_mask);
1236         pm_writel(PBA_MASK, pba_mask);
1237         pm_writel(PBB_MASK, pbb_mask);
1238 }