arch/avr32/mach-at32ap/at32ap7000.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/fb.h>
  10 #include <linux/init.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/spi/spi.h>
  14
  15 #include <asm/io.h>
  16
  17 #include <asm/arch/at32ap7000.h>
  18 #include <asm/arch/board.h>
  19 #include <asm/arch/portmux.h>
  20
  21 #include <video/atmel_lcdc.h>
  22
  23 #include "clock.h"
  24 #include "hmatrix.h"
  25 #include "pio.h"
  26 #include "pm.h"
  27
  28 /*
  29  * We can reduce the code size a bit by using a constant here. Since
  30  * this file is completely chip-specific, it's safe to not use
  31  * ioremap. Generic drivers should of course never do this.
  32  */
  33 #define AT32_PM_BASE    0xfff00000
  34
  35 #define PBMEM(base)                                     \
  36         {                                               \
  37                 .start          = base,                 \
  38                 .end            = base + 0x3ff,         \
  39                 .flags          = IORESOURCE_MEM,       \
  40         }
  41 #define IRQ(num)                                        \
  42         {                                               \
  43                 .start          = num,                  \
  44                 .end            = num,                  \
  45                 .flags          = IORESOURCE_IRQ,       \
  46         }
  47 #define NAMED_IRQ(num, _name)                           \
  48         {                                               \
  49                 .start          = num,                  \
  50                 .end            = num,                  \
  51                 .name           = _name,                \
  52                 .flags          = IORESOURCE_IRQ,       \
  53         }
  54
  55 /* REVISIT these assume *every* device supports DMA, but several
  56  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  57  */
  58 #define DEFINE_DEV(_name, _id)                                  \
  59 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  60 static struct platform_device _name##_id##_device = {           \
  61         .name           = #_name,                               \
  62         .id             = _id,                                  \
  63         .dev            = {                                     \
  64                 .dma_mask = &_name##_id##_dma_mask,             \
  65                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  66         },                                                      \
  67         .resource       = _name##_id##_resource,                \
  68         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  69 }
  70 #define DEFINE_DEV_DATA(_name, _id)                             \
  71 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  72 static struct platform_device _name##_id##_device = {           \
  73         .name           = #_name,                               \
  74         .id             = _id,                                  \
  75         .dev            = {                                     \
  76                 .dma_mask = &_name##_id##_dma_mask,             \
  77                 .platform_data  = &_name##_id##_data,           \
  78                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  79         },                                                      \
  80         .resource       = _name##_id##_resource,                \
  81         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  82 }
  83
  84 #define select_peripheral(pin, periph, flags)                   \
  85         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  86
  87 #define DEV_CLK(_name, devname, bus, _index)                    \
  88 static struct clk devname##_##_name = {                         \
  89         .name           = #_name,                               \
  90         .dev            = &devname##_device.dev,                \
  91         .parent         = &bus##_clk,                           \
  92         .mode           = bus##_clk_mode,                       \
  93         .get_rate       = bus##_clk_get_rate,                   \
  94         .index          = _index,                               \
  95 }
  96
  97 static DEFINE_SPINLOCK(pm_lock);
  98
  99 unsigned long at32ap7000_osc_rates[3] = {
 100         [0] = 32768,
 101         /* FIXME: these are ATSTK1002-specific */
 102         [1] = 20000000,
 103         [2] = 12000000,
 104 };
 105
 106 static unsigned long osc_get_rate(struct clk *clk)
 107 {
 108         return at32ap7000_osc_rates[clk->index];
 109 }
 110
 111 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 112 {
 113         unsigned long div, mul, rate;
 114
 115         if (!(control & PM_BIT(PLLEN)))
 116                 return 0;
 117
 118         div = PM_BFEXT(PLLDIV, control) + 1;
 119         mul = PM_BFEXT(PLLMUL, control) + 1;
 120
 121         rate = clk->parent->get_rate(clk->parent);
 122         rate = (rate + div / 2) / div;
 123         rate *= mul;
 124
 125         return rate;
 126 }
 127
 128 static unsigned long pll0_get_rate(struct clk *clk)
 129 {
 130         u32 control;
 131
 132         control = pm_readl(PLL0);
 133
 134         return pll_get_rate(clk, control);
 135 }
 136
 137 static unsigned long pll1_get_rate(struct clk *clk)
 138 {
 139         u32 control;
 140
 141         control = pm_readl(PLL1);
 142
 143         return pll_get_rate(clk, control);
 144 }
 145
 146 /*
 147  * The AT32AP7000 has five primary clock sources: One 32kHz
 148  * oscillator, two crystal oscillators and two PLLs.
 149  */
 150 static struct clk osc32k = {
 151         .name           = "osc32k",
 152         .get_rate       = osc_get_rate,
 153         .users          = 1,
 154         .index          = 0,
 155 };
 156 static struct clk osc0 = {
 157         .name           = "osc0",
 158         .get_rate       = osc_get_rate,
 159         .users          = 1,
 160         .index          = 1,
 161 };
 162 static struct clk osc1 = {
 163         .name           = "osc1",
 164         .get_rate       = osc_get_rate,
 165         .index          = 2,
 166 };
 167 static struct clk pll0 = {
 168         .name           = "pll0",
 169         .get_rate       = pll0_get_rate,
 170         .parent         = &osc0,
 171 };
 172 static struct clk pll1 = {
 173         .name           = "pll1",
 174         .get_rate       = pll1_get_rate,
 175         .parent         = &osc0,
 176 };
 177
 178 /*
 179  * The main clock can be either osc0 or pll0.  The boot loader may
 180  * have chosen one for us, so we don't really know which one until we
 181  * have a look at the SM.
 182  */
 183 static struct clk *main_clock;
 184
 185 /*
 186  * Synchronous clocks are generated from the main clock. The clocks
 187  * must satisfy the constraint
 188  *   fCPU >= fHSB >= fPB
 189  * i.e. each clock must not be faster than its parent.
 190  */
 191 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 192 {
 193         return main_clock->get_rate(main_clock) >> shift;
 194 };
 195
 196 static void cpu_clk_mode(struct clk *clk, int enabled)
 197 {
 198         unsigned long flags;
 199         u32 mask;
 200
 201         spin_lock_irqsave(&pm_lock, flags);
 202         mask = pm_readl(CPU_MASK);
 203         if (enabled)
 204                 mask |= 1 << clk->index;
 205         else
 206                 mask &= ~(1 << clk->index);
 207         pm_writel(CPU_MASK, mask);
 208         spin_unlock_irqrestore(&pm_lock, flags);
 209 }
 210
 211 static unsigned long cpu_clk_get_rate(struct clk *clk)
 212 {
 213         unsigned long cksel, shift = 0;
 214
 215         cksel = pm_readl(CKSEL);
 216         if (cksel & PM_BIT(CPUDIV))
 217                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 218
 219         return bus_clk_get_rate(clk, shift);
 220 }
 221
 222 static void hsb_clk_mode(struct clk *clk, int enabled)
 223 {
 224         unsigned long flags;
 225         u32 mask;
 226
 227         spin_lock_irqsave(&pm_lock, flags);
 228         mask = pm_readl(HSB_MASK);
 229         if (enabled)
 230                 mask |= 1 << clk->index;
 231         else
 232                 mask &= ~(1 << clk->index);
 233         pm_writel(HSB_MASK, mask);
 234         spin_unlock_irqrestore(&pm_lock, flags);
 235 }
 236
 237 static unsigned long hsb_clk_get_rate(struct clk *clk)
 238 {
 239         unsigned long cksel, shift = 0;
 240
 241         cksel = pm_readl(CKSEL);
 242         if (cksel & PM_BIT(HSBDIV))
 243                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 244
 245         return bus_clk_get_rate(clk, shift);
 246 }
 247
 248 static void pba_clk_mode(struct clk *clk, int enabled)
 249 {
 250         unsigned long flags;
 251         u32 mask;
 252
 253         spin_lock_irqsave(&pm_lock, flags);
 254         mask = pm_readl(PBA_MASK);
 255         if (enabled)
 256                 mask |= 1 << clk->index;
 257         else
 258                 mask &= ~(1 << clk->index);
 259         pm_writel(PBA_MASK, mask);
 260         spin_unlock_irqrestore(&pm_lock, flags);
 261 }
 262
 263 static unsigned long pba_clk_get_rate(struct clk *clk)
 264 {
 265         unsigned long cksel, shift = 0;
 266
 267         cksel = pm_readl(CKSEL);
 268         if (cksel & PM_BIT(PBADIV))
 269                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 270
 271         return bus_clk_get_rate(clk, shift);
 272 }
 273
 274 static void pbb_clk_mode(struct clk *clk, int enabled)
 275 {
 276         unsigned long flags;
 277         u32 mask;
 278
 279         spin_lock_irqsave(&pm_lock, flags);
 280         mask = pm_readl(PBB_MASK);
 281         if (enabled)
 282                 mask |= 1 << clk->index;
 283         else
 284                 mask &= ~(1 << clk->index);
 285         pm_writel(PBB_MASK, mask);
 286         spin_unlock_irqrestore(&pm_lock, flags);
 287 }
 288
 289 static unsigned long pbb_clk_get_rate(struct clk *clk)
 290 {
 291         unsigned long cksel, shift = 0;
 292
 293         cksel = pm_readl(CKSEL);
 294         if (cksel & PM_BIT(PBBDIV))
 295                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 296
 297         return bus_clk_get_rate(clk, shift);
 298 }
 299
 300 static struct clk cpu_clk = {
 301         .name           = "cpu",
 302         .get_rate       = cpu_clk_get_rate,
 303         .users          = 1,
 304 };
 305 static struct clk hsb_clk = {
 306         .name           = "hsb",
 307         .parent         = &cpu_clk,
 308         .get_rate       = hsb_clk_get_rate,
 309 };
 310 static struct clk pba_clk = {
 311         .name           = "pba",
 312         .parent         = &hsb_clk,
 313         .mode           = hsb_clk_mode,
 314         .get_rate       = pba_clk_get_rate,
 315         .index          = 1,
 316 };
 317 static struct clk pbb_clk = {
 318         .name           = "pbb",
 319         .parent         = &hsb_clk,
 320         .mode           = hsb_clk_mode,
 321         .get_rate       = pbb_clk_get_rate,
 322         .users          = 1,
 323         .index          = 2,
 324 };
 325
 326 /* --------------------------------------------------------------------
 327  *  Generic Clock operations
 328  * -------------------------------------------------------------------- */
 329
 330 static void genclk_mode(struct clk *clk, int enabled)
 331 {
 332         u32 control;
 333
 334         control = pm_readl(GCCTRL(clk->index));
 335         if (enabled)
 336                 control |= PM_BIT(CEN);
 337         else
 338                 control &= ~PM_BIT(CEN);
 339         pm_writel(GCCTRL(clk->index), control);
 340 }
 341
 342 static unsigned long genclk_get_rate(struct clk *clk)
 343 {
 344         u32 control;
 345         unsigned long div = 1;
 346
 347         control = pm_readl(GCCTRL(clk->index));
 348         if (control & PM_BIT(DIVEN))
 349                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 350
 351         return clk->parent->get_rate(clk->parent) / div;
 352 }
 353
 354 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 355 {
 356         u32 control;
 357         unsigned long parent_rate, actual_rate, div;
 358
 359         parent_rate = clk->parent->get_rate(clk->parent);
 360         control = pm_readl(GCCTRL(clk->index));
 361
 362         if (rate > 3 * parent_rate / 4) {
 363                 actual_rate = parent_rate;
 364                 control &= ~PM_BIT(DIVEN);
 365         } else {
 366                 div = (parent_rate + rate) / (2 * rate) - 1;
 367                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 368                 actual_rate = parent_rate / (2 * (div + 1));
 369         }
 370
 371         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 372                 clk->name, rate, actual_rate);
 373
 374         if (apply)
 375                 pm_writel(GCCTRL(clk->index), control);
 376
 377         return actual_rate;
 378 }
 379
 380 int genclk_set_parent(struct clk *clk, struct clk *parent)
 381 {
 382         u32 control;
 383
 384         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 385                 clk->name, parent->name, clk->parent->name);
 386
 387         control = pm_readl(GCCTRL(clk->index));
 388
 389         if (parent == &osc1 || parent == &pll1)
 390                 control |= PM_BIT(OSCSEL);
 391         else if (parent == &osc0 || parent == &pll0)
 392                 control &= ~PM_BIT(OSCSEL);
 393         else
 394                 return -EINVAL;
 395
 396         if (parent == &pll0 || parent == &pll1)
 397                 control |= PM_BIT(PLLSEL);
 398         else
 399                 control &= ~PM_BIT(PLLSEL);
 400
 401         pm_writel(GCCTRL(clk->index), control);
 402         clk->parent = parent;
 403
 404         return 0;
 405 }
 406
 407 static void __init genclk_init_parent(struct clk *clk)
 408 {
 409         u32 control;
 410         struct clk *parent;
 411
 412         BUG_ON(clk->index > 7);
 413
 414         control = pm_readl(GCCTRL(clk->index));
 415         if (control & PM_BIT(OSCSEL))
 416                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 417         else
 418                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 419
 420         clk->parent = parent;
 421 }
 422
 423 /* --------------------------------------------------------------------
 424  *  System peripherals
 425  * -------------------------------------------------------------------- */
 426 static struct resource at32_pm0_resource[] = {
 427         {
 428                 .start  = 0xfff00000,
 429                 .end    = 0xfff0007f,
 430                 .flags  = IORESOURCE_MEM,
 431         },
 432         IRQ(20),
 433 };
 434
 435 static struct resource at32ap700x_rtc0_resource[] = {
 436         {
 437                 .start  = 0xfff00080,
 438                 .end    = 0xfff000af,
 439                 .flags  = IORESOURCE_MEM,
 440         },
 441         IRQ(21),
 442 };
 443
 444 static struct resource at32_wdt0_resource[] = {
 445         {
 446                 .start  = 0xfff000b0,
 447                 .end    = 0xfff000bf,
 448                 .flags  = IORESOURCE_MEM,
 449         },
 450 };
 451
 452 static struct resource at32_eic0_resource[] = {
 453         {
 454                 .start  = 0xfff00100,
 455                 .end    = 0xfff0013f,
 456                 .flags  = IORESOURCE_MEM,
 457         },
 458         IRQ(19),
 459 };
 460
 461 DEFINE_DEV(at32_pm, 0);
 462 DEFINE_DEV(at32ap700x_rtc, 0);
 463 DEFINE_DEV(at32_wdt, 0);
 464 DEFINE_DEV(at32_eic, 0);
 465
 466 /*
 467  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 468  * is always running.
 469  */
 470 static struct clk at32_pm_pclk = {
 471         .name           = "pclk",
 472         .dev            = &at32_pm0_device.dev,
 473         .parent         = &pbb_clk,
 474         .mode           = pbb_clk_mode,
 475         .get_rate       = pbb_clk_get_rate,
 476         .users          = 1,
 477         .index          = 0,
 478 };
 479
 480 static struct resource intc0_resource[] = {
 481         PBMEM(0xfff00400),
 482 };
 483 struct platform_device at32_intc0_device = {
 484         .name           = "intc",
 485         .id             = 0,
 486         .resource       = intc0_resource,
 487         .num_resources  = ARRAY_SIZE(intc0_resource),
 488 };
 489 DEV_CLK(pclk, at32_intc0, pbb, 1);
 490
 491 static struct clk ebi_clk = {
 492         .name           = "ebi",
 493         .parent         = &hsb_clk,
 494         .mode           = hsb_clk_mode,
 495         .get_rate       = hsb_clk_get_rate,
 496         .users          = 1,
 497 };
 498 static struct clk hramc_clk = {
 499         .name           = "hramc",
 500         .parent         = &hsb_clk,
 501         .mode           = hsb_clk_mode,
 502         .get_rate       = hsb_clk_get_rate,
 503         .users          = 1,
 504         .index          = 3,
 505 };
 506
 507 static struct resource smc0_resource[] = {
 508         PBMEM(0xfff03400),
 509 };
 510 DEFINE_DEV(smc, 0);
 511 DEV_CLK(pclk, smc0, pbb, 13);
 512 DEV_CLK(mck, smc0, hsb, 0);
 513
 514 static struct platform_device pdc_device = {
 515         .name           = "pdc",
 516         .id             = 0,
 517 };
 518 DEV_CLK(hclk, pdc, hsb, 4);
 519 DEV_CLK(pclk, pdc, pba, 16);
 520
 521 static struct clk pico_clk = {
 522         .name           = "pico",
 523         .parent         = &cpu_clk,
 524         .mode           = cpu_clk_mode,
 525         .get_rate       = cpu_clk_get_rate,
 526         .users          = 1,
 527 };
 528
 529 /* --------------------------------------------------------------------
 530  * HMATRIX
 531  * -------------------------------------------------------------------- */
 532
 533 static struct clk hmatrix_clk = {
 534         .name           = "hmatrix_clk",
 535         .parent         = &pbb_clk,
 536         .mode           = pbb_clk_mode,
 537         .get_rate       = pbb_clk_get_rate,
 538         .index          = 2,
 539         .users          = 1,
 540 };
 541 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 542
 543 #define hmatrix_readl(reg)                                      \
 544         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 545 #define hmatrix_writel(reg,value)                               \
 546         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 547
 548 /*
 549  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 550  * External Bus Interface (EBI). This can be used to enable special
 551  * features like CompactFlash support, NAND Flash support, etc. on
 552  * certain chipselects.
 553  */
 554 static inline void set_ebi_sfr_bits(u32 mask)
 555 {
 556         u32 sfr;
 557
 558         clk_enable(&hmatrix_clk);
 559         sfr = hmatrix_readl(SFR4);
 560         sfr |= mask;
 561         hmatrix_writel(SFR4, sfr);
 562         clk_disable(&hmatrix_clk);
 563 }
 564
 565 /* --------------------------------------------------------------------
 566  *  System Timer/Counter (TC)
 567  * -------------------------------------------------------------------- */
 568 static struct resource at32_systc0_resource[] = {
 569         PBMEM(0xfff00c00),
 570         IRQ(22),
 571 };
 572 struct platform_device at32_systc0_device = {
 573         .name           = "systc",
 574         .id             = 0,
 575         .resource       = at32_systc0_resource,
 576         .num_resources  = ARRAY_SIZE(at32_systc0_resource),
 577 };
 578 DEV_CLK(pclk, at32_systc0, pbb, 3);
 579
 580 /* --------------------------------------------------------------------
 581  *  PIO
 582  * -------------------------------------------------------------------- */
 583
 584 static struct resource pio0_resource[] = {
 585         PBMEM(0xffe02800),
 586         IRQ(13),
 587 };
 588 DEFINE_DEV(pio, 0);
 589 DEV_CLK(mck, pio0, pba, 10);
 590
 591 static struct resource pio1_resource[] = {
 592         PBMEM(0xffe02c00),
 593         IRQ(14),
 594 };
 595 DEFINE_DEV(pio, 1);
 596 DEV_CLK(mck, pio1, pba, 11);
 597
 598 static struct resource pio2_resource[] = {
 599         PBMEM(0xffe03000),
 600         IRQ(15),
 601 };
 602 DEFINE_DEV(pio, 2);
 603 DEV_CLK(mck, pio2, pba, 12);
 604
 605 static struct resource pio3_resource[] = {
 606         PBMEM(0xffe03400),
 607         IRQ(16),
 608 };
 609 DEFINE_DEV(pio, 3);
 610 DEV_CLK(mck, pio3, pba, 13);
 611
 612 static struct resource pio4_resource[] = {
 613         PBMEM(0xffe03800),
 614         IRQ(17),
 615 };
 616 DEFINE_DEV(pio, 4);
 617 DEV_CLK(mck, pio4, pba, 14);
 618
 619 void __init at32_add_system_devices(void)
 620 {
 621         platform_device_register(&at32_pm0_device);
 622         platform_device_register(&at32_intc0_device);
 623         platform_device_register(&at32ap700x_rtc0_device);
 624         platform_device_register(&at32_wdt0_device);
 625         platform_device_register(&at32_eic0_device);
 626         platform_device_register(&smc0_device);
 627         platform_device_register(&pdc_device);
 628
 629         platform_device_register(&at32_systc0_device);
 630
 631         platform_device_register(&pio0_device);
 632         platform_device_register(&pio1_device);
 633         platform_device_register(&pio2_device);
 634         platform_device_register(&pio3_device);
 635         platform_device_register(&pio4_device);
 636 }
 637
 638 /* --------------------------------------------------------------------
 639  *  USART
 640  * -------------------------------------------------------------------- */
 641
 642 static struct atmel_uart_data atmel_usart0_data = {
 643         .use_dma_tx     = 1,
 644         .use_dma_rx     = 1,
 645 };
 646 static struct resource atmel_usart0_resource[] = {
 647         PBMEM(0xffe00c00),
 648         IRQ(6),
 649 };
 650 DEFINE_DEV_DATA(atmel_usart, 0);
 651 DEV_CLK(usart, atmel_usart0, pba, 4);
 652
 653 static struct atmel_uart_data atmel_usart1_data = {
 654         .use_dma_tx     = 1,
 655         .use_dma_rx     = 1,
 656 };
 657 static struct resource atmel_usart1_resource[] = {
 658         PBMEM(0xffe01000),
 659         IRQ(7),
 660 };
 661 DEFINE_DEV_DATA(atmel_usart, 1);
 662 DEV_CLK(usart, atmel_usart1, pba, 4);
 663
 664 static struct atmel_uart_data atmel_usart2_data = {
 665         .use_dma_tx     = 1,
 666         .use_dma_rx     = 1,
 667 };
 668 static struct resource atmel_usart2_resource[] = {
 669         PBMEM(0xffe01400),
 670         IRQ(8),
 671 };
 672 DEFINE_DEV_DATA(atmel_usart, 2);
 673 DEV_CLK(usart, atmel_usart2, pba, 5);
 674
 675 static struct atmel_uart_data atmel_usart3_data = {
 676         .use_dma_tx     = 1,
 677         .use_dma_rx     = 1,
 678 };
 679 static struct resource atmel_usart3_resource[] = {
 680         PBMEM(0xffe01800),
 681         IRQ(9),
 682 };
 683 DEFINE_DEV_DATA(atmel_usart, 3);
 684 DEV_CLK(usart, atmel_usart3, pba, 6);
 685
 686 static inline void configure_usart0_pins(void)
 687 {
 688         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 689         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 690 }
 691
 692 static inline void configure_usart1_pins(void)
 693 {
 694         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 695         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 696 }
 697
 698 static inline void configure_usart2_pins(void)
 699 {
 700         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 701         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 702 }
 703
 704 static inline void configure_usart3_pins(void)
 705 {
 706         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 707         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 708 }
 709
 710 static struct platform_device *__initdata at32_usarts[4];
 711
 712 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 713 {
 714         struct platform_device *pdev;
 715
 716         switch (hw_id) {
 717         case 0:
 718                 pdev = &atmel_usart0_device;
 719                 configure_usart0_pins();
 720                 break;
 721         case 1:
 722                 pdev = &atmel_usart1_device;
 723                 configure_usart1_pins();
 724                 break;
 725         case 2:
 726                 pdev = &atmel_usart2_device;
 727                 configure_usart2_pins();
 728                 break;
 729         case 3:
 730                 pdev = &atmel_usart3_device;
 731                 configure_usart3_pins();
 732                 break;
 733         default:
 734                 return;
 735         }
 736
 737         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 738                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 739                 struct atmel_uart_data *data = pdev->dev.platform_data;
 740                 data->regs = (void __iomem *)pdev->resource[0].start;
 741         }
 742
 743         pdev->id = line;
 744         at32_usarts[line] = pdev;
 745 }
 746
 747 struct platform_device *__init at32_add_device_usart(unsigned int id)
 748 {
 749         platform_device_register(at32_usarts[id]);
 750         return at32_usarts[id];
 751 }
 752
 753 struct platform_device *atmel_default_console_device;
 754
 755 void __init at32_setup_serial_console(unsigned int usart_id)
 756 {
 757         atmel_default_console_device = at32_usarts[usart_id];
 758 }
 759
 760 /* --------------------------------------------------------------------
 761  *  Ethernet
 762  * -------------------------------------------------------------------- */
 763
 764 static struct eth_platform_data macb0_data;
 765 static struct resource macb0_resource[] = {
 766         PBMEM(0xfff01800),
 767         IRQ(25),
 768 };
 769 DEFINE_DEV_DATA(macb, 0);
 770 DEV_CLK(hclk, macb0, hsb, 8);
 771 DEV_CLK(pclk, macb0, pbb, 6);
 772
 773 static struct eth_platform_data macb1_data;
 774 static struct resource macb1_resource[] = {
 775         PBMEM(0xfff01c00),
 776         IRQ(26),
 777 };
 778 DEFINE_DEV_DATA(macb, 1);
 779 DEV_CLK(hclk, macb1, hsb, 9);
 780 DEV_CLK(pclk, macb1, pbb, 7);
 781
 782 struct platform_device *__init
 783 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 784 {
 785         struct platform_device *pdev;
 786
 787         switch (id) {
 788         case 0:
 789                 pdev = &macb0_device;
 790
 791                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 792                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 793                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 794                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 795                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 796                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 797                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 798                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 799                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 800                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 801
 802                 if (!data->is_rmii) {
 803                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 804                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 805                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 806                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 807                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 808                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 809                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 810                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 811                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 812                 }
 813                 break;
 814
 815         case 1:
 816                 pdev = &macb1_device;
 817
 818                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 819                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 820                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 821                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 822                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 823                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 824                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 825                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 826                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 827                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 828
 829                 if (!data->is_rmii) {
 830                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 831                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 832                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 833                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 834                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 835                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 836                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 837                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 838                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 839                 }
 840                 break;
 841
 842         default:
 843                 return NULL;
 844         }
 845
 846         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 847         platform_device_register(pdev);
 848
 849         return pdev;
 850 }
 851
 852 /* --------------------------------------------------------------------
 853  *  SPI
 854  * -------------------------------------------------------------------- */
 855 static struct resource atmel_spi0_resource[] = {
 856         PBMEM(0xffe00000),
 857         IRQ(3),
 858 };
 859 DEFINE_DEV(atmel_spi, 0);
 860 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 861
 862 static struct resource atmel_spi1_resource[] = {
 863         PBMEM(0xffe00400),
 864         IRQ(4),
 865 };
 866 DEFINE_DEV(atmel_spi, 1);
 867 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 868
 869 static void __init
 870 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 871                       unsigned int n, const u8 *pins)
 872 {
 873         unsigned int pin, mode;
 874
 875         for (; n; n--, b++) {
 876                 b->bus_num = bus_num;
 877                 if (b->chip_select >= 4)
 878                         continue;
 879                 pin = (unsigned)b->controller_data;
 880                 if (!pin) {
 881                         pin = pins[b->chip_select];
 882                         b->controller_data = (void *)pin;
 883                 }
 884                 mode = AT32_GPIOF_OUTPUT;
 885                 if (!(b->mode & SPI_CS_HIGH))
 886                         mode |= AT32_GPIOF_HIGH;
 887                 at32_select_gpio(pin, mode);
 888         }
 889 }
 890
 891 struct platform_device *__init
 892 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 893 {
 894         /*
 895          * Manage the chipselects as GPIOs, normally using the same pins
 896          * the SPI controller expects; but boards can use other pins.
 897          */
 898         static u8 __initdata spi0_pins[] =
 899                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 900                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 901         static u8 __initdata spi1_pins[] =
 902                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 903                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 904         struct platform_device *pdev;
 905
 906         switch (id) {
 907         case 0:
 908                 pdev = &atmel_spi0_device;
 909                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 910                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 911                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 912                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 913                 break;
 914
 915         case 1:
 916                 pdev = &atmel_spi1_device;
 917                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 918                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 919                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 920                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 921                 break;
 922
 923         default:
 924                 return NULL;
 925         }
 926
 927         spi_register_board_info(b, n);
 928         platform_device_register(pdev);
 929         return pdev;
 930 }
 931
 932 /* --------------------------------------------------------------------
 933  *  LCDC
 934  * -------------------------------------------------------------------- */
 935 static struct atmel_lcdfb_info atmel_lcdfb0_data;
 936 static struct resource atmel_lcdfb0_resource[] = {
 937         {
 938                 .start          = 0xff000000,
 939                 .end            = 0xff000fff,
 940                 .flags          = IORESOURCE_MEM,
 941         },
 942         IRQ(1),
 943         {
 944                 /* Placeholder for pre-allocated fb memory */
 945                 .start          = 0x00000000,
 946                 .end            = 0x00000000,
 947                 .flags          = 0,
 948         },
 949 };
 950 DEFINE_DEV_DATA(atmel_lcdfb, 0);
 951 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
 952 static struct clk atmel_lcdfb0_pixclk = {
 953         .name           = "lcdc_clk",
 954         .dev            = &atmel_lcdfb0_device.dev,
 955         .mode           = genclk_mode,
 956         .get_rate       = genclk_get_rate,
 957         .set_rate       = genclk_set_rate,
 958         .set_parent     = genclk_set_parent,
 959         .index          = 7,
 960 };
 961
 962 struct platform_device *__init
 963 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
 964                      unsigned long fbmem_start, unsigned long fbmem_len)
 965 {
 966         struct platform_device *pdev;
 967         struct atmel_lcdfb_info *info;
 968         struct fb_monspecs *monspecs;
 969         struct fb_videomode *modedb;
 970         unsigned int modedb_size;
 971
 972         /*
 973          * Do a deep copy of the fb data, monspecs and modedb. Make
 974          * sure all allocations are done before setting up the
 975          * portmux.
 976          */
 977         monspecs = kmemdup(data->default_monspecs,
 978                            sizeof(struct fb_monspecs), GFP_KERNEL);
 979         if (!monspecs)
 980                 return NULL;
 981
 982         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
 983         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
 984         if (!modedb)
 985                 goto err_dup_modedb;
 986         monspecs->modedb = modedb;
 987
 988         switch (id) {
 989         case 0:
 990                 pdev = &atmel_lcdfb0_device;
 991                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
 992                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
 993                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
 994                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
 995                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
 996                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
 997                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
 998                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
 999                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1000                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1001                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1002                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1003                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1004                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1005                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1006                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1007                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1008                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1009                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1010                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1011                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1012                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1013                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1014                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1015                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1016                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1017                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1018                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1019                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1020                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1021                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1022
1023                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1024                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1025                 break;
1026
1027         default:
1028                 goto err_invalid_id;
1029         }
1030
1031         if (fbmem_len) {
1032                 pdev->resource[2].start = fbmem_start;
1033                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1034                 pdev->resource[2].flags = IORESOURCE_MEM;
1035         }
1036
1037         info = pdev->dev.platform_data;
1038         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1039         info->default_monspecs = monspecs;
1040
1041         platform_device_register(pdev);
1042         return pdev;
1043
1044 err_invalid_id:
1045         kfree(modedb);
1046 err_dup_modedb:
1047         kfree(monspecs);
1048         return NULL;
1049 }
1050
1051 /* --------------------------------------------------------------------
1052  *  GCLK
1053  * -------------------------------------------------------------------- */
1054 static struct clk gclk0 = {
1055         .name           = "gclk0",
1056         .mode           = genclk_mode,
1057         .get_rate       = genclk_get_rate,
1058         .set_rate       = genclk_set_rate,
1059         .set_parent     = genclk_set_parent,
1060         .index          = 0,
1061 };
1062 static struct clk gclk1 = {
1063         .name           = "gclk1",
1064         .mode           = genclk_mode,
1065         .get_rate       = genclk_get_rate,
1066         .set_rate       = genclk_set_rate,
1067         .set_parent     = genclk_set_parent,
1068         .index          = 1,
1069 };
1070 static struct clk gclk2 = {
1071         .name           = "gclk2",
1072         .mode           = genclk_mode,
1073         .get_rate       = genclk_get_rate,
1074         .set_rate       = genclk_set_rate,
1075         .set_parent     = genclk_set_parent,
1076         .index          = 2,
1077 };
1078 static struct clk gclk3 = {
1079         .name           = "gclk3",
1080         .mode           = genclk_mode,
1081         .get_rate       = genclk_get_rate,
1082         .set_rate       = genclk_set_rate,
1083         .set_parent     = genclk_set_parent,
1084         .index          = 3,
1085 };
1086 static struct clk gclk4 = {
1087         .name           = "gclk4",
1088         .mode           = genclk_mode,
1089         .get_rate       = genclk_get_rate,
1090         .set_rate       = genclk_set_rate,
1091         .set_parent     = genclk_set_parent,
1092         .index          = 4,
1093 };
1094
1095 struct clk *at32_clock_list[] = {
1096         &osc32k,
1097         &osc0,
1098         &osc1,
1099         &pll0,
1100         &pll1,
1101         &cpu_clk,
1102         &hsb_clk,
1103         &pba_clk,
1104         &pbb_clk,
1105         &at32_pm_pclk,
1106         &at32_intc0_pclk,
1107         &hmatrix_clk,
1108         &ebi_clk,
1109         &hramc_clk,
1110         &smc0_pclk,
1111         &smc0_mck,
1112         &pdc_hclk,
1113         &pdc_pclk,
1114         &pico_clk,
1115         &pio0_mck,
1116         &pio1_mck,
1117         &pio2_mck,
1118         &pio3_mck,
1119         &pio4_mck,
1120         &at32_systc0_pclk,
1121         &atmel_usart0_usart,
1122         &atmel_usart1_usart,
1123         &atmel_usart2_usart,
1124         &atmel_usart3_usart,
1125         &macb0_hclk,
1126         &macb0_pclk,
1127         &macb1_hclk,
1128         &macb1_pclk,
1129         &atmel_spi0_spi_clk,
1130         &atmel_spi1_spi_clk,
1131         &atmel_lcdfb0_hck1,
1132         &atmel_lcdfb0_pixclk,
1133         &gclk0,
1134         &gclk1,
1135         &gclk2,
1136         &gclk3,
1137         &gclk4,
1138 };
1139 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1140
1141 void __init at32_portmux_init(void)
1142 {
1143         at32_init_pio(&pio0_device);
1144         at32_init_pio(&pio1_device);
1145         at32_init_pio(&pio2_device);
1146         at32_init_pio(&pio3_device);
1147         at32_init_pio(&pio4_device);
1148 }
1149
1150 void __init at32_clock_init(void)
1151 {
1152         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1153         int i;
1154
1155         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL))
1156                 main_clock = &pll0;
1157         else
1158                 main_clock = &osc0;
1159
1160         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1161                 pll0.parent = &osc1;
1162         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1163                 pll1.parent = &osc1;
1164
1165         genclk_init_parent(&gclk0);
1166         genclk_init_parent(&gclk1);
1167         genclk_init_parent(&gclk2);
1168         genclk_init_parent(&gclk3);
1169         genclk_init_parent(&gclk4);
1170         genclk_init_parent(&atmel_lcdfb0_pixclk);
1171
1172         /*
1173          * Turn on all clocks that have at least one user already, and
1174          * turn off everything else. We only do this for module
1175          * clocks, and even though it isn't particularly pretty to
1176          * check the address of the mode function, it should do the
1177          * trick...
1178          */
1179         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1180                 struct clk *clk = at32_clock_list[i];
1181
1182                 if (clk->users == 0)
1183                         continue;
1184
1185                 if (clk->mode == &cpu_clk_mode)
1186                         cpu_mask |= 1 << clk->index;
1187                 else if (clk->mode == &hsb_clk_mode)
1188                         hsb_mask |= 1 << clk->index;
1189                 else if (clk->mode == &pba_clk_mode)
1190                         pba_mask |= 1 << clk->index;
1191                 else if (clk->mode == &pbb_clk_mode)
1192                         pbb_mask |= 1 << clk->index;
1193         }
1194
1195         pm_writel(CPU_MASK, cpu_mask);
1196         pm_writel(HSB_MASK, hsb_mask);
1197         pm_writel(PBA_MASK, pba_mask);
1198         pm_writel(PBB_MASK, pbb_mask);
1199 }