arch/avr32/mach-at32ap/at32ap7000.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/init.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/spi/spi.h>
  12
  13 #include <asm/io.h>
  14
  15 #include <asm/arch/at32ap7000.h>
  16 #include <asm/arch/board.h>
  17 #include <asm/arch/portmux.h>
  18 #include <asm/arch/sm.h>
  19
  20 #include "clock.h"
  21 #include "hmatrix.h"
  22 #include "pio.h"
  23 #include "sm.h"
  24
  25 #define PBMEM(base)                                     \
  26         {                                               \
  27                 .start          = base,                 \
  28                 .end            = base + 0x3ff,         \
  29                 .flags          = IORESOURCE_MEM,       \
  30         }
  31 #define IRQ(num)                                        \
  32         {                                               \
  33                 .start          = num,                  \
  34                 .end            = num,                  \
  35                 .flags          = IORESOURCE_IRQ,       \
  36         }
  37 #define NAMED_IRQ(num, _name)                           \
  38         {                                               \
  39                 .start          = num,                  \
  40                 .end            = num,                  \
  41                 .name           = _name,                \
  42                 .flags          = IORESOURCE_IRQ,       \
  43         }
  44
  45 #define DEFINE_DEV(_name, _id)                                  \
  46 static struct platform_device _name##_id##_device = {           \
  47         .name           = #_name,                               \
  48         .id             = _id,                                  \
  49         .resource       = _name##_id##_resource,                \
  50         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  51 }
  52 #define DEFINE_DEV_DATA(_name, _id)                             \
  53 static struct platform_device _name##_id##_device = {           \
  54         .name           = #_name,                               \
  55         .id             = _id,                                  \
  56         .dev            = {                                     \
  57                 .platform_data  = &_name##_id##_data,           \
  58         },                                                      \
  59         .resource       = _name##_id##_resource,                \
  60         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  61 }
  62
  63 #define select_peripheral(pin, periph, flags)                   \
  64         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  65
  66 #define DEV_CLK(_name, devname, bus, _index)                    \
  67 static struct clk devname##_##_name = {                         \
  68         .name           = #_name,                               \
  69         .dev            = &devname##_device.dev,                \
  70         .parent         = &bus##_clk,                           \
  71         .mode           = bus##_clk_mode,                       \
  72         .get_rate       = bus##_clk_get_rate,                   \
  73         .index          = _index,                               \
  74 }
  75
  76 unsigned long at32ap7000_osc_rates[3] = {
  77         [0] = 32768,
  78         /* FIXME: these are ATSTK1002-specific */
  79         [1] = 20000000,
  80         [2] = 12000000,
  81 };
  82
  83 static unsigned long osc_get_rate(struct clk *clk)
  84 {
  85         return at32ap7000_osc_rates[clk->index];
  86 }
  87
  88 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
  89 {
  90         unsigned long div, mul, rate;
  91
  92         if (!(control & SM_BIT(PLLEN)))
  93                 return 0;
  94
  95         div = SM_BFEXT(PLLDIV, control) + 1;
  96         mul = SM_BFEXT(PLLMUL, control) + 1;
  97
  98         rate = clk->parent->get_rate(clk->parent);
  99         rate = (rate + div / 2) / div;
 100         rate *= mul;
 101
 102         return rate;
 103 }
 104
 105 static unsigned long pll0_get_rate(struct clk *clk)
 106 {
 107         u32 control;
 108
 109         control = sm_readl(&system_manager, PM_PLL0);
 110
 111         return pll_get_rate(clk, control);
 112 }
 113
 114 static unsigned long pll1_get_rate(struct clk *clk)
 115 {
 116         u32 control;
 117
 118         control = sm_readl(&system_manager, PM_PLL1);
 119
 120         return pll_get_rate(clk, control);
 121 }
 122
 123 /*
 124  * The AT32AP7000 has five primary clock sources: One 32kHz
 125  * oscillator, two crystal oscillators and two PLLs.
 126  */
 127 static struct clk osc32k = {
 128         .name           = "osc32k",
 129         .get_rate       = osc_get_rate,
 130         .users          = 1,
 131         .index          = 0,
 132 };
 133 static struct clk osc0 = {
 134         .name           = "osc0",
 135         .get_rate       = osc_get_rate,
 136         .users          = 1,
 137         .index          = 1,
 138 };
 139 static struct clk osc1 = {
 140         .name           = "osc1",
 141         .get_rate       = osc_get_rate,
 142         .index          = 2,
 143 };
 144 static struct clk pll0 = {
 145         .name           = "pll0",
 146         .get_rate       = pll0_get_rate,
 147         .parent         = &osc0,
 148 };
 149 static struct clk pll1 = {
 150         .name           = "pll1",
 151         .get_rate       = pll1_get_rate,
 152         .parent         = &osc0,
 153 };
 154
 155 /*
 156  * The main clock can be either osc0 or pll0.  The boot loader may
 157  * have chosen one for us, so we don't really know which one until we
 158  * have a look at the SM.
 159  */
 160 static struct clk *main_clock;
 161
 162 /*
 163  * Synchronous clocks are generated from the main clock. The clocks
 164  * must satisfy the constraint
 165  *   fCPU >= fHSB >= fPB
 166  * i.e. each clock must not be faster than its parent.
 167  */
 168 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 169 {
 170         return main_clock->get_rate(main_clock) >> shift;
 171 };
 172
 173 static void cpu_clk_mode(struct clk *clk, int enabled)
 174 {
 175         struct at32_sm *sm = &system_manager;
 176         unsigned long flags;
 177         u32 mask;
 178
 179         spin_lock_irqsave(&sm->lock, flags);
 180         mask = sm_readl(sm, PM_CPU_MASK);
 181         if (enabled)
 182                 mask |= 1 << clk->index;
 183         else
 184                 mask &= ~(1 << clk->index);
 185         sm_writel(sm, PM_CPU_MASK, mask);
 186         spin_unlock_irqrestore(&sm->lock, flags);
 187 }
 188
 189 static unsigned long cpu_clk_get_rate(struct clk *clk)
 190 {
 191         unsigned long cksel, shift = 0;
 192
 193         cksel = sm_readl(&system_manager, PM_CKSEL);
 194         if (cksel & SM_BIT(CPUDIV))
 195                 shift = SM_BFEXT(CPUSEL, cksel) + 1;
 196
 197         return bus_clk_get_rate(clk, shift);
 198 }
 199
 200 static void hsb_clk_mode(struct clk *clk, int enabled)
 201 {
 202         struct at32_sm *sm = &system_manager;
 203         unsigned long flags;
 204         u32 mask;
 205
 206         spin_lock_irqsave(&sm->lock, flags);
 207         mask = sm_readl(sm, PM_HSB_MASK);
 208         if (enabled)
 209                 mask |= 1 << clk->index;
 210         else
 211                 mask &= ~(1 << clk->index);
 212         sm_writel(sm, PM_HSB_MASK, mask);
 213         spin_unlock_irqrestore(&sm->lock, flags);
 214 }
 215
 216 static unsigned long hsb_clk_get_rate(struct clk *clk)
 217 {
 218         unsigned long cksel, shift = 0;
 219
 220         cksel = sm_readl(&system_manager, PM_CKSEL);
 221         if (cksel & SM_BIT(HSBDIV))
 222                 shift = SM_BFEXT(HSBSEL, cksel) + 1;
 223
 224         return bus_clk_get_rate(clk, shift);
 225 }
 226
 227 static void pba_clk_mode(struct clk *clk, int enabled)
 228 {
 229         struct at32_sm *sm = &system_manager;
 230         unsigned long flags;
 231         u32 mask;
 232
 233         spin_lock_irqsave(&sm->lock, flags);
 234         mask = sm_readl(sm, PM_PBA_MASK);
 235         if (enabled)
 236                 mask |= 1 << clk->index;
 237         else
 238                 mask &= ~(1 << clk->index);
 239         sm_writel(sm, PM_PBA_MASK, mask);
 240         spin_unlock_irqrestore(&sm->lock, flags);
 241 }
 242
 243 static unsigned long pba_clk_get_rate(struct clk *clk)
 244 {
 245         unsigned long cksel, shift = 0;
 246
 247         cksel = sm_readl(&system_manager, PM_CKSEL);
 248         if (cksel & SM_BIT(PBADIV))
 249                 shift = SM_BFEXT(PBASEL, cksel) + 1;
 250
 251         return bus_clk_get_rate(clk, shift);
 252 }
 253
 254 static void pbb_clk_mode(struct clk *clk, int enabled)
 255 {
 256         struct at32_sm *sm = &system_manager;
 257         unsigned long flags;
 258         u32 mask;
 259
 260         spin_lock_irqsave(&sm->lock, flags);
 261         mask = sm_readl(sm, PM_PBB_MASK);
 262         if (enabled)
 263                 mask |= 1 << clk->index;
 264         else
 265                 mask &= ~(1 << clk->index);
 266         sm_writel(sm, PM_PBB_MASK, mask);
 267         spin_unlock_irqrestore(&sm->lock, flags);
 268 }
 269
 270 static unsigned long pbb_clk_get_rate(struct clk *clk)
 271 {
 272         unsigned long cksel, shift = 0;
 273
 274         cksel = sm_readl(&system_manager, PM_CKSEL);
 275         if (cksel & SM_BIT(PBBDIV))
 276                 shift = SM_BFEXT(PBBSEL, cksel) + 1;
 277
 278         return bus_clk_get_rate(clk, shift);
 279 }
 280
 281 static struct clk cpu_clk = {
 282         .name           = "cpu",
 283         .get_rate       = cpu_clk_get_rate,
 284         .users          = 1,
 285 };
 286 static struct clk hsb_clk = {
 287         .name           = "hsb",
 288         .parent         = &cpu_clk,
 289         .get_rate       = hsb_clk_get_rate,
 290 };
 291 static struct clk pba_clk = {
 292         .name           = "pba",
 293         .parent         = &hsb_clk,
 294         .mode           = hsb_clk_mode,
 295         .get_rate       = pba_clk_get_rate,
 296         .index          = 1,
 297 };
 298 static struct clk pbb_clk = {
 299         .name           = "pbb",
 300         .parent         = &hsb_clk,
 301         .mode           = hsb_clk_mode,
 302         .get_rate       = pbb_clk_get_rate,
 303         .users          = 1,
 304         .index          = 2,
 305 };
 306
 307 /* --------------------------------------------------------------------
 308  *  Generic Clock operations
 309  * -------------------------------------------------------------------- */
 310
 311 static void genclk_mode(struct clk *clk, int enabled)
 312 {
 313         u32 control;
 314
 315         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 316         if (enabled)
 317                 control |= SM_BIT(CEN);
 318         else
 319                 control &= ~SM_BIT(CEN);
 320         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
 321 }
 322
 323 static unsigned long genclk_get_rate(struct clk *clk)
 324 {
 325         u32 control;
 326         unsigned long div = 1;
 327
 328         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 329         if (control & SM_BIT(DIVEN))
 330                 div = 2 * (SM_BFEXT(DIV, control) + 1);
 331
 332         return clk->parent->get_rate(clk->parent) / div;
 333 }
 334
 335 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 336 {
 337         u32 control;
 338         unsigned long parent_rate, actual_rate, div;
 339
 340         parent_rate = clk->parent->get_rate(clk->parent);
 341         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 342
 343         if (rate > 3 * parent_rate / 4) {
 344                 actual_rate = parent_rate;
 345                 control &= ~SM_BIT(DIVEN);
 346         } else {
 347                 div = (parent_rate + rate) / (2 * rate) - 1;
 348                 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
 349                 actual_rate = parent_rate / (2 * (div + 1));
 350         }
 351
 352         printk("clk %s: new rate %lu (actual rate %lu)\n",
 353                clk->name, rate, actual_rate);
 354
 355         if (apply)
 356                 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
 357                           control);
 358
 359         return actual_rate;
 360 }
 361
 362 int genclk_set_parent(struct clk *clk, struct clk *parent)
 363 {
 364         u32 control;
 365
 366         printk("clk %s: new parent %s (was %s)\n",
 367                clk->name, parent->name, clk->parent->name);
 368
 369         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 370
 371         if (parent == &osc1 || parent == &pll1)
 372                 control |= SM_BIT(OSCSEL);
 373         else if (parent == &osc0 || parent == &pll0)
 374                 control &= ~SM_BIT(OSCSEL);
 375         else
 376                 return -EINVAL;
 377
 378         if (parent == &pll0 || parent == &pll1)
 379                 control |= SM_BIT(PLLSEL);
 380         else
 381                 control &= ~SM_BIT(PLLSEL);
 382
 383         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
 384         clk->parent = parent;
 385
 386         return 0;
 387 }
 388
 389 static void __init genclk_init_parent(struct clk *clk)
 390 {
 391         u32 control;
 392         struct clk *parent;
 393
 394         BUG_ON(clk->index > 7);
 395
 396         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 397         if (control & SM_BIT(OSCSEL))
 398                 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
 399         else
 400                 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
 401
 402         clk->parent = parent;
 403 }
 404
 405 /* --------------------------------------------------------------------
 406  *  System peripherals
 407  * -------------------------------------------------------------------- */
 408 static struct resource sm_resource[] = {
 409         PBMEM(0xfff00000),
 410         NAMED_IRQ(19, "eim"),
 411         NAMED_IRQ(20, "pm"),
 412         NAMED_IRQ(21, "rtc"),
 413 };
 414 struct platform_device at32_sm_device = {
 415         .name           = "sm",
 416         .id             = 0,
 417         .resource       = sm_resource,
 418         .num_resources  = ARRAY_SIZE(sm_resource),
 419 };
 420 DEV_CLK(pclk, at32_sm, pbb, 0);
 421
 422 static struct resource intc0_resource[] = {
 423         PBMEM(0xfff00400),
 424 };
 425 struct platform_device at32_intc0_device = {
 426         .name           = "intc",
 427         .id             = 0,
 428         .resource       = intc0_resource,
 429         .num_resources  = ARRAY_SIZE(intc0_resource),
 430 };
 431 DEV_CLK(pclk, at32_intc0, pbb, 1);
 432
 433 static struct clk ebi_clk = {
 434         .name           = "ebi",
 435         .parent         = &hsb_clk,
 436         .mode           = hsb_clk_mode,
 437         .get_rate       = hsb_clk_get_rate,
 438         .users          = 1,
 439 };
 440 static struct clk hramc_clk = {
 441         .name           = "hramc",
 442         .parent         = &hsb_clk,
 443         .mode           = hsb_clk_mode,
 444         .get_rate       = hsb_clk_get_rate,
 445         .users          = 1,
 446 };
 447
 448 static struct resource smc0_resource[] = {
 449         PBMEM(0xfff03400),
 450 };
 451 DEFINE_DEV(smc, 0);
 452 DEV_CLK(pclk, smc0, pbb, 13);
 453 DEV_CLK(mck, smc0, hsb, 0);
 454
 455 static struct platform_device pdc_device = {
 456         .name           = "pdc",
 457         .id             = 0,
 458 };
 459 DEV_CLK(hclk, pdc, hsb, 4);
 460 DEV_CLK(pclk, pdc, pba, 16);
 461
 462 static struct clk pico_clk = {
 463         .name           = "pico",
 464         .parent         = &cpu_clk,
 465         .mode           = cpu_clk_mode,
 466         .get_rate       = cpu_clk_get_rate,
 467         .users          = 1,
 468 };
 469
 470 /* --------------------------------------------------------------------
 471  * HMATRIX
 472  * -------------------------------------------------------------------- */
 473
 474 static struct clk hmatrix_clk = {
 475         .name           = "hmatrix_clk",
 476         .parent         = &pbb_clk,
 477         .mode           = pbb_clk_mode,
 478         .get_rate       = pbb_clk_get_rate,
 479         .index          = 2,
 480         .users          = 1,
 481 };
 482 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 483
 484 #define hmatrix_readl(reg)                                      \
 485         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 486 #define hmatrix_writel(reg,value)                               \
 487         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 488
 489 /*
 490  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 491  * External Bus Interface (EBI). This can be used to enable special
 492  * features like CompactFlash support, NAND Flash support, etc. on
 493  * certain chipselects.
 494  */
 495 static inline void set_ebi_sfr_bits(u32 mask)
 496 {
 497         u32 sfr;
 498
 499         clk_enable(&hmatrix_clk);
 500         sfr = hmatrix_readl(SFR4);
 501         sfr |= mask;
 502         hmatrix_writel(SFR4, sfr);
 503         clk_disable(&hmatrix_clk);
 504 }
 505
 506 /* --------------------------------------------------------------------
 507  *  PIO
 508  * -------------------------------------------------------------------- */
 509
 510 static struct resource pio0_resource[] = {
 511         PBMEM(0xffe02800),
 512         IRQ(13),
 513 };
 514 DEFINE_DEV(pio, 0);
 515 DEV_CLK(mck, pio0, pba, 10);
 516
 517 static struct resource pio1_resource[] = {
 518         PBMEM(0xffe02c00),
 519         IRQ(14),
 520 };
 521 DEFINE_DEV(pio, 1);
 522 DEV_CLK(mck, pio1, pba, 11);
 523
 524 static struct resource pio2_resource[] = {
 525         PBMEM(0xffe03000),
 526         IRQ(15),
 527 };
 528 DEFINE_DEV(pio, 2);
 529 DEV_CLK(mck, pio2, pba, 12);
 530
 531 static struct resource pio3_resource[] = {
 532         PBMEM(0xffe03400),
 533         IRQ(16),
 534 };
 535 DEFINE_DEV(pio, 3);
 536 DEV_CLK(mck, pio3, pba, 13);
 537
 538 static struct resource pio4_resource[] = {
 539         PBMEM(0xffe03800),
 540         IRQ(17),
 541 };
 542 DEFINE_DEV(pio, 4);
 543 DEV_CLK(mck, pio4, pba, 14);
 544
 545 void __init at32_add_system_devices(void)
 546 {
 547         system_manager.eim_first_irq = EIM_IRQ_BASE;
 548
 549         platform_device_register(&at32_sm_device);
 550         platform_device_register(&at32_intc0_device);
 551         platform_device_register(&smc0_device);
 552         platform_device_register(&pdc_device);
 553
 554         platform_device_register(&pio0_device);
 555         platform_device_register(&pio1_device);
 556         platform_device_register(&pio2_device);
 557         platform_device_register(&pio3_device);
 558         platform_device_register(&pio4_device);
 559 }
 560
 561 /* --------------------------------------------------------------------
 562  *  USART
 563  * -------------------------------------------------------------------- */
 564
 565 static struct atmel_uart_data atmel_usart0_data = {
 566         .use_dma_tx     = 1,
 567         .use_dma_rx     = 1,
 568 };
 569 static struct resource atmel_usart0_resource[] = {
 570         PBMEM(0xffe00c00),
 571         IRQ(6),
 572 };
 573 DEFINE_DEV_DATA(atmel_usart, 0);
 574 DEV_CLK(usart, atmel_usart0, pba, 4);
 575
 576 static struct atmel_uart_data atmel_usart1_data = {
 577         .use_dma_tx     = 1,
 578         .use_dma_rx     = 1,
 579 };
 580 static struct resource atmel_usart1_resource[] = {
 581         PBMEM(0xffe01000),
 582         IRQ(7),
 583 };
 584 DEFINE_DEV_DATA(atmel_usart, 1);
 585 DEV_CLK(usart, atmel_usart1, pba, 4);
 586
 587 static struct atmel_uart_data atmel_usart2_data = {
 588         .use_dma_tx     = 1,
 589         .use_dma_rx     = 1,
 590 };
 591 static struct resource atmel_usart2_resource[] = {
 592         PBMEM(0xffe01400),
 593         IRQ(8),
 594 };
 595 DEFINE_DEV_DATA(atmel_usart, 2);
 596 DEV_CLK(usart, atmel_usart2, pba, 5);
 597
 598 static struct atmel_uart_data atmel_usart3_data = {
 599         .use_dma_tx     = 1,
 600         .use_dma_rx     = 1,
 601 };
 602 static struct resource atmel_usart3_resource[] = {
 603         PBMEM(0xffe01800),
 604         IRQ(9),
 605 };
 606 DEFINE_DEV_DATA(atmel_usart, 3);
 607 DEV_CLK(usart, atmel_usart3, pba, 6);
 608
 609 static inline void configure_usart0_pins(void)
 610 {
 611         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 612         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 613 }
 614
 615 static inline void configure_usart1_pins(void)
 616 {
 617         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 618         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 619 }
 620
 621 static inline void configure_usart2_pins(void)
 622 {
 623         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 624         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 625 }
 626
 627 static inline void configure_usart3_pins(void)
 628 {
 629         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 630         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 631 }
 632
 633 static struct platform_device *__initdata at32_usarts[4];
 634
 635 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 636 {
 637         struct platform_device *pdev;
 638
 639         switch (hw_id) {
 640         case 0:
 641                 pdev = &atmel_usart0_device;
 642                 configure_usart0_pins();
 643                 break;
 644         case 1:
 645                 pdev = &atmel_usart1_device;
 646                 configure_usart1_pins();
 647                 break;
 648         case 2:
 649                 pdev = &atmel_usart2_device;
 650                 configure_usart2_pins();
 651                 break;
 652         case 3:
 653                 pdev = &atmel_usart3_device;
 654                 configure_usart3_pins();
 655                 break;
 656         default:
 657                 return;
 658         }
 659
 660         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 661                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 662                 struct atmel_uart_data *data = pdev->dev.platform_data;
 663                 data->regs = (void __iomem *)pdev->resource[0].start;
 664         }
 665
 666         pdev->id = line;
 667         at32_usarts[line] = pdev;
 668 }
 669
 670 struct platform_device *__init at32_add_device_usart(unsigned int id)
 671 {
 672         platform_device_register(at32_usarts[id]);
 673         return at32_usarts[id];
 674 }
 675
 676 struct platform_device *atmel_default_console_device;
 677
 678 void __init at32_setup_serial_console(unsigned int usart_id)
 679 {
 680         atmel_default_console_device = at32_usarts[usart_id];
 681 }
 682
 683 /* --------------------------------------------------------------------
 684  *  Ethernet
 685  * -------------------------------------------------------------------- */
 686
 687 static struct eth_platform_data macb0_data;
 688 static struct resource macb0_resource[] = {
 689         PBMEM(0xfff01800),
 690         IRQ(25),
 691 };
 692 DEFINE_DEV_DATA(macb, 0);
 693 DEV_CLK(hclk, macb0, hsb, 8);
 694 DEV_CLK(pclk, macb0, pbb, 6);
 695
 696 static struct eth_platform_data macb1_data;
 697 static struct resource macb1_resource[] = {
 698         PBMEM(0xfff01c00),
 699         IRQ(26),
 700 };
 701 DEFINE_DEV_DATA(macb, 1);
 702 DEV_CLK(hclk, macb1, hsb, 9);
 703 DEV_CLK(pclk, macb1, pbb, 7);
 704
 705 struct platform_device *__init
 706 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 707 {
 708         struct platform_device *pdev;
 709
 710         switch (id) {
 711         case 0:
 712                 pdev = &macb0_device;
 713
 714                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 715                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 716                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 717                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 718                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 719                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 720                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 721                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 722                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 723                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 724
 725                 if (!data->is_rmii) {
 726                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 727                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 728                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 729                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 730                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 731                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 732                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 733                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 734                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 735                 }
 736                 break;
 737
 738         case 1:
 739                 pdev = &macb1_device;
 740
 741                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 742                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 743                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 744                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 745                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 746                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 747                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 748                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 749                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 750                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 751
 752                 if (!data->is_rmii) {
 753                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 754                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 755                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 756                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 757                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 758                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 759                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 760                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 761                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 762                 }
 763                 break;
 764
 765         default:
 766                 return NULL;
 767         }
 768
 769         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 770         platform_device_register(pdev);
 771
 772         return pdev;
 773 }
 774
 775 /* --------------------------------------------------------------------
 776  *  SPI
 777  * -------------------------------------------------------------------- */
 778 static struct resource atmel_spi0_resource[] = {
 779         PBMEM(0xffe00000),
 780         IRQ(3),
 781 };
 782 DEFINE_DEV(atmel_spi, 0);
 783 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 784
 785 static struct resource atmel_spi1_resource[] = {
 786         PBMEM(0xffe00400),
 787         IRQ(4),
 788 };
 789 DEFINE_DEV(atmel_spi, 1);
 790 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 791
 792 static void __init
 793 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 794                       unsigned int n, const u8 *pins)
 795 {
 796         unsigned int pin, mode;
 797
 798         for (; n; n--, b++) {
 799                 b->bus_num = bus_num;
 800                 if (b->chip_select >= 4)
 801                         continue;
 802                 pin = (unsigned)b->controller_data;
 803                 if (!pin) {
 804                         pin = pins[b->chip_select];
 805                         b->controller_data = (void *)pin;
 806                 }
 807                 mode = AT32_GPIOF_OUTPUT;
 808                 if (!(b->mode & SPI_CS_HIGH))
 809                         mode |= AT32_GPIOF_HIGH;
 810                 at32_select_gpio(pin, mode);
 811         }
 812 }
 813
 814 struct platform_device *__init
 815 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 816 {
 817         /*
 818          * Manage the chipselects as GPIOs, normally using the same pins
 819          * the SPI controller expects; but boards can use other pins.
 820          */
 821         static u8 __initdata spi0_pins[] =
 822                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 823                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 824         static u8 __initdata spi1_pins[] =
 825                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 826                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 827         struct platform_device *pdev;
 828
 829         switch (id) {
 830         case 0:
 831                 pdev = &atmel_spi0_device;
 832                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 833                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 834                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 835                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 836                 break;
 837
 838         case 1:
 839                 pdev = &atmel_spi1_device;
 840                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 841                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 842                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 843                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 844                 break;
 845
 846         default:
 847                 return NULL;
 848         }
 849
 850         spi_register_board_info(b, n);
 851         platform_device_register(pdev);
 852         return pdev;
 853 }
 854
 855 /* --------------------------------------------------------------------
 856  *  LCDC
 857  * -------------------------------------------------------------------- */
 858 static struct lcdc_platform_data lcdc0_data;
 859 static struct resource lcdc0_resource[] = {
 860         {
 861                 .start          = 0xff000000,
 862                 .end            = 0xff000fff,
 863                 .flags          = IORESOURCE_MEM,
 864         },
 865         IRQ(1),
 866 };
 867 DEFINE_DEV_DATA(lcdc, 0);
 868 DEV_CLK(hclk, lcdc0, hsb, 7);
 869 static struct clk lcdc0_pixclk = {
 870         .name           = "pixclk",
 871         .dev            = &lcdc0_device.dev,
 872         .mode           = genclk_mode,
 873         .get_rate       = genclk_get_rate,
 874         .set_rate       = genclk_set_rate,
 875         .set_parent     = genclk_set_parent,
 876         .index          = 7,
 877 };
 878
 879 struct platform_device *__init
 880 at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
 881 {
 882         struct platform_device *pdev;
 883
 884         switch (id) {
 885         case 0:
 886                 pdev = &lcdc0_device;
 887                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
 888                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
 889                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
 890                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
 891                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
 892                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
 893                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
 894                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
 895                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
 896                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
 897                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
 898                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
 899                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
 900                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
 901                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
 902                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
 903                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
 904                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
 905                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
 906                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
 907                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
 908                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
 909                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
 910                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
 911                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
 912                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
 913                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
 914                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
 915                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
 916                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
 917                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
 918
 919                 clk_set_parent(&lcdc0_pixclk, &pll0);
 920                 clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
 921                 break;
 922
 923         default:
 924                 return NULL;
 925         }
 926
 927         memcpy(pdev->dev.platform_data, data,
 928                sizeof(struct lcdc_platform_data));
 929
 930         platform_device_register(pdev);
 931         return pdev;
 932 }
 933
 934 /* --------------------------------------------------------------------
 935  *  GCLK
 936  * -------------------------------------------------------------------- */
 937 static struct clk gclk0 = {
 938         .name           = "gclk0",
 939         .mode           = genclk_mode,
 940         .get_rate       = genclk_get_rate,
 941         .set_rate       = genclk_set_rate,
 942         .set_parent     = genclk_set_parent,
 943         .index          = 0,
 944 };
 945 static struct clk gclk1 = {
 946         .name           = "gclk1",
 947         .mode           = genclk_mode,
 948         .get_rate       = genclk_get_rate,
 949         .set_rate       = genclk_set_rate,
 950         .set_parent     = genclk_set_parent,
 951         .index          = 1,
 952 };
 953 static struct clk gclk2 = {
 954         .name           = "gclk2",
 955         .mode           = genclk_mode,
 956         .get_rate       = genclk_get_rate,
 957         .set_rate       = genclk_set_rate,
 958         .set_parent     = genclk_set_parent,
 959         .index          = 2,
 960 };
 961 static struct clk gclk3 = {
 962         .name           = "gclk3",
 963         .mode           = genclk_mode,
 964         .get_rate       = genclk_get_rate,
 965         .set_rate       = genclk_set_rate,
 966         .set_parent     = genclk_set_parent,
 967         .index          = 3,
 968 };
 969 static struct clk gclk4 = {
 970         .name           = "gclk4",
 971         .mode           = genclk_mode,
 972         .get_rate       = genclk_get_rate,
 973         .set_rate       = genclk_set_rate,
 974         .set_parent     = genclk_set_parent,
 975         .index          = 4,
 976 };
 977
 978 struct clk *at32_clock_list[] = {
 979         &osc32k,
 980         &osc0,
 981         &osc1,
 982         &pll0,
 983         &pll1,
 984         &cpu_clk,
 985         &hsb_clk,
 986         &pba_clk,
 987         &pbb_clk,
 988         &at32_sm_pclk,
 989         &at32_intc0_pclk,
 990         &hmatrix_clk,
 991         &ebi_clk,
 992         &hramc_clk,
 993         &smc0_pclk,
 994         &smc0_mck,
 995         &pdc_hclk,
 996         &pdc_pclk,
 997         &pico_clk,
 998         &pio0_mck,
 999         &pio1_mck,
1000         &pio2_mck,
1001         &pio3_mck,
1002         &pio4_mck,
1003         &atmel_usart0_usart,
1004         &atmel_usart1_usart,
1005         &atmel_usart2_usart,
1006         &atmel_usart3_usart,
1007         &macb0_hclk,
1008         &macb0_pclk,
1009         &macb1_hclk,
1010         &macb1_pclk,
1011         &atmel_spi0_spi_clk,
1012         &atmel_spi1_spi_clk,
1013         &lcdc0_hclk,
1014         &lcdc0_pixclk,
1015         &gclk0,
1016         &gclk1,
1017         &gclk2,
1018         &gclk3,
1019         &gclk4,
1020 };
1021 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1022
1023 void __init at32_portmux_init(void)
1024 {
1025         at32_init_pio(&pio0_device);
1026         at32_init_pio(&pio1_device);
1027         at32_init_pio(&pio2_device);
1028         at32_init_pio(&pio3_device);
1029         at32_init_pio(&pio4_device);
1030 }
1031
1032 void __init at32_clock_init(void)
1033 {
1034         struct at32_sm *sm = &system_manager;
1035         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1036         int i;
1037
1038         if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1039                 main_clock = &pll0;
1040         else
1041                 main_clock = &osc0;
1042
1043         if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1044                 pll0.parent = &osc1;
1045         if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1046                 pll1.parent = &osc1;
1047
1048         genclk_init_parent(&gclk0);
1049         genclk_init_parent(&gclk1);
1050         genclk_init_parent(&gclk2);
1051         genclk_init_parent(&gclk3);
1052         genclk_init_parent(&gclk4);
1053         genclk_init_parent(&lcdc0_pixclk);
1054
1055         /*
1056          * Turn on all clocks that have at least one user already, and
1057          * turn off everything else. We only do this for module
1058          * clocks, and even though it isn't particularly pretty to
1059          * check the address of the mode function, it should do the
1060          * trick...
1061          */
1062         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1063                 struct clk *clk = at32_clock_list[i];
1064
1065                 if (clk->mode == &cpu_clk_mode)
1066                         cpu_mask |= 1 << clk->index;
1067                 else if (clk->mode == &hsb_clk_mode)
1068                         hsb_mask |= 1 << clk->index;
1069                 else if (clk->mode == &pba_clk_mode)
1070                         pba_mask |= 1 << clk->index;
1071                 else if (clk->mode == &pbb_clk_mode)
1072                         pbb_mask |= 1 << clk->index;
1073         }
1074
1075         sm_writel(sm, PM_CPU_MASK, cpu_mask);
1076         sm_writel(sm, PM_HSB_MASK, hsb_mask);
1077         sm_writel(sm, PM_PBA_MASK, pba_mask);
1078         sm_writel(sm, PM_PBB_MASK, pbb_mask);
1079 }