2 * linux/arch/arm/vfp/vfphw.S
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This code is called from the kernel's undefined instruction trap.
12 * r9 holds the return address for successful handling.
13 * lr holds the return address for unrecognised instructions.
14 * r10 points at the start of the private FP workspace in the thread structure
15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
17 #include <asm/thread_info.h>
18 #include <asm/vfpmacros.h>
19 #include "../kernel/entry-header.S"
23 stmfd sp!, {r0-r3, ip, lr}
27 .asciz "<7>VFP: \str\n"
29 1: ldmfd sp!, {r0-r3, ip, lr}
33 .macro DBGSTR1, str, arg
35 stmfd sp!, {r0-r3, ip, lr}
40 .asciz "<7>VFP: \str\n"
42 1: ldmfd sp!, {r0-r3, ip, lr}
46 .macro DBGSTR3, str, arg1, arg2, arg3
48 stmfd sp!, {r0-r3, ip, lr}
55 .asciz "<7>VFP: \str\n"
57 1: ldmfd sp!, {r0-r3, ip, lr}
62 @ VFP hardware support entry point.
64 @ r0 = faulted instruction
66 @ r9 = successful return
67 @ r10 = vfp_state union
71 .globl vfp_support_entry
73 DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
75 VFPFMRX r1, FPEXC @ Is the VFP enabled?
76 DBGSTR1 "fpexc %08x", r1
78 bne look_for_VFP_exceptions @ VFP is already enabled
80 DBGSTR1 "enable %x", r10
81 ldr r3, last_VFP_context_address
82 orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
83 ldr r4, [r3, r11, lsl #2] @ last_VFP_context pointer
84 bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
86 beq check_for_exception @ we are returning to the same
87 @ process, so the registers are
88 @ still there. In this case, we do
89 @ not want to drop a pending exception.
91 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
92 @ exceptions, so we can get at the
96 @ Save out the current registers to the old thread state
97 @ No need for SMP since this is not done lazily
99 DBGSTR1 "save old state %p", r4
101 beq no_old_VFP_process
102 VFPFMRX r5, FPSCR @ current status
104 VFPFMRX r6, FPINST @ FPINST (always there, rev0 onwards)
105 tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
106 VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading
107 @ nonexistant reg on rev0
109 VFPFSTMIA r4 @ save the working registers
110 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
111 @ and point r4 at the word at the
112 @ start of the register dump
116 DBGSTR1 "load state %p", r10
117 str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
118 @ Load the saved state back into the VFP
119 VFPFLDMIA r10 @ reload the working registers while
120 @ FPEXC is in a safe state
121 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
123 tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write?
124 VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing
125 @ nonexistant reg on rev0
128 VFPFMXR FPSCR, r5 @ restore status
132 bne process_exception @ might as well handle the pending
133 @ exception before retrying branch
134 @ out before setting an FPEXC that
135 @ stops us reading stuff
136 VFPFMXR FPEXC, r1 @ restore FPEXC last
138 str r2, [sp, #S_PC] @ retry the instruction
139 mov pc, r9 @ we think we have handled things
142 look_for_VFP_exceptions:
144 bne process_exception
146 tst r5, #FPSCR_IXE @ IXE doesn't set FPEXC_EX !
147 bne process_exception
149 @ Fall into hand on to next handler - appropriate coproc instr
150 @ not recognised by VFP
158 str r2, [sp, #S_PC] @ retry the instruction on exit from
159 @ the imprecise exception handling in
161 mov r2, sp @ nothing stacked - regdump is at TOS
162 mov lr, r9 @ setup for a return to the user code.
164 @ Now call the C code to package up the bounce to the support code
165 @ r0 holds the trigger instruction
166 @ r1 holds the FPEXC value
167 @ r2 pointer to register dump
168 b VFP9_bounce @ we have handled this - the support
169 @ code will raise an exception if
170 @ required. If not, the user code will
171 @ retry the faulted instruction
174 .globl vfp_save_state
175 .type vfp_save_state, %function
177 @ Save the current VFP state
180 DBGSTR1 "save VFP state %p", r0
181 VFPFMRX r2, FPSCR @ current status
183 VFPFMRX r3, FPINST @ FPINST (always there, rev0 onwards)
184 tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
185 VFPFMRX r12, FPINST2, NE @ FPINST2 if needed - avoids reading
186 @ nonexistant reg on rev0
188 VFPFSTMIA r0 @ save the working registers
189 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
193 last_VFP_context_address:
194 .word last_VFP_context
198 add pc, pc, r0, lsl #3
200 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
201 mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
203 mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
209 add pc, pc, r1, lsl #3
211 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
212 mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
214 mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
218 .globl vfp_get_double
220 add pc, pc, r0, lsl #3
222 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
227 @ d16 - d31 registers
228 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
229 mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
234 @ virtual register 16 (or 32 if VFPv3) for compare with zero
239 .globl vfp_put_double
241 add pc, pc, r2, lsl #3
243 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
248 @ d16 - d31 registers
249 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
250 mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr