2 * linux/arch/arm/plat-omap/timer32k.c
6 * Copyright (C) 2004 - 2005 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * OMAP Dual-mode timer framework support by Timo Teras
12 * MPU timer code based on the older MPU timer code for OMAP
13 * Copyright (C) 2000 RidgeRun, Inc.
14 * Author: Greg Lonnon <glonnon@ridgerun.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/sched.h>
42 #include <linux/spinlock.h>
43 #include <linux/err.h>
44 #include <linux/clk.h>
45 #include <linux/clocksource.h>
47 #include <asm/system.h>
48 #include <asm/hardware.h>
52 #include <asm/mach/irq.h>
53 #include <asm/mach/time.h>
54 #include <asm/arch/dmtimer.h>
56 struct sys_timer omap_timer;
59 * ---------------------------------------------------------------------------
62 * This currently works only on 16xx, as 1510 does not have the continuous
63 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
64 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * on 1510 would be possible, but the timer would not be as accurate as
66 * with the 32KHz synchronized timer.
67 * ---------------------------------------------------------------------------
70 #if defined(CONFIG_ARCH_OMAP16XX)
71 #define TIMER_32K_SYNCHRONIZED 0xfffbc410
72 #elif defined(CONFIG_ARCH_OMAP24XX)
73 #define TIMER_32K_SYNCHRONIZED 0x48004010
75 #error OMAP 32KHz timer does not currently work on 15XX!
78 /* 16xx specific defines */
79 #define OMAP1_32K_TIMER_BASE 0xfffb9000
80 #define OMAP1_32K_TIMER_CR 0x08
81 #define OMAP1_32K_TIMER_TVR 0x00
82 #define OMAP1_32K_TIMER_TCR 0x04
84 #define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
87 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
88 * so with HZ = 128, TVR = 255.
90 #define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
92 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
93 (((nr_jiffies) * (clock_rate)) / HZ)
95 #if defined(CONFIG_ARCH_OMAP1)
97 static inline void omap_32k_timer_write(int val, int reg)
99 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
102 static inline unsigned long omap_32k_timer_read(int reg)
104 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
107 static inline void omap_32k_timer_start(unsigned long load_val)
111 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
112 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
115 static inline void omap_32k_timer_stop(void)
117 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
120 #define omap_32k_timer_ack_irq()
122 #elif defined(CONFIG_ARCH_OMAP2)
124 static struct omap_dm_timer *gptimer;
126 static inline void omap_32k_timer_start(unsigned long load_val)
128 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
129 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
130 omap_dm_timer_start(gptimer);
133 static inline void omap_32k_timer_stop(void)
135 omap_dm_timer_stop(gptimer);
138 static inline void omap_32k_timer_ack_irq(void)
140 u32 status = omap_dm_timer_read_status(gptimer);
141 omap_dm_timer_write_status(gptimer, status);
147 * The 32KHz synchronized timer is an additional timer on 16xx.
148 * It is always running.
150 static inline unsigned long omap_32k_sync_timer_read(void)
152 return omap_readl(TIMER_32K_SYNCHRONIZED);
156 * Rounds down to nearest usec. Note that this will overflow for larger values.
158 static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
160 return (ticks_32k * 5*5*5*5*5*5) >> 9;
164 * Rounds down to nearest nsec.
166 static inline unsigned long long
167 omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
169 return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
172 static unsigned long omap_32k_last_tick = 0;
175 * Returns current time from boot in nsecs. It's OK for this to wrap
176 * around for now, as it's just a relative time stamp.
178 unsigned long long sched_clock(void)
180 return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
184 * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
185 * function is also called from other interrupts to remove latency
186 * issues with dynamic tick. In the dynamic tick case, we need to lock
189 static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id)
193 omap_32k_timer_ack_irq();
194 now = omap_32k_sync_timer_read();
196 while ((signed long)(now - omap_32k_last_tick)
197 >= OMAP_32K_TICKS_PER_HZ) {
198 omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
202 /* Restart timer so we don't drift off due to modulo or dynamic tick.
203 * By default we program the next timer to be continuous to avoid
204 * latencies during high system load. During dynamic tick operation the
205 * continuous timer can be overridden from pm_idle to be longer.
207 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
212 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
216 write_seqlock_irqsave(&xtime_lock, flags);
217 _omap_32k_timer_interrupt(irq, dev_id);
218 write_sequnlock_irqrestore(&xtime_lock, flags);
223 #ifdef CONFIG_NO_IDLE_HZ
224 static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id)
228 now = omap_32k_sync_timer_read();
230 /* Don't bother reprogramming timer if last tick was before next
231 * jiffie. We will get another interrupt when previously programmed
232 * timer expires. This cuts down interrupt load quite a bit.
234 if (now - omap_32k_last_tick < OMAP_32K_TICKS_PER_HZ)
237 return _omap_32k_timer_interrupt(irq, dev_id);
241 * Programs the next timer interrupt needed. Called when dynamic tick is
242 * enabled, and to reprogram the ticks to skip from pm_idle. Note that
243 * we can keep the timer continuous, and don't need to set it to run in
244 * one-shot mode. This is because the timer will get reprogrammed again
245 * after next interrupt.
247 void omap_32k_timer_reprogram(unsigned long next_tick)
249 unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
250 unsigned long now = omap_32k_sync_timer_read();
251 unsigned long idled = now - omap_32k_last_tick;
253 if (idled + 1 < ticks)
257 omap_32k_timer_start(ticks);
260 static struct irqaction omap_32k_timer_irq;
261 extern struct timer_update_handler timer_update;
263 static int omap_32k_timer_enable_dyn_tick(void)
265 /* No need to reprogram timer, just use the next interrupt */
269 static int omap_32k_timer_disable_dyn_tick(void)
271 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
275 static struct dyn_tick_timer omap_dyn_tick_timer = {
276 .enable = omap_32k_timer_enable_dyn_tick,
277 .disable = omap_32k_timer_disable_dyn_tick,
278 .reprogram = omap_32k_timer_reprogram,
279 .handler = omap_32k_timer_handler,
281 #endif /* CONFIG_NO_IDLE_HZ */
283 static struct irqaction omap_32k_timer_irq = {
284 .name = "32KHz timer",
285 .flags = IRQF_DISABLED | IRQF_TIMER,
286 .handler = omap_32k_timer_interrupt,
289 static __init void omap_init_32k_timer(void)
291 #ifdef CONFIG_NO_IDLE_HZ
292 omap_timer.dyn_tick = &omap_dyn_tick_timer;
295 if (cpu_class_is_omap1())
296 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
297 omap_32k_last_tick = omap_32k_sync_timer_read();
299 #ifdef CONFIG_ARCH_OMAP2
300 /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
301 if (cpu_is_omap24xx()) {
302 gptimer = omap_dm_timer_request_specific(1);
303 BUG_ON(gptimer == NULL);
305 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
306 setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
307 omap_dm_timer_set_int_enable(gptimer,
308 OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
309 OMAP_TIMER_INT_MATCH);
313 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
317 * ---------------------------------------------------------------------------
318 * Timer initialization
319 * ---------------------------------------------------------------------------
321 static void __init omap_timer_init(void)
323 #ifdef CONFIG_OMAP_DM_TIMER
324 omap_dm_timer_init();
326 omap_init_32k_timer();
329 struct sys_timer omap_timer = {
330 .init = omap_timer_init,