2 * linux/arch/arm/plat-omap/timer32k.c
6 * Copyright (C) 2004 - 2005 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * OMAP Dual-mode timer framework support by Timo Teras
12 * MPU timer code based on the older MPU timer code for OMAP
13 * Copyright (C) 2000 RidgeRun, Inc.
14 * Author: Greg Lonnon <glonnon@ridgerun.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/sched.h>
42 #include <linux/spinlock.h>
43 #include <linux/err.h>
44 #include <linux/clk.h>
45 #include <linux/clocksource.h>
46 #include <linux/clockchips.h>
48 #include <asm/system.h>
49 #include <asm/hardware.h>
53 #include <asm/mach/irq.h>
54 #include <asm/mach/time.h>
55 #include <asm/arch/dmtimer.h>
57 struct sys_timer omap_timer;
60 * ---------------------------------------------------------------------------
63 * This currently works only on 16xx, as 1510 does not have the continuous
64 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
65 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
66 * on 1510 would be possible, but the timer would not be as accurate as
67 * with the 32KHz synchronized timer.
68 * ---------------------------------------------------------------------------
71 #if defined(CONFIG_ARCH_OMAP16XX)
72 #define TIMER_32K_SYNCHRONIZED 0xfffbc410
73 #elif defined(CONFIG_ARCH_OMAP24XX)
74 #define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
75 #elif defined(CONFIG_ARCH_OMAP34XX)
76 #define TIMER_32K_SYNCHRONIZED 0x48320010
78 #error OMAP 32KHz timer does not currently work on 15XX!
81 /* 16xx specific defines */
82 #define OMAP1_32K_TIMER_BASE 0xfffb9000
83 #define OMAP1_32K_TIMER_CR 0x08
84 #define OMAP1_32K_TIMER_TVR 0x00
85 #define OMAP1_32K_TIMER_TCR 0x04
87 #define OMAP_32K_TICKS_PER_SEC (32768)
90 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
91 * so with HZ = 128, TVR = 255.
93 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
95 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
96 (((nr_jiffies) * (clock_rate)) / HZ)
98 #if defined(CONFIG_ARCH_OMAP1)
100 static inline void omap_32k_timer_write(int val, int reg)
102 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
105 static inline unsigned long omap_32k_timer_read(int reg)
107 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
110 static inline void omap_32k_timer_start(unsigned long load_val)
114 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
115 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
118 static inline void omap_32k_timer_stop(void)
120 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
123 #define omap_32k_timer_ack_irq()
125 #elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
127 static struct omap_dm_timer *gptimer;
129 static inline void omap_32k_timer_start(unsigned long load_val)
131 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
132 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
133 omap_dm_timer_start(gptimer);
136 static inline void omap_32k_timer_stop(void)
138 omap_dm_timer_stop(gptimer);
141 static inline void omap_32k_timer_ack_irq(void)
143 u32 status = omap_dm_timer_read_status(gptimer);
144 omap_dm_timer_write_status(gptimer, status);
149 static int omap_32k_timer_set_next_event(unsigned long delta,
150 struct clock_event_device *dev)
152 omap_32k_timer_start(delta);
157 static void omap_32k_timer_set_mode(enum clock_event_mode mode,
158 struct clock_event_device *evt)
160 omap_32k_timer_stop();
163 case CLOCK_EVT_MODE_PERIODIC:
164 case CLOCK_EVT_MODE_ONESHOT:
165 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
167 case CLOCK_EVT_MODE_UNUSED:
168 case CLOCK_EVT_MODE_SHUTDOWN:
170 case CLOCK_EVT_MODE_RESUME:
175 static struct clock_event_device clockevent_32k_timer = {
177 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
179 .set_next_event = omap_32k_timer_set_next_event,
180 .set_mode = omap_32k_timer_set_mode,
184 * The 32KHz synchronized timer is an additional timer on 16xx.
185 * It is always running.
187 static inline unsigned long omap_32k_sync_timer_read(void)
189 return omap_readl(TIMER_32K_SYNCHRONIZED);
193 * Rounds down to nearest usec. Note that this will overflow for larger values.
195 static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
197 return (ticks_32k * 5*5*5*5*5*5) >> 9;
201 * Rounds down to nearest nsec.
203 static inline unsigned long long
204 omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
206 return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
210 * Returns current time from boot in nsecs. It's OK for this to wrap
211 * around for now, as it's just a relative time stamp.
213 unsigned long long sched_clock(void)
215 return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
218 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
220 struct clock_event_device *evt = &clockevent_32k_timer;
221 omap_32k_timer_ack_irq();
223 evt->event_handler(evt);
228 static struct irqaction omap_32k_timer_irq = {
229 .name = "32KHz timer",
230 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
231 .handler = omap_32k_timer_interrupt,
234 static __init void omap_init_32k_timer(void)
236 if (cpu_class_is_omap1())
237 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
239 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
240 /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
241 if (cpu_class_is_omap2()) {
242 gptimer = omap_dm_timer_request_specific(1);
243 BUG_ON(gptimer == NULL);
245 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
246 setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
247 omap_dm_timer_set_int_enable(gptimer,
248 OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
249 OMAP_TIMER_INT_MATCH);
253 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
255 clockevent_32k_timer.shift);
256 clockevent_32k_timer.max_delta_ns =
257 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
258 clockevent_32k_timer.min_delta_ns =
259 clockevent_delta2ns(1, &clockevent_32k_timer);
261 clockevent_32k_timer.cpumask = cpumask_of_cpu(0);
262 clockevents_register_device(&clockevent_32k_timer);
266 * ---------------------------------------------------------------------------
267 * Timer initialization
268 * ---------------------------------------------------------------------------
270 static void __init omap_timer_init(void)
272 #ifdef CONFIG_OMAP_DM_TIMER
273 omap_dm_timer_init();
275 omap_init_32k_timer();
278 struct sys_timer omap_timer = {
279 .init = omap_timer_init,