arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/tlb.h>
  20 #include <asm/io.h>
  21 #include <asm/cacheflush.h>
  22
  23 #include <asm/mach/map.h>
  24
  25 #include <asm/arch/sram.h>
  26 #include <asm/arch/board.h>
  27
  28 #include <asm/arch/control.h>
  29
  30 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  31 # include "../mach-omap2/prm.h"
  32 # include "../mach-omap2/cm.h"
  33 # include "../mach-omap2/sdrc.h"
  34 #endif
  35
  36 #define OMAP1_SRAM_PA           0x20000000
  37 #define OMAP1_SRAM_VA           VMALLOC_END
  38 #define OMAP2_SRAM_PA           0x40200000
  39 #define OMAP2_SRAM_PUB_PA       0x4020f800
  40 #define OMAP2_SRAM_VA           VMALLOC_END
  41 #define OMAP2_SRAM_PUB_VA       (VMALLOC_END + 0x800)
  42 #define OMAP3_SRAM_PA           0x40200000
  43 #define OMAP3_SRAM_VA           0xd7000000
  44 #define OMAP3_SRAM_PUB_PA       0x40208000
  45 #define OMAP3_SRAM_PUB_VA       0xd7008000
  46
  47 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  48 #define SRAM_BOOTLOADER_SZ      0x00
  49 #else
  50 #define SRAM_BOOTLOADER_SZ      0x80
  51 #endif
  52
  53 #define OMAP24XX_VA_REQINFOPERM0        IO_ADDRESS(0x68005048)
  54 #define OMAP24XX_VA_READPERM0           IO_ADDRESS(0x68005050)
  55 #define OMAP24XX_VA_WRITEPERM0          IO_ADDRESS(0x68005058)
  56
  57 #define OMAP34XX_VA_REQINFOPERM0        IO_ADDRESS(0x68012848)
  58 #define OMAP34XX_VA_READPERM0           IO_ADDRESS(0x68012850)
  59 #define OMAP34XX_VA_WRITEPERM0          IO_ADDRESS(0x68012858)
  60 #define OMAP34XX_VA_ADDR_MATCH2         IO_ADDRESS(0x68012880)
  61 #define OMAP34XX_VA_SMS_RG_ATT0         IO_ADDRESS(0x6C000048)
  62 #define OMAP34XX_VA_CONTROL_STAT        IO_ADDRESS(0x480022F0)
  63
  64 #define GP_DEVICE               0x300
  65
  66 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  67
  68 static unsigned long omap_sram_start;
  69 static unsigned long omap_sram_base;
  70 static unsigned long omap_sram_size;
  71 static unsigned long omap_sram_ceil;
  72
  73 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  74                                          unsigned long sram_vstart,
  75                                          unsigned long sram_size,
  76                                          unsigned long pstart_avail,
  77                                          unsigned long size_avail);
  78
  79 /* Global symbols in sram-fn.S to be patched with omap_sram_patch_va() */
  80 extern void *omap24xx_sdi_cm_clksel2_pll;
  81 extern void *omap24xx_sdi_sdrc_dlla_ctrl;
  82 extern void *omap24xx_sdi_prcm_voltctrl;
  83 extern void *omap24xx_sdi_timer_32ksynct_cr;
  84 extern void *omap24xx_srs_cm_clksel2_pll;
  85 extern void *omap24xx_srs_sdrc_dlla_ctrl;
  86 extern void *omap24xx_srs_sdrc_rfr_ctrl;
  87 extern void *omap24xx_srs_prcm_voltctrl;
  88 extern void *omap24xx_srs_timer_32ksynct;
  89 extern void *omap24xx_ssp_set_config;
  90 extern void *omap24xx_ssp_pll_ctl;
  91 extern void *omap24xx_ssp_pll_stat;
  92 extern void *omap24xx_ssp_pll_div;
  93 extern void *omap24xx_ssp_sdrc_rfr;
  94 extern void *omap24xx_ssp_dlla_ctrl;
  95
  96
  97 /*
  98  * Depending on the target RAMFS firewall setup, the public usable amount of
  99  * SRAM varies.  The default accessible size for all device types is 2k. A GP
 100  * device allows ARM11 but not other initiators for full size. This
 101  * functionality seems ok until some nice security API happens.
 102  */
 103 static int is_sram_locked(void)
 104 {
 105         int type = 0;
 106
 107         if (cpu_is_omap242x())
 108                 type = system_rev & OMAP2_DEVICETYPE_MASK;
 109
 110         if (type == GP_DEVICE) {
 111                 /* RAMFW: R/W access to all initiators for all qualifier sets */
 112                 if (cpu_is_omap242x()) {
 113                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
 114                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
 115                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
 116                 }
 117                 if (cpu_is_omap34xx()) {
 118                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
 119                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 120                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 121                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 122                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 123                 }
 124                 return 0;
 125         } else
 126                 return 1; /* assume locked with no PPA or security driver */
 127 }
 128
 129 /*
 130  * The amount of SRAM depends on the core type.
 131  * Note that we cannot try to test for SRAM here because writes
 132  * to secure SRAM will hang the system. Also the SRAM is not
 133  * yet mapped at this point.
 134  */
 135 void __init omap_detect_sram(void)
 136 {
 137         unsigned long reserved;
 138
 139         if (cpu_class_is_omap2()) {
 140                 if (is_sram_locked()) {
 141                         if (cpu_is_omap34xx()) {
 142                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 143                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 144                                 omap_sram_size = 0x8000; /* 32K */
 145                         } else {
 146                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 147                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 148                                 omap_sram_size = 0x800; /* 2K */
 149                         }
 150                 } else {
 151                         if (cpu_is_omap34xx()) {
 152                                 omap_sram_base = OMAP3_SRAM_VA;
 153                                 omap_sram_start = OMAP3_SRAM_PA;
 154                                 omap_sram_size = 0x10000; /* 64K */
 155                         } else {
 156                                 omap_sram_base = OMAP2_SRAM_VA;
 157                                 omap_sram_start = OMAP2_SRAM_PA;
 158                                 if (cpu_is_omap242x())
 159                                         omap_sram_size = 0xa0000; /* 640K */
 160                                 else if (cpu_is_omap243x())
 161                                         omap_sram_size = 0x10000; /* 64K */
 162                         }
 163                 }
 164         } else {
 165                 omap_sram_base = OMAP1_SRAM_VA;
 166                 omap_sram_start = OMAP1_SRAM_PA;
 167
 168                 if (cpu_is_omap730())
 169                         omap_sram_size = 0x32000;       /* 200K */
 170                 else if (cpu_is_omap15xx())
 171                         omap_sram_size = 0x30000;       /* 192K */
 172                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 173                      cpu_is_omap1710())
 174                         omap_sram_size = 0x4000;        /* 16K */
 175                 else if (cpu_is_omap1611())
 176                         omap_sram_size = 0x3e800;       /* 250K */
 177                 else {
 178                         printk(KERN_ERR "Could not detect SRAM size\n");
 179                         omap_sram_size = 0x4000;
 180                 }
 181         }
 182         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 183                                        omap_sram_size,
 184                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 185                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 186         omap_sram_size -= reserved;
 187         omap_sram_ceil = omap_sram_base + omap_sram_size;
 188 }
 189
 190 static struct map_desc omap_sram_io_desc[] __initdata = {
 191         {       /* .length gets filled in at runtime */
 192                 .virtual        = OMAP1_SRAM_VA,
 193                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 194                 .type           = MT_MEMORY
 195         }
 196 };
 197
 198 /*
 199  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 200  */
 201 void __init omap_map_sram(void)
 202 {
 203         unsigned long base;
 204
 205         if (omap_sram_size == 0)
 206                 return;
 207
 208         if (cpu_is_omap24xx()) {
 209                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 210
 211                 base = OMAP2_SRAM_PA;
 212                 base = ROUND_DOWN(base, PAGE_SIZE);
 213                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 214         }
 215
 216         if (cpu_is_omap34xx()) {
 217                 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
 218                 base = OMAP3_SRAM_PA;
 219                 base = ROUND_DOWN(base, PAGE_SIZE);
 220                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 221         }
 222
 223         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 224         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 225
 226         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 227         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 228         omap_sram_io_desc[0].virtual,
 229                omap_sram_io_desc[0].length);
 230
 231         /*
 232          * Normally devicemaps_init() would flush caches and tlb after
 233          * mdesc->map_io(), but since we're called from map_io(), we
 234          * must do it here.
 235          */
 236         local_flush_tlb_all();
 237         flush_cache_all();
 238
 239         /*
 240          * Looks like we need to preserve some bootloader code at the
 241          * beginning of SRAM for jumping to flash for reboot to work...
 242          */
 243         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 244                omap_sram_size - SRAM_BOOTLOADER_SZ);
 245 }
 246
 247 void * omap_sram_push(void * start, unsigned long size)
 248 {
 249         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 250                 printk(KERN_ERR "Not enough space in SRAM\n");
 251                 return NULL;
 252         }
 253
 254         omap_sram_ceil -= size;
 255         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 256         memcpy((void *)omap_sram_ceil, start, size);
 257         flush_icache_range((unsigned long)start, (unsigned long)(start + size));
 258
 259         return (void *)omap_sram_ceil;
 260 }
 261
 262 /**
 263  * omap_sram_patch_va - patch a virtual address into SRAM code
 264  * @srcfn: original start address (in DRAM) of function to patch
 265  * @srcd: original address (in DRAM) of location to patch
 266  * @sramfn: start address (in SRAM) of function to patch
 267  * @d: virtual address to insert
 268  *
 269  * Replace a location in SRAM containing a magic number
 270  * (SRAM_VA_MAGIC) with a caller-specified virtual address.  Used to
 271  * dynamically patch SRAM code at runtime for multiboot, since some
 272  * register addresses change depending on the OMAP chip in use.
 273  * Returns 1 upon success, 0 upon failure.
 274  */
 275 int omap_sram_patch_va(void *srcfn, void *srcd, void *sramfn, void __iomem *d)
 276 {
 277         unsigned long sram_addr;
 278         long offs;
 279
 280         offs = (unsigned long)srcd - (unsigned long)srcfn;
 281         sram_addr = (unsigned long)sramfn + offs;
 282
 283 #ifdef CONFIG_OMAP_DEBUG_SRAM_PATCH
 284         if (offs < 0) {
 285                 printk(KERN_ERR "sram: patch address 0x%0lx < function start "
 286                        "address 0x%0lx\n", (unsigned long)srcd,
 287                        (unsigned long)srcfn);
 288                 WARN_ON(1);
 289                 return 0;
 290         }
 291
 292         /*
 293          * REVISIT: We should probably pass in the function's size also,
 294          * so we can verify that the address to patch exists within
 295          * the function
 296          */
 297         if (sram_addr > omap_sram_base + omap_sram_size ||
 298             sram_addr < omap_sram_base + SRAM_BOOTLOADER_SZ) {
 299                 printk(KERN_ERR "sram: invalid patch address 0x%0lx\n",
 300                        sram_addr);
 301                 WARN_ON(1);
 302                 return 0;
 303         }
 304
 305         if (*(typeof(SRAM_VA_MAGIC) *)sram_addr != SRAM_VA_MAGIC) {
 306                 printk(KERN_ERR "sram: will not patch address 0x%0lx: "
 307                        "no magic\n", sram_addr);
 308                 WARN_ON(1);
 309                 return 0;
 310         }
 311 #endif /* CONFIG_OMAP_DEBUG_SRAM_PATCH */
 312
 313         pr_debug("sram: patching 0x%0lx with 0x%0lx\n", sram_addr,
 314                  (unsigned long)d);
 315
 316         *(unsigned long *)sram_addr = (unsigned long)d;
 317
 318         return 1;
 319 }
 320
 321
 322 static void omap_sram_error(void)
 323 {
 324         panic("Uninitialized SRAM function\n");
 325 }
 326
 327 #ifdef CONFIG_ARCH_OMAP1
 328
 329 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 330
 331 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 332 {
 333         if (!_omap_sram_reprogram_clock)
 334                 omap_sram_error();
 335
 336         return _omap_sram_reprogram_clock(dpllctl, ckctl);
 337 }
 338
 339 int __init omap1_sram_init(void)
 340 {
 341         _omap_sram_reprogram_clock =
 342                         omap_sram_push(omap1_sram_reprogram_clock,
 343                                         omap1_sram_reprogram_clock_sz);
 344
 345         return 0;
 346 }
 347
 348 #else
 349 #define omap1_sram_init()       do {} while (0)
 350 #endif
 351
 352 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 353
 354 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 355                               u32 base_cs, u32 force_unlock);
 356
 357 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 358                    u32 base_cs, u32 force_unlock)
 359 {
 360         if (!_omap2_sram_ddr_init)
 361                 omap_sram_error();
 362
 363         return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 364                                     base_cs, force_unlock);
 365 }
 366
 367 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 368                                           u32 mem_type);
 369
 370 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 371 {
 372         if (!_omap2_sram_reprogram_sdrc)
 373                 omap_sram_error();
 374
 375         return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 376 }
 377
 378 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 379
 380 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 381 {
 382         if (!_omap2_set_prcm)
 383                 omap_sram_error();
 384
 385         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 386 }
 387 #endif
 388
 389 #ifdef CONFIG_ARCH_OMAP2
 390 int __init omap24xx_sram_init(void)
 391 {
 392         _omap2_sram_ddr_init = omap_sram_push(omap24xx_sram_ddr_init,
 393                                         omap24xx_sram_ddr_init_sz);
 394
 395         /* Patch in the correct register addresses for multiboot */
 396         omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_cm_clksel2_pll,
 397                            _omap2_sram_ddr_init,
 398                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
 399         omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_sdrc_dlla_ctrl,
 400                            _omap2_sram_ddr_init,
 401                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 402         omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_prcm_voltctrl,
 403                            _omap2_sram_ddr_init, OMAP24XX_PRCM_VOLTCTRL);
 404         omap_sram_patch_va(omap24xx_sram_ddr_init,
 405                            &omap24xx_sdi_timer_32ksynct_cr,
 406                            _omap2_sram_ddr_init,
 407                            (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
 408
 409         _omap2_sram_reprogram_sdrc = omap_sram_push(omap24xx_sram_reprogram_sdrc,
 410                                                     omap24xx_sram_reprogram_sdrc_sz);
 411
 412         omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
 413                            &omap24xx_srs_cm_clksel2_pll,
 414                            _omap2_sram_reprogram_sdrc,
 415                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
 416         omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
 417                            &omap24xx_srs_sdrc_dlla_ctrl,
 418                            _omap2_sram_reprogram_sdrc,
 419                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 420         omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
 421                            &omap24xx_srs_sdrc_rfr_ctrl,
 422                            _omap2_sram_reprogram_sdrc,
 423                            OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
 424         omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
 425                            &omap24xx_srs_prcm_voltctrl,
 426                            _omap2_sram_reprogram_sdrc,
 427                            OMAP24XX_PRCM_VOLTCTRL);
 428         omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
 429                            &omap24xx_srs_timer_32ksynct,
 430                            _omap2_sram_reprogram_sdrc,
 431                            (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
 432
 433         _omap2_set_prcm = omap_sram_push(omap24xx_sram_set_prcm,
 434                                          omap24xx_sram_set_prcm_sz);
 435
 436         omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_set_config,
 437                            _omap2_set_prcm,
 438                            OMAP24XX_PRCM_CLKCFG_CTRL);
 439         omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_ctl,
 440                            _omap2_set_prcm,
 441                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN));
 442         omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_stat,
 443                            _omap2_set_prcm,
 444                            OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST));
 445         omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_div,
 446                            _omap2_set_prcm,
 447                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1));
 448         omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_sdrc_rfr,
 449                            _omap2_set_prcm,
 450                            OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
 451         omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_dlla_ctrl,
 452                            _omap2_set_prcm,
 453                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 454
 455         return 0;
 456 }
 457 #else
 458 static inline int omap24xx_sram_init(void)
 459 {
 460         return 0;
 461 }
 462 #endif
 463
 464 int __init omap_sram_init(void)
 465 {
 466         omap_detect_sram();
 467         omap_map_sram();
 468
 469         if (!(cpu_class_is_omap2()))
 470                 omap1_sram_init();
 471         else if (cpu_is_omap24xx())
 472                 omap24xx_sram_init();
 473
 474         return 0;
 475 }