arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/tlb.h>
  20 #include <asm/io.h>
  21 #include <asm/cacheflush.h>
  22
  23 #include <asm/mach/map.h>
  24
  25 #include <asm/arch/sram.h>
  26 #include <asm/arch/board.h>
  27
  28 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  29 # include "../mach-omap2/prm.h"
  30 # include "../mach-omap2/cm.h"
  31 # include "../mach-omap2/sdrc.h"
  32 #endif
  33
  34 #define OMAP1_SRAM_PA           0x20000000
  35 #define OMAP1_SRAM_VA           0xd0000000
  36 #define OMAP2_SRAM_PA           0x40200000
  37 #define OMAP2_SRAM_PUB_PA       0x4020f800
  38 #define OMAP2_SRAM_VA           0xd0000000
  39 #define OMAP2_SRAM_PUB_VA       0xd0000800
  40
  41 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  42 #define SRAM_BOOTLOADER_SZ      0x00
  43 #else
  44 #define SRAM_BOOTLOADER_SZ      0x80
  45 #endif
  46
  47 #define VA_REQINFOPERM0         IO_ADDRESS(0x68005048)
  48 #define VA_READPERM0            IO_ADDRESS(0x68005050)
  49 #define VA_WRITEPERM0           IO_ADDRESS(0x68005058)
  50 #define VA_CONTROL_STAT         IO_ADDRESS(0x480002F8)
  51 #define GP_DEVICE               0x300
  52 #define TYPE_MASK               0x700
  53
  54 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  55
  56 static unsigned long omap_sram_start;
  57 static unsigned long omap_sram_base;
  58 static unsigned long omap_sram_size;
  59 static unsigned long omap_sram_ceil;
  60
  61 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  62                                          unsigned long sram_vstart,
  63                                          unsigned long sram_size,
  64                                          unsigned long pstart_avail,
  65                                          unsigned long size_avail);
  66
  67 /* Global symbols in sram-fn.S to be patched with omap_sram_patch_va() */
  68 extern void *omap2_sdi_cm_clksel2_pll;
  69 extern void *omap2_sdi_sdrc_dlla_ctrl;
  70 extern void *omap2_sdi_prcm_voltctrl;
  71 extern void *omap2_sdi_timer_32ksynct_cr;
  72 extern void *omap2_srs_cm_clksel2_pll;
  73 extern void *omap2_srs_sdrc_dlla_ctrl;
  74 extern void *omap2_srs_sdrc_rfr_ctrl;
  75 extern void *omap2_srs_prcm_voltctrl;
  76 extern void *omap2_srs_timer_32ksynct;
  77 extern void *omap2_ssp_set_config;
  78 extern void *omap2_ssp_pll_ctl;
  79 extern void *omap2_ssp_pll_stat;
  80 extern void *omap2_ssp_pll_div;
  81 extern void *omap2_ssp_sdrc_rfr;
  82 extern void *omap2_ssp_dlla_ctrl;
  83
  84
  85 /*
  86  * Depending on the target RAMFS firewall setup, the public usable amount of
  87  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  88  * device allows ARM11 but not other initiators for full size. This
  89  * functionality seems ok until some nice security API happens.
  90  */
  91 static int is_sram_locked(void)
  92 {
  93         int type = 0;
  94
  95         if (cpu_is_omap242x())
  96                 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
  97
  98         if (type == GP_DEVICE) {
  99                 /* RAMFW: R/W access to all initiators for all qualifier sets */
 100                 if (cpu_is_omap242x()) {
 101                         __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
 102                         __raw_writel(0xCFDE, VA_READPERM0);  /* all i-read */
 103                         __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */
 104                 }
 105                 return 0;
 106         } else
 107                 return 1; /* assume locked with no PPA or security driver */
 108 }
 109
 110 /*
 111  * The amount of SRAM depends on the core type.
 112  * Note that we cannot try to test for SRAM here because writes
 113  * to secure SRAM will hang the system. Also the SRAM is not
 114  * yet mapped at this point.
 115  */
 116 void __init omap_detect_sram(void)
 117 {
 118         unsigned long reserved;
 119
 120         if (cpu_class_is_omap2()) {
 121                 if (is_sram_locked()) {
 122                         omap_sram_base = OMAP2_SRAM_PUB_VA;
 123                         omap_sram_start = OMAP2_SRAM_PUB_PA;
 124                         omap_sram_size = 0x800; /* 2K */
 125                 } else {
 126                         omap_sram_base = OMAP2_SRAM_VA;
 127                         omap_sram_start = OMAP2_SRAM_PA;
 128                         if (cpu_is_omap242x())
 129                                 omap_sram_size = 0xa0000; /* 640K */
 130                         else if (cpu_is_omap243x() || cpu_is_omap34xx())
 131                                 omap_sram_size = 0x10000; /* 64K */
 132                 }
 133         } else {
 134                 omap_sram_base = OMAP1_SRAM_VA;
 135                 omap_sram_start = OMAP1_SRAM_PA;
 136
 137                 if (cpu_is_omap730())
 138                         omap_sram_size = 0x32000;       /* 200K */
 139                 else if (cpu_is_omap15xx())
 140                         omap_sram_size = 0x30000;       /* 192K */
 141                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 142                      cpu_is_omap1710())
 143                         omap_sram_size = 0x4000;        /* 16K */
 144                 else if (cpu_is_omap1611())
 145                         omap_sram_size = 0x3e800;       /* 250K */
 146                 else {
 147                         printk(KERN_ERR "Could not detect SRAM size\n");
 148                         omap_sram_size = 0x4000;
 149                 }
 150         }
 151         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 152                                        omap_sram_size,
 153                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 154                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 155         omap_sram_size -= reserved;
 156         omap_sram_ceil = omap_sram_base + omap_sram_size;
 157 }
 158
 159 static struct map_desc omap_sram_io_desc[] __initdata = {
 160         {       /* .length gets filled in at runtime */
 161                 .virtual        = OMAP1_SRAM_VA,
 162                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 163                 .type           = MT_MEMORY
 164         }
 165 };
 166
 167 /*
 168  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 169  */
 170 void __init omap_map_sram(void)
 171 {
 172         unsigned long base;
 173
 174         if (omap_sram_size == 0)
 175                 return;
 176
 177         if (cpu_class_is_omap2()) {
 178                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 179
 180                 base = OMAP2_SRAM_PA;
 181                 base = ROUND_DOWN(base, PAGE_SIZE);
 182                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 183         }
 184
 185         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 186         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 187
 188         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 189         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 190         omap_sram_io_desc[0].virtual,
 191                omap_sram_io_desc[0].length);
 192
 193         /*
 194          * Normally devicemaps_init() would flush caches and tlb after
 195          * mdesc->map_io(), but since we're called from map_io(), we
 196          * must do it here.
 197          */
 198         local_flush_tlb_all();
 199         flush_cache_all();
 200
 201         /*
 202          * Looks like we need to preserve some bootloader code at the
 203          * beginning of SRAM for jumping to flash for reboot to work...
 204          */
 205         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 206                omap_sram_size - SRAM_BOOTLOADER_SZ);
 207 }
 208
 209 void * omap_sram_push(void * start, unsigned long size)
 210 {
 211         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 212                 printk(KERN_ERR "Not enough space in SRAM\n");
 213                 return NULL;
 214         }
 215
 216         omap_sram_ceil -= size;
 217         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 218         memcpy((void *)omap_sram_ceil, start, size);
 219
 220         return (void *)omap_sram_ceil;
 221 }
 222
 223 /**
 224  * omap_sram_patch_va - patch a virtual address into SRAM code
 225  * @srcfn: original start address (in DRAM) of function to patch
 226  * @srcd: original address (in DRAM) of location to patch
 227  * @sramfn: start address (in SRAM) of function to patch
 228  * @d: virtual address to insert
 229  *
 230  * Replace a location in SRAM containing a magic number
 231  * (SRAM_VA_MAGIC) with a caller-specified virtual address.  Used to
 232  * dynamically patch SRAM code at runtime for multiboot, since some
 233  * register addresses change depending on the OMAP chip in use.
 234  * Returns 1 upon success, 0 upon failure.
 235  */
 236 int omap_sram_patch_va(void *srcfn, void *srcd, void *sramfn, void __iomem *d)
 237 {
 238         unsigned long sram_addr;
 239         long offs;
 240
 241         offs = (unsigned long)srcd - (unsigned long)srcfn;
 242         sram_addr = (unsigned long)sramfn + offs;
 243
 244 #ifdef CONFIG_OMAP_DEBUG_SRAM_PATCH
 245         if (offs < 0) {
 246                 printk(KERN_ERR "sram: patch address 0x%0lx < function start "
 247                        "address 0x%0lx\n", (unsigned long)srcd,
 248                        (unsigned long)srcfn);
 249                 WARN_ON(1);
 250                 return 0;
 251         }
 252
 253         /*
 254          * REVISIT: We should probably pass in the function's size also,
 255          * so we can verify that the address to patch exists within
 256          * the function
 257          */
 258         if (sram_addr > omap_sram_base + omap_sram_size ||
 259             sram_addr < omap_sram_base + SRAM_BOOTLOADER_SZ) {
 260                 printk(KERN_ERR "sram: invalid patch address 0x%0lx\n",
 261                        sram_addr);
 262                 WARN_ON(1);
 263                 return 0;
 264         }
 265
 266         if (*(typeof(SRAM_VA_MAGIC) *)sram_addr != SRAM_VA_MAGIC) {
 267                 printk(KERN_ERR "sram: will not patch address 0x%0lx: "
 268                        "no magic\n", sram_addr);
 269                 WARN_ON(1);
 270                 return 0;
 271         }
 272 #endif /* CONFIG_OMAP_DEBUG_SRAM_PATCH */
 273
 274         pr_debug("sram: patching 0x%0lx with 0x%0lx\n", sram_addr,
 275                  (unsigned long)d);
 276
 277         *(unsigned long *)sram_addr = (unsigned long)d;
 278
 279         return 1;
 280 }
 281
 282
 283 static void omap_sram_error(void)
 284 {
 285         panic("Uninitialized SRAM function\n");
 286 }
 287
 288 #ifdef CONFIG_ARCH_OMAP1
 289
 290 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 291
 292 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 293 {
 294         if (!_omap_sram_reprogram_clock)
 295                 omap_sram_error();
 296
 297         return _omap_sram_reprogram_clock(dpllctl, ckctl);
 298 }
 299
 300 int __init omap1_sram_init(void)
 301 {
 302         _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
 303                                                     sram_reprogram_clock_sz);
 304
 305         return 0;
 306 }
 307
 308 #else
 309 #define omap1_sram_init()       do {} while (0)
 310 #endif
 311
 312 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 313
 314 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 315                               u32 base_cs, u32 force_unlock);
 316
 317 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 318                    u32 base_cs, u32 force_unlock)
 319 {
 320         if (!_omap2_sram_ddr_init)
 321                 omap_sram_error();
 322
 323         return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 324                                     base_cs, force_unlock);
 325 }
 326
 327 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 328                                           u32 mem_type);
 329
 330 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 331 {
 332         if (!_omap2_sram_reprogram_sdrc)
 333                 omap_sram_error();
 334
 335         return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 336 }
 337
 338 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 339
 340 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 341 {
 342         if (!_omap2_set_prcm)
 343                 omap_sram_error();
 344
 345         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 346 }
 347
 348 int __init omap2_sram_init(void)
 349 {
 350         _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
 351
 352         /* Patch in the correct register addresses for multiboot */
 353         omap_sram_patch_va(sram_ddr_init, &omap2_sdi_cm_clksel2_pll,
 354                            _omap2_sram_ddr_init,
 355                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
 356         omap_sram_patch_va(sram_ddr_init, &omap2_sdi_sdrc_dlla_ctrl,
 357                            _omap2_sram_ddr_init,
 358                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 359         omap_sram_patch_va(sram_ddr_init, &omap2_sdi_prcm_voltctrl,
 360                            _omap2_sram_ddr_init, OMAP24XX_PRCM_VOLTCTRL);
 361         omap_sram_patch_va(sram_ddr_init, &omap2_sdi_timer_32ksynct_cr,
 362                            _omap2_sram_ddr_init,
 363                            (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
 364
 365         _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
 366                                                     sram_reprogram_sdrc_sz);
 367
 368         omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_cm_clksel2_pll,
 369                            _omap2_sram_reprogram_sdrc,
 370                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
 371         omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_sdrc_dlla_ctrl,
 372                            _omap2_sram_reprogram_sdrc,
 373                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 374         omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_sdrc_rfr_ctrl,
 375                            _omap2_sram_reprogram_sdrc,
 376                            OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
 377         omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_prcm_voltctrl,
 378                            _omap2_sram_reprogram_sdrc,
 379                            OMAP24XX_PRCM_VOLTCTRL);
 380         omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_timer_32ksynct,
 381                            _omap2_sram_reprogram_sdrc,
 382                            (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
 383
 384         _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
 385
 386         /* REVISIT: prefix all these symbols with omap2_sram_ */
 387         omap_sram_patch_va(sram_set_prcm, &omap2_ssp_set_config,
 388                            _omap2_set_prcm,
 389                            OMAP24XX_PRCM_CLKCFG_CTRL);
 390         omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_ctl,
 391                            _omap2_set_prcm,
 392                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN));
 393         omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_stat,
 394                            _omap2_set_prcm,
 395                            OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST));
 396         omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_div,
 397                            _omap2_set_prcm,
 398                            OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1));
 399         omap_sram_patch_va(sram_set_prcm, &omap2_ssp_sdrc_rfr,
 400                            _omap2_set_prcm,
 401                            OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
 402         omap_sram_patch_va(sram_set_prcm, &omap2_ssp_dlla_ctrl,
 403                            _omap2_set_prcm,
 404                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 405
 406         return 0;
 407 }
 408 #else
 409 #define omap2_sram_init()       do {} while (0)
 410 #endif
 411
 412 int __init omap_sram_init(void)
 413 {
 414         omap_detect_sram();
 415         omap_map_sram();
 416
 417         if (!(cpu_class_is_omap2()))
 418                 omap1_sram_init();
 419         else
 420                 omap2_sram_init();
 421
 422         return 0;
 423 }