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1 /*
2  * linux/arch/arm/plat-omap/pm.c
3  *
4  * OMAP Power Management Routines
5  *
6  * Original code for the SA11x0:
7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8  *
9  * Modified for the PXA250 by Nicolas Pitre:
10  * Copyright (c) 2002 Monta Vista Software, Inc.
11  *
12  * Modified for the OMAP1510 by David Singleton:
13  * Copyright (c) 2002 Monta Vista Software, Inc.
14  *
15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16  *
17  * This program is free software; you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation; either version 2 of the License, or (at your
20  * option) any later version.
21  *
22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * You should have received a copy of the GNU General Public License along
34  * with this program; if not, write to the Free Software Foundation, Inc.,
35  * 675 Mass Ave, Cambridge, MA 02139, USA.
36  */
37
38 #include <linux/pm.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/pm.h>
42 #include <linux/interrupt.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/mach/time.h>
47 #include <asm/mach/irq.h>
48
49 #include <asm/mach-types.h>
50 #include <asm/arch/irqs.h>
51 #include <asm/arch/tc.h>
52 #include <asm/arch/pm.h>
53 #include <asm/arch/mux.h>
54 #include <asm/arch/tps65010.h>
55 #include <asm/arch/dsp_common.h>
56
57 #include "clock.h"
58 #include "sram.h"
59
60 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
61 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
62 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
63 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
64
65 static void (*omap_sram_idle)(void) = NULL;
66 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
67
68 /*
69  * Let's power down on idle, but only if we are really
70  * idle, because once we start down the path of
71  * going idle we continue to do idle even if we get
72  * a clock tick interrupt . .
73  */
74 void omap_pm_idle(void)
75 {
76         unsigned int mask32 = 0;
77
78         /*
79          * If the DSP is being used let's just idle the CPU, the overhead
80          * to wake up from Big Sleep is big, milliseconds versus micro
81          * seconds for wait for interrupt.
82          */
83
84         local_irq_disable();
85         local_fiq_disable();
86         if (need_resched()) {
87                 local_fiq_enable();
88                 local_irq_enable();
89                 return;
90         }
91         mask32 = omap_readl(ARM_SYSST);
92
93         /*
94          * Prevent the ULPD from entering low power state by setting
95          * POWER_CTRL_REG:4 = 0
96          */
97         omap_writew(omap_readw(ULPD_POWER_CTRL) &
98                     ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
99
100         /*
101          * Since an interrupt may set up a timer, we don't want to
102          * reprogram the hardware timer with interrupts enabled.
103          * Re-enable interrupts only after returning from idle.
104          */
105         timer_dyn_reprogram();
106
107         if ((mask32 & DSP_IDLE) == 0) {
108                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
109         } else
110                 omap_sram_idle();
111
112         local_fiq_enable();
113         local_irq_enable();
114 }
115
116 /*
117  * Configuration of the wakeup event is board specific. For the
118  * moment we put it into this helper function. Later it may move
119  * to board specific files.
120  */
121 static void omap_pm_wakeup_setup(void)
122 {
123         u32 level1_wake = OMAP_IRQ_BIT(INT_IH2_IRQ);
124         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2) | OMAP_IRQ_BIT(INT_KEYBOARD);
125
126         /*
127          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
128          * and the L2 wakeup interrupts: keypad and UART2. Note that the
129          * drivers must still separately call omap_set_gpio_wakeup() to
130          * wake up to a GPIO interrupt.
131          */
132         if (cpu_is_omap1510() || cpu_is_omap16xx())
133                 level1_wake |= OMAP_IRQ_BIT(INT_GPIO_BANK1);
134         else if (cpu_is_omap730())
135                 level1_wake |= OMAP_IRQ_BIT(INT_730_GPIO_BANK1);
136
137         omap_writel(~level1_wake, OMAP_IH1_MIR);
138
139         if (cpu_is_omap1510())
140                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
141
142         /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
143         if (cpu_is_omap16xx()) {
144                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
145                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
146                 omap_writel(~0x0, OMAP_IH2_2_MIR);
147                 omap_writel(~0x0, OMAP_IH2_3_MIR);
148         }
149
150         /*  New IRQ agreement, recalculate in cascade order */
151         omap_writel(1, OMAP_IH2_CONTROL);
152         omap_writel(1, OMAP_IH1_CONTROL);
153 }
154
155 void omap_pm_suspend(void)
156 {
157         unsigned long arg0 = 0, arg1 = 0;
158
159         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
160
161         omap_serial_wake_trigger(1);
162
163         if (machine_is_omap_osk()) {
164                 /* Stop LED1 (D9) blink */
165                 tps65010_set_led(LED1, OFF);
166         }
167
168         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
169
170         /*
171          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
172          */
173
174         local_irq_disable();
175         local_fiq_disable();
176
177         /*
178          * Step 2: save registers
179          *
180          * The omap is a strange/beautiful device. The caches, memory
181          * and register state are preserved across power saves.
182          * We have to save and restore very little register state to
183          * idle the omap.
184          *
185          * Save interrupt, MPUI, ARM and UPLD control registers.
186          */
187
188         if (cpu_is_omap1510()) {
189                 MPUI1510_SAVE(OMAP_IH1_MIR);
190                 MPUI1510_SAVE(OMAP_IH2_MIR);
191                 MPUI1510_SAVE(MPUI_CTRL);
192                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
193                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
194                 MPUI1510_SAVE(EMIFS_CONFIG);
195                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
196         } else if (cpu_is_omap16xx()) {
197                 MPUI1610_SAVE(OMAP_IH1_MIR);
198                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
199                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
200                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
201                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
202                 MPUI1610_SAVE(MPUI_CTRL);
203                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
204                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
205                 MPUI1610_SAVE(EMIFS_CONFIG);
206                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
207         }
208
209         ARM_SAVE(ARM_CKCTL);
210         ARM_SAVE(ARM_IDLECT1);
211         ARM_SAVE(ARM_IDLECT2);
212         if (!(cpu_is_omap1510()))
213                 ARM_SAVE(ARM_IDLECT3);
214         ARM_SAVE(ARM_EWUPCT);
215         ARM_SAVE(ARM_RSTCT1);
216         ARM_SAVE(ARM_RSTCT2);
217         ARM_SAVE(ARM_SYSST);
218         ULPD_SAVE(ULPD_CLOCK_CTRL);
219         ULPD_SAVE(ULPD_STATUS_REQ);
220
221         /* (Step 3 removed - we now allow deep sleep by default) */
222
223         /*
224          * Step 4: OMAP DSP Shutdown
225          */
226
227
228         /*
229          * Step 5: Wakeup Event Setup
230          */
231
232         omap_pm_wakeup_setup();
233
234         /*
235          * Step 6: ARM and Traffic controller shutdown
236          */
237
238         /* disable ARM watchdog */
239         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
240         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
241
242         /*
243          * Step 6b: ARM and Traffic controller shutdown
244          *
245          * Step 6 continues here. Prepare jump to power management
246          * assembly code in internal SRAM.
247          *
248          * Since the omap_cpu_suspend routine has been copied to
249          * SRAM, we'll do an indirect procedure call to it and pass the
250          * contents of arm_idlect1 and arm_idlect2 so it can restore
251          * them when it wakes up and it will return.
252          */
253
254         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
255         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
256
257         /*
258          * Step 6c: ARM and Traffic controller shutdown
259          *
260          * Jump to assembly code. The processor will stay there
261          * until wake up.
262          */
263         omap_sram_suspend(arg0, arg1);
264
265         /*
266          * If we are here, processor is woken up!
267          */
268
269         /*
270          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
271          */
272
273         if (!(cpu_is_omap1510()))
274                 ARM_RESTORE(ARM_IDLECT3);
275         ARM_RESTORE(ARM_CKCTL);
276         ARM_RESTORE(ARM_EWUPCT);
277         ARM_RESTORE(ARM_RSTCT1);
278         ARM_RESTORE(ARM_RSTCT2);
279         ARM_RESTORE(ARM_SYSST);
280         ULPD_RESTORE(ULPD_CLOCK_CTRL);
281         ULPD_RESTORE(ULPD_STATUS_REQ);
282
283         if (cpu_is_omap1510()) {
284                 MPUI1510_RESTORE(MPUI_CTRL);
285                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
286                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
287                 MPUI1510_RESTORE(EMIFS_CONFIG);
288                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
289                 MPUI1510_RESTORE(OMAP_IH1_MIR);
290                 MPUI1510_RESTORE(OMAP_IH2_MIR);
291         } else if (cpu_is_omap16xx()) {
292                 MPUI1610_RESTORE(MPUI_CTRL);
293                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
294                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
295                 MPUI1610_RESTORE(EMIFS_CONFIG);
296                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
297
298                 MPUI1610_RESTORE(OMAP_IH1_MIR);
299                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
300                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
301                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
302                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
303         }
304
305         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
306
307         /*
308          * Reenable interrupts
309          */
310
311         local_irq_enable();
312         local_fiq_enable();
313
314         omap_serial_wake_trigger(0);
315
316         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
317
318         if (machine_is_omap_osk()) {
319                 /* Let LED1 (D9) blink again */
320                 tps65010_set_led(LED1, BLINK);
321         }
322 }
323
324 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
325 static int g_read_completed;
326
327 /*
328  * Read system PM registers for debugging
329  */
330 static int omap_pm_read_proc(
331         char *page_buffer,
332         char **my_first_byte,
333         off_t virtual_start,
334         int length,
335         int *eof,
336         void *data)
337 {
338         int my_buffer_offset = 0;
339         char * const my_base = page_buffer;
340
341         ARM_SAVE(ARM_CKCTL);
342         ARM_SAVE(ARM_IDLECT1);
343         ARM_SAVE(ARM_IDLECT2);
344         if (!(cpu_is_omap1510()))
345                 ARM_SAVE(ARM_IDLECT3);
346         ARM_SAVE(ARM_EWUPCT);
347         ARM_SAVE(ARM_RSTCT1);
348         ARM_SAVE(ARM_RSTCT2);
349         ARM_SAVE(ARM_SYSST);
350
351         ULPD_SAVE(ULPD_IT_STATUS);
352         ULPD_SAVE(ULPD_CLOCK_CTRL);
353         ULPD_SAVE(ULPD_SOFT_REQ);
354         ULPD_SAVE(ULPD_STATUS_REQ);
355         ULPD_SAVE(ULPD_DPLL_CTRL);
356         ULPD_SAVE(ULPD_POWER_CTRL);
357
358         if (cpu_is_omap1510()) {
359                 MPUI1510_SAVE(MPUI_CTRL);
360                 MPUI1510_SAVE(MPUI_DSP_STATUS);
361                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
362                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
363                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
364                 MPUI1510_SAVE(EMIFS_CONFIG);
365         } else if (cpu_is_omap16xx()) {
366                 MPUI1610_SAVE(MPUI_CTRL);
367                 MPUI1610_SAVE(MPUI_DSP_STATUS);
368                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
369                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
370                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
371                 MPUI1610_SAVE(EMIFS_CONFIG);
372         }
373
374         if (virtual_start == 0) {
375                 g_read_completed = 0;
376
377                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
378                    "ARM_CKCTL_REG:            0x%-8x     \n"
379                    "ARM_IDLECT1_REG:          0x%-8x     \n"
380                    "ARM_IDLECT2_REG:          0x%-8x     \n"
381                    "ARM_IDLECT3_REG:          0x%-8x     \n"
382                    "ARM_EWUPCT_REG:           0x%-8x     \n"
383                    "ARM_RSTCT1_REG:           0x%-8x     \n"
384                    "ARM_RSTCT2_REG:           0x%-8x     \n"
385                    "ARM_SYSST_REG:            0x%-8x     \n"
386                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
387                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
388                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
389                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
390                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
391                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
392                    ARM_SHOW(ARM_CKCTL),
393                    ARM_SHOW(ARM_IDLECT1),
394                    ARM_SHOW(ARM_IDLECT2),
395                    ARM_SHOW(ARM_IDLECT3),
396                    ARM_SHOW(ARM_EWUPCT),
397                    ARM_SHOW(ARM_RSTCT1),
398                    ARM_SHOW(ARM_RSTCT2),
399                    ARM_SHOW(ARM_SYSST),
400                    ULPD_SHOW(ULPD_IT_STATUS),
401                    ULPD_SHOW(ULPD_CLOCK_CTRL),
402                    ULPD_SHOW(ULPD_SOFT_REQ),
403                    ULPD_SHOW(ULPD_DPLL_CTRL),
404                    ULPD_SHOW(ULPD_STATUS_REQ),
405                    ULPD_SHOW(ULPD_POWER_CTRL));
406
407                 if (cpu_is_omap1510()) {
408                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
409                            "MPUI1510_CTRL_REG             0x%-8x \n"
410                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
411                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
412                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
413                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
414                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
415                            MPUI1510_SHOW(MPUI_CTRL),
416                            MPUI1510_SHOW(MPUI_DSP_STATUS),
417                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
418                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
419                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
420                            MPUI1510_SHOW(EMIFS_CONFIG));
421                 } else if (cpu_is_omap16xx()) {
422                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
423                            "MPUI1610_CTRL_REG             0x%-8x \n"
424                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
425                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
426                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
427                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
428                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
429                            MPUI1610_SHOW(MPUI_CTRL),
430                            MPUI1610_SHOW(MPUI_DSP_STATUS),
431                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
432                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
433                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
434                            MPUI1610_SHOW(EMIFS_CONFIG));
435                 }
436
437                 g_read_completed++;
438         } else if (g_read_completed >= 1) {
439                  *eof = 1;
440                  return 0;
441         }
442         g_read_completed++;
443
444         *my_first_byte = page_buffer;
445         return  my_buffer_offset;
446 }
447
448 static void omap_pm_init_proc(void)
449 {
450         struct proc_dir_entry *entry;
451
452         entry = create_proc_read_entry("driver/omap_pm",
453                                        S_IWUSR | S_IRUGO, NULL,
454            omap_pm_read_proc, NULL);
455 }
456
457 #endif /* DEBUG && CONFIG_PROC_FS */
458
459 /*
460  *      omap_pm_prepare - Do preliminary suspend work.
461  *      @state:         suspend state we're entering.
462  *
463  */
464 //#include <asm/arch/hardware.h>
465
466 static int omap_pm_prepare(suspend_state_t state)
467 {
468         int error = 0;
469
470         switch (state)
471         {
472         case PM_SUSPEND_STANDBY:
473         case PM_SUSPEND_MEM:
474                 break;
475
476         case PM_SUSPEND_DISK:
477                 return -ENOTSUPP;
478
479         default:
480                 return -EINVAL;
481         }
482
483         return error;
484 }
485
486
487 /*
488  *      omap_pm_enter - Actually enter a sleep state.
489  *      @state:         State we're entering.
490  *
491  */
492
493 static int omap_pm_enter(suspend_state_t state)
494 {
495         switch (state)
496         {
497         case PM_SUSPEND_STANDBY:
498         case PM_SUSPEND_MEM:
499                 omap_pm_suspend();
500                 break;
501
502         case PM_SUSPEND_DISK:
503                 return -ENOTSUPP;
504
505         default:
506                 return -EINVAL;
507         }
508
509         return 0;
510 }
511
512
513 /**
514  *      omap_pm_finish - Finish up suspend sequence.
515  *      @state:         State we're coming out of.
516  *
517  *      This is called after we wake back up (or if entering the sleep state
518  *      failed).
519  */
520
521 static int omap_pm_finish(suspend_state_t state)
522 {
523         return 0;
524 }
525
526
527 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
528                                      struct pt_regs *  regs)
529 {
530         return IRQ_HANDLED;
531 }
532
533 static struct irqaction omap_wakeup_irq = {
534         .name           = "peripheral wakeup",
535         .flags          = SA_INTERRUPT,
536         .handler        = omap_wakeup_interrupt
537 };
538
539
540
541 static struct pm_ops omap_pm_ops ={
542         .pm_disk_mode = 0,
543         .prepare        = omap_pm_prepare,
544         .enter          = omap_pm_enter,
545         .finish         = omap_pm_finish,
546 };
547
548 static int __init omap_pm_init(void)
549 {
550         printk("Power Management for TI OMAP.\n");
551         /*
552          * We copy the assembler sleep/wakeup routines to SRAM.
553          * These routines need to be in SRAM as that's the only
554          * memory the MPU can see when it wakes up.
555          */
556         if (cpu_is_omap1510()) {
557                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
558                                                 omap1510_idle_loop_suspend_sz);
559                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
560                                                    omap1510_cpu_suspend_sz);
561         } else if (cpu_is_omap16xx()) {
562                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
563                                                 omap1610_idle_loop_suspend_sz);
564                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
565                                                    omap1610_cpu_suspend_sz);
566         }
567
568         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
569                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
570                 return -ENODEV;
571         }
572
573         pm_idle = omap_pm_idle;
574
575         setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
576 #if 0
577         /* --- BEGIN BOARD-DEPENDENT CODE --- */
578         /* Sleepx mask direction */
579         omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
580         /* Unmask sleepx signal */
581         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
582         /* --- END BOARD-DEPENDENT CODE --- */
583 #endif
584
585         /* Program new power ramp-up time
586          * (0 for most boards since we don't lower voltage when in deep sleep)
587          */
588         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
589
590         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
591         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
592
593         /* Configure IDLECT3 */
594         if (cpu_is_omap16xx())
595                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
596
597         pm_set_ops(&omap_pm_ops);
598
599 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
600         omap_pm_init_proc();
601 #endif
602
603         /* configure LOW_PWR pin */
604         omap_cfg_reg(T20_1610_LOW_PWR);
605
606         return 0;
607 }
608 __initcall(omap_pm_init);
609