arch/arm/plat-omap/pm.c

   1 /*
   2  * linux/arch/arm/plat-omap/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43
  44 #include <asm/io.h>
  45 #include <asm/irq.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/irq.h>
  48
  49 #include <asm/mach-types.h>
  50 #include <asm/arch/irqs.h>
  51 #include <asm/arch/tc.h>
  52 #include <asm/arch/pm.h>
  53 #include <asm/arch/mux.h>
  54 #include <asm/arch/tps65010.h>
  55 #include <asm/arch/dsp_common.h>
  56
  57 #include <asm/arch/clock.h>
  58 #include <asm/arch/sram.h>
  59
  60 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  61 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  62 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  63 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  64 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  65
  66 static void (*omap_sram_idle)(void) = NULL;
  67 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
  68
  69 /*
  70  * Let's power down on idle, but only if we are really
  71  * idle, because once we start down the path of
  72  * going idle we continue to do idle even if we get
  73  * a clock tick interrupt . .
  74  */
  75 void omap_pm_idle(void)
  76 {
  77         unsigned int mask32 = 0;
  78
  79         /*
  80          * If the DSP is being used let's just idle the CPU, the overhead
  81          * to wake up from Big Sleep is big, milliseconds versus micro
  82          * seconds for wait for interrupt.
  83          */
  84
  85         local_irq_disable();
  86         local_fiq_disable();
  87         if (need_resched()) {
  88                 local_fiq_enable();
  89                 local_irq_enable();
  90                 return;
  91         }
  92         mask32 = omap_readl(ARM_SYSST);
  93
  94         /*
  95          * Prevent the ULPD from entering low power state by setting
  96          * POWER_CTRL_REG:4 = 0
  97          */
  98         omap_writew(omap_readw(ULPD_POWER_CTRL) &
  99                     ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
 100
 101         /*
 102          * Since an interrupt may set up a timer, we don't want to
 103          * reprogram the hardware timer with interrupts enabled.
 104          * Re-enable interrupts only after returning from idle.
 105          */
 106         timer_dyn_reprogram();
 107
 108         if ((mask32 & DSP_IDLE) == 0) {
 109                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 110         } else
 111                 omap_sram_idle();
 112
 113         local_fiq_enable();
 114         local_irq_enable();
 115 }
 116
 117 /*
 118  * Configuration of the wakeup event is board specific. For the
 119  * moment we put it into this helper function. Later it may move
 120  * to board specific files.
 121  */
 122 static void omap_pm_wakeup_setup(void)
 123 {
 124         u32 level1_wake = 0;
 125         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 126
 127         /*
 128          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 129          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 130          * drivers must still separately call omap_set_gpio_wakeup() to
 131          * wake up to a GPIO interrupt.
 132          */
 133         if (cpu_is_omap730())
 134                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 135                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 136         else if (cpu_is_omap1510())
 137                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 138                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 139         else if (cpu_is_omap16xx())
 140                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 141                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 142
 143         omap_writel(~level1_wake, OMAP_IH1_MIR);
 144
 145         if (cpu_is_omap730()) {
 146                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 147                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
 148         } else if (cpu_is_omap1510()) {
 149                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 150                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 151         } else if (cpu_is_omap16xx()) {
 152                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 153                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 154
 155                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 156                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
 157                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 158                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 159         }
 160
 161         /*  New IRQ agreement, recalculate in cascade order */
 162         omap_writel(1, OMAP_IH2_CONTROL);
 163         omap_writel(1, OMAP_IH1_CONTROL);
 164 }
 165
 166 void omap_pm_suspend(void)
 167 {
 168         unsigned long arg0 = 0, arg1 = 0;
 169
 170         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 171
 172         omap_serial_wake_trigger(1);
 173
 174         if (machine_is_omap_osk()) {
 175                 /* Stop LED1 (D9) blink */
 176                 tps65010_set_led(LED1, OFF);
 177         }
 178
 179         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 180
 181         /*
 182          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 183          */
 184
 185         local_irq_disable();
 186         local_fiq_disable();
 187
 188         /*
 189          * Step 2: save registers
 190          *
 191          * The omap is a strange/beautiful device. The caches, memory
 192          * and register state are preserved across power saves.
 193          * We have to save and restore very little register state to
 194          * idle the omap.
 195          *
 196          * Save interrupt, MPUI, ARM and UPLD control registers.
 197          */
 198
 199         if (cpu_is_omap730()) {
 200                 MPUI730_SAVE(OMAP_IH1_MIR);
 201                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 202                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 203                 MPUI730_SAVE(MPUI_CTRL);
 204                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 205                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 206                 MPUI730_SAVE(EMIFS_CONFIG);
 207                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 208
 209         } else if (cpu_is_omap1510()) {
 210                 MPUI1510_SAVE(OMAP_IH1_MIR);
 211                 MPUI1510_SAVE(OMAP_IH2_MIR);
 212                 MPUI1510_SAVE(MPUI_CTRL);
 213                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 214                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 215                 MPUI1510_SAVE(EMIFS_CONFIG);
 216                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 217         } else if (cpu_is_omap16xx()) {
 218                 MPUI1610_SAVE(OMAP_IH1_MIR);
 219                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 220                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 221                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 222                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 223                 MPUI1610_SAVE(MPUI_CTRL);
 224                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 225                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 226                 MPUI1610_SAVE(EMIFS_CONFIG);
 227                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 228         }
 229
 230         ARM_SAVE(ARM_CKCTL);
 231         ARM_SAVE(ARM_IDLECT1);
 232         ARM_SAVE(ARM_IDLECT2);
 233         if (!(cpu_is_omap1510()))
 234                 ARM_SAVE(ARM_IDLECT3);
 235         ARM_SAVE(ARM_EWUPCT);
 236         ARM_SAVE(ARM_RSTCT1);
 237         ARM_SAVE(ARM_RSTCT2);
 238         ARM_SAVE(ARM_SYSST);
 239         ULPD_SAVE(ULPD_CLOCK_CTRL);
 240         ULPD_SAVE(ULPD_STATUS_REQ);
 241
 242         /* (Step 3 removed - we now allow deep sleep by default) */
 243
 244         /*
 245          * Step 4: OMAP DSP Shutdown
 246          */
 247
 248         omap_dsp_pm_suspend();
 249
 250         /*
 251          * Step 5: Wakeup Event Setup
 252          */
 253
 254         omap_pm_wakeup_setup();
 255
 256         /*
 257          * Step 6: ARM and Traffic controller shutdown
 258          */
 259
 260         /* disable ARM watchdog */
 261         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 262         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 263
 264         /*
 265          * Step 6b: ARM and Traffic controller shutdown
 266          *
 267          * Step 6 continues here. Prepare jump to power management
 268          * assembly code in internal SRAM.
 269          *
 270          * Since the omap_cpu_suspend routine has been copied to
 271          * SRAM, we'll do an indirect procedure call to it and pass the
 272          * contents of arm_idlect1 and arm_idlect2 so it can restore
 273          * them when it wakes up and it will return.
 274          */
 275
 276         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 277         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 278
 279         /*
 280          * Step 6c: ARM and Traffic controller shutdown
 281          *
 282          * Jump to assembly code. The processor will stay there
 283          * until wake up.
 284          */
 285         omap_sram_suspend(arg0, arg1);
 286
 287         /*
 288          * If we are here, processor is woken up!
 289          */
 290
 291         /* Restore DSP clocks */
 292         omap_dsp_pm_resume();
 293
 294         /*
 295          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 296          */
 297
 298         if (!(cpu_is_omap1510()))
 299                 ARM_RESTORE(ARM_IDLECT3);
 300         ARM_RESTORE(ARM_CKCTL);
 301         ARM_RESTORE(ARM_EWUPCT);
 302         ARM_RESTORE(ARM_RSTCT1);
 303         ARM_RESTORE(ARM_RSTCT2);
 304         ARM_RESTORE(ARM_SYSST);
 305         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 306         ULPD_RESTORE(ULPD_STATUS_REQ);
 307
 308         if (cpu_is_omap730()) {
 309                 MPUI730_RESTORE(EMIFS_CONFIG);
 310                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 311                 MPUI730_RESTORE(OMAP_IH1_MIR);
 312                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 313                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 314         } else if (cpu_is_omap1510()) {
 315                 MPUI1510_RESTORE(MPUI_CTRL);
 316                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 317                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 318                 MPUI1510_RESTORE(EMIFS_CONFIG);
 319                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 320                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 321                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 322         } else if (cpu_is_omap16xx()) {
 323                 MPUI1610_RESTORE(MPUI_CTRL);
 324                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 325                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 326                 MPUI1610_RESTORE(EMIFS_CONFIG);
 327                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 328
 329                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 330                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 331                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 332                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 333                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 334         }
 335
 336         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 337
 338         /*
 339          * Reenable interrupts
 340          */
 341
 342         local_irq_enable();
 343         local_fiq_enable();
 344
 345         omap_serial_wake_trigger(0);
 346
 347         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 348
 349         if (machine_is_omap_osk()) {
 350                 /* Let LED1 (D9) blink again */
 351                 tps65010_set_led(LED1, BLINK);
 352         }
 353 }
 354
 355 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 356 static int g_read_completed;
 357
 358 /*
 359  * Read system PM registers for debugging
 360  */
 361 static int omap_pm_read_proc(
 362         char *page_buffer,
 363         char **my_first_byte,
 364         off_t virtual_start,
 365         int length,
 366         int *eof,
 367         void *data)
 368 {
 369         int my_buffer_offset = 0;
 370         char * const my_base = page_buffer;
 371
 372         ARM_SAVE(ARM_CKCTL);
 373         ARM_SAVE(ARM_IDLECT1);
 374         ARM_SAVE(ARM_IDLECT2);
 375         if (!(cpu_is_omap1510()))
 376                 ARM_SAVE(ARM_IDLECT3);
 377         ARM_SAVE(ARM_EWUPCT);
 378         ARM_SAVE(ARM_RSTCT1);
 379         ARM_SAVE(ARM_RSTCT2);
 380         ARM_SAVE(ARM_SYSST);
 381
 382         ULPD_SAVE(ULPD_IT_STATUS);
 383         ULPD_SAVE(ULPD_CLOCK_CTRL);
 384         ULPD_SAVE(ULPD_SOFT_REQ);
 385         ULPD_SAVE(ULPD_STATUS_REQ);
 386         ULPD_SAVE(ULPD_DPLL_CTRL);
 387         ULPD_SAVE(ULPD_POWER_CTRL);
 388
 389         if (cpu_is_omap730()) {
 390                 MPUI730_SAVE(MPUI_CTRL);
 391                 MPUI730_SAVE(MPUI_DSP_STATUS);
 392                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 393                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 394                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 395                 MPUI730_SAVE(EMIFS_CONFIG);
 396         } else if (cpu_is_omap1510()) {
 397                 MPUI1510_SAVE(MPUI_CTRL);
 398                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 399                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 400                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 401                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 402                 MPUI1510_SAVE(EMIFS_CONFIG);
 403         } else if (cpu_is_omap16xx()) {
 404                 MPUI1610_SAVE(MPUI_CTRL);
 405                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 406                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 407                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 408                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 409                 MPUI1610_SAVE(EMIFS_CONFIG);
 410         }
 411
 412         if (virtual_start == 0) {
 413                 g_read_completed = 0;
 414
 415                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 416                    "ARM_CKCTL_REG:            0x%-8x     \n"
 417                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 418                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 419                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 420                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 421                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 422                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 423                    "ARM_SYSST_REG:            0x%-8x     \n"
 424                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 425                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 426                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 427                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 428                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 429                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 430                    ARM_SHOW(ARM_CKCTL),
 431                    ARM_SHOW(ARM_IDLECT1),
 432                    ARM_SHOW(ARM_IDLECT2),
 433                    ARM_SHOW(ARM_IDLECT3),
 434                    ARM_SHOW(ARM_EWUPCT),
 435                    ARM_SHOW(ARM_RSTCT1),
 436                    ARM_SHOW(ARM_RSTCT2),
 437                    ARM_SHOW(ARM_SYSST),
 438                    ULPD_SHOW(ULPD_IT_STATUS),
 439                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 440                    ULPD_SHOW(ULPD_SOFT_REQ),
 441                    ULPD_SHOW(ULPD_DPLL_CTRL),
 442                    ULPD_SHOW(ULPD_STATUS_REQ),
 443                    ULPD_SHOW(ULPD_POWER_CTRL));
 444
 445                 if (cpu_is_omap730()) {
 446                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 447                            "MPUI730_CTRL_REG         0x%-8x \n"
 448                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 449                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 450          "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 451          "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 452          "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 453          MPUI730_SHOW(MPUI_CTRL),
 454          MPUI730_SHOW(MPUI_DSP_STATUS),
 455          MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 456          MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 457          MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 458          MPUI730_SHOW(EMIFS_CONFIG));
 459                 } else if (cpu_is_omap1510()) {
 460                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 461                            "MPUI1510_CTRL_REG             0x%-8x \n"
 462                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 463                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 464                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 465                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 466                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 467                            MPUI1510_SHOW(MPUI_CTRL),
 468                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 469                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 470                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 471                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 472                            MPUI1510_SHOW(EMIFS_CONFIG));
 473                 } else if (cpu_is_omap16xx()) {
 474                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 475                            "MPUI1610_CTRL_REG             0x%-8x \n"
 476                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 477                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 478                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 479                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 480                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 481                            MPUI1610_SHOW(MPUI_CTRL),
 482                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 483                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 484                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 485                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 486                            MPUI1610_SHOW(EMIFS_CONFIG));
 487                 }
 488
 489                 g_read_completed++;
 490         } else if (g_read_completed >= 1) {
 491                  *eof = 1;
 492                  return 0;
 493         }
 494         g_read_completed++;
 495
 496         *my_first_byte = page_buffer;
 497         return  my_buffer_offset;
 498 }
 499
 500 static void omap_pm_init_proc(void)
 501 {
 502         struct proc_dir_entry *entry;
 503
 504         entry = create_proc_read_entry("driver/omap_pm",
 505                                        S_IWUSR | S_IRUGO, NULL,
 506            omap_pm_read_proc, NULL);
 507 }
 508
 509 #endif /* DEBUG && CONFIG_PROC_FS */
 510
 511 /*
 512  *      omap_pm_prepare - Do preliminary suspend work.
 513  *      @state:         suspend state we're entering.
 514  *
 515  */
 516 //#include <asm/arch/hardware.h>
 517
 518 static int omap_pm_prepare(suspend_state_t state)
 519 {
 520         int error = 0;
 521
 522         switch (state)
 523         {
 524         case PM_SUSPEND_STANDBY:
 525         case PM_SUSPEND_MEM:
 526                 break;
 527
 528         case PM_SUSPEND_DISK:
 529                 return -ENOTSUPP;
 530
 531         default:
 532                 return -EINVAL;
 533         }
 534
 535         return error;
 536 }
 537
 538
 539 /*
 540  *      omap_pm_enter - Actually enter a sleep state.
 541  *      @state:         State we're entering.
 542  *
 543  */
 544
 545 static int omap_pm_enter(suspend_state_t state)
 546 {
 547         switch (state)
 548         {
 549         case PM_SUSPEND_STANDBY:
 550         case PM_SUSPEND_MEM:
 551                 omap_pm_suspend();
 552                 break;
 553
 554         case PM_SUSPEND_DISK:
 555                 return -ENOTSUPP;
 556
 557         default:
 558                 return -EINVAL;
 559         }
 560
 561         return 0;
 562 }
 563
 564
 565 /**
 566  *      omap_pm_finish - Finish up suspend sequence.
 567  *      @state:         State we're coming out of.
 568  *
 569  *      This is called after we wake back up (or if entering the sleep state
 570  *      failed).
 571  */
 572
 573 static int omap_pm_finish(suspend_state_t state)
 574 {
 575         return 0;
 576 }
 577
 578
 579 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
 580                                      struct pt_regs *  regs)
 581 {
 582         return IRQ_HANDLED;
 583 }
 584
 585 static struct irqaction omap_wakeup_irq = {
 586         .name           = "peripheral wakeup",
 587         .flags          = SA_INTERRUPT,
 588         .handler        = omap_wakeup_interrupt
 589 };
 590
 591
 592
 593 static struct pm_ops omap_pm_ops ={
 594         .pm_disk_mode = 0,
 595         .prepare        = omap_pm_prepare,
 596         .enter          = omap_pm_enter,
 597         .finish         = omap_pm_finish,
 598 };
 599
 600 static int __init omap_pm_init(void)
 601 {
 602         printk("Power Management for TI OMAP.\n");
 603         /*
 604          * We copy the assembler sleep/wakeup routines to SRAM.
 605          * These routines need to be in SRAM as that's the only
 606          * memory the MPU can see when it wakes up.
 607          */
 608         if (cpu_is_omap730()) {
 609                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 610                                                 omap730_idle_loop_suspend_sz);
 611                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 612          omap730_cpu_suspend_sz);
 613         } else if (cpu_is_omap1510()) {
 614                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 615                                                 omap1510_idle_loop_suspend_sz);
 616                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 617                                                    omap1510_cpu_suspend_sz);
 618         } else if (cpu_is_omap16xx()) {
 619                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 620                                                 omap1610_idle_loop_suspend_sz);
 621                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 622                                                    omap1610_cpu_suspend_sz);
 623         }
 624
 625         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 626                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 627                 return -ENODEV;
 628         }
 629
 630         pm_idle = omap_pm_idle;
 631
 632         if (cpu_is_omap730())
 633                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 634         else if (cpu_is_omap16xx())
 635                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 636
 637 #if 0
 638         /* --- BEGIN BOARD-DEPENDENT CODE --- */
 639         /* Sleepx mask direction */
 640         omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
 641         /* Unmask sleepx signal */
 642         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 643         /* --- END BOARD-DEPENDENT CODE --- */
 644 #endif
 645
 646         /* Program new power ramp-up time
 647          * (0 for most boards since we don't lower voltage when in deep sleep)
 648          */
 649         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 650
 651         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 652         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 653
 654         /* Configure IDLECT3 */
 655         if (cpu_is_omap730())
 656                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 657         else if (cpu_is_omap16xx())
 658                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 659
 660         pm_set_ops(&omap_pm_ops);
 661
 662 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 663         omap_pm_init_proc();
 664 #endif
 665
 666         if (cpu_is_omap16xx()) {
 667                 /* configure LOW_PWR pin */
 668                 omap_cfg_reg(T20_1610_LOW_PWR);
 669         }
 670
 671         return 0;
 672 }
 673 __initcall(omap_pm_init);
 674