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Runtime constants: use runtime-computed system control module base
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1 /*
2  * linux/arch/arm/plat-omap/mux.c
3  *
4  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
5  *
6  * Copyright (C) 2003 - 2005 Nokia Corporation
7  *
8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23  *
24  */
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <asm/system.h>
29 #include <asm/io.h>
30 #include <linux/spinlock.h>
31 #include <asm/arch/mux.h>
32
33 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
34 # include "../mach-omap2/control.h"
35 #endif
36
37 #ifdef CONFIG_OMAP_MUX
38
39 #define OMAP24XX_PULL_ENA       (1 << 3)
40 #define OMAP24XX_PULL_UP        (1 << 4)
41
42 static struct pin_config * pin_table;
43 static unsigned long pin_table_sz;
44
45 extern struct pin_config * omap730_pins;
46 extern struct pin_config * omap1xxx_pins;
47 extern struct pin_config * omap24xx_pins;
48
49 int __init omap_mux_register(struct pin_config * pins, unsigned long size)
50 {
51         pin_table = pins;
52         pin_table_sz = size;
53
54         return 0;
55 }
56
57 /*
58  * Sets the Omap MUX and PULL_DWN registers based on the table
59  */
60 int __init_or_module omap_cfg_reg(const unsigned long index)
61 {
62         static DEFINE_SPINLOCK(mux_spin_lock);
63
64         unsigned long flags;
65         struct pin_config *cfg;
66         unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
67                 pull_orig = 0, pull = 0;
68         unsigned int mask, warn = 0;
69
70         if (!pin_table)
71                 BUG();
72
73         if (index >= pin_table_sz) {
74                 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
75                        index, pin_table_sz);
76                 dump_stack();
77                 return -ENODEV;
78         }
79
80         cfg = (struct pin_config *)&pin_table[index];
81 #ifdef CONFIG_ARCH_OMAP24XX
82         /* REVISIT: Convert this code to use ctrl_{read,write}_reg */
83         if (cpu_is_omap24xx()) {
84                 u8 reg = 0;
85
86                 reg |= cfg->mask & 0x7;
87                 if (cfg->pull_val)
88                         reg |= OMAP24XX_PULL_ENA;
89                 if(cfg->pu_pd_val)
90                         reg |= OMAP24XX_PULL_UP;
91 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
92                 {
93                         u8 orig = omap_readb(omap2_ctrl_base + cfg->mux_reg);
94                         u8 debug = 0;
95
96 #ifdef  CONFIG_OMAP_MUX_DEBUG
97                         debug = cfg->debug;
98 #endif
99                         warn = (orig != reg);
100                         if (debug || warn)
101                                 printk("MUX: setup %s (0x%08lx): 0x%02x -> 0x%02x\n",
102                                                 cfg->name,
103                                                 omap2_ctrl_base + cfg->mux_reg,
104                                                 orig, reg);
105                 }
106 #endif
107                 omap_writeb(reg, omap2_ctrl_base + cfg->mux_reg);
108
109                 return 0;
110         }
111 #endif /* ARCH_OMAP24XX */
112
113         /* Check the mux register in question */
114         if (cfg->mux_reg) {
115                 unsigned        tmp1, tmp2;
116
117                 spin_lock_irqsave(&mux_spin_lock, flags);
118                 reg_orig = omap_readl(cfg->mux_reg);
119
120                 /* The mux registers always seem to be 3 bits long */
121                 mask = (0x7 << cfg->mask_offset);
122                 tmp1 = reg_orig & mask;
123                 reg = reg_orig & ~mask;
124
125                 tmp2 = (cfg->mask << cfg->mask_offset);
126                 reg |= tmp2;
127
128                 if (tmp1 != tmp2)
129                         warn = 1;
130
131                 omap_writel(reg, cfg->mux_reg);
132                 spin_unlock_irqrestore(&mux_spin_lock, flags);
133         }
134
135         /* Check for pull up or pull down selection on 1610 */
136         if (!cpu_is_omap15xx()) {
137                 if (cfg->pu_pd_reg && cfg->pull_val) {
138                         spin_lock_irqsave(&mux_spin_lock, flags);
139                         pu_pd_orig = omap_readl(cfg->pu_pd_reg);
140                         mask = 1 << cfg->pull_bit;
141
142                         if (cfg->pu_pd_val) {
143                                 if (!(pu_pd_orig & mask))
144                                         warn = 1;
145                                 /* Use pull up */
146                                 pu_pd = pu_pd_orig | mask;
147                         } else {
148                                 if (pu_pd_orig & mask)
149                                         warn = 1;
150                                 /* Use pull down */
151                                 pu_pd = pu_pd_orig & ~mask;
152                         }
153                         omap_writel(pu_pd, cfg->pu_pd_reg);
154                         spin_unlock_irqrestore(&mux_spin_lock, flags);
155                 }
156         }
157
158         /* Check for an associated pull down register */
159         if (cfg->pull_reg) {
160                 spin_lock_irqsave(&mux_spin_lock, flags);
161                 pull_orig = omap_readl(cfg->pull_reg);
162                 mask = 1 << cfg->pull_bit;
163
164                 if (cfg->pull_val) {
165                         if (pull_orig & mask)
166                                 warn = 1;
167                         /* Low bit = pull enabled */
168                         pull = pull_orig & ~mask;
169                 } else {
170                         if (!(pull_orig & mask))
171                                 warn = 1;
172                         /* High bit = pull disabled */
173                         pull = pull_orig | mask;
174                 }
175
176                 omap_writel(pull, cfg->pull_reg);
177                 spin_unlock_irqrestore(&mux_spin_lock, flags);
178         }
179
180         if (warn) {
181 #ifdef CONFIG_OMAP_MUX_WARNINGS
182                 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
183 #endif
184         }
185
186 #ifdef CONFIG_OMAP_MUX_DEBUG
187         if (cfg->debug || warn) {
188                 printk("MUX: Setting register %s\n", cfg->name);
189                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
190                        cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
191
192                 if (!cpu_is_omap15xx()) {
193                         if (cfg->pu_pd_reg && cfg->pull_val) {
194                                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
195                                        cfg->pu_pd_name, cfg->pu_pd_reg,
196                                        pu_pd_orig, pu_pd);
197                         }
198                 }
199
200                 if (cfg->pull_reg)
201                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
202                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
203         }
204 #endif
205
206 #ifdef CONFIG_OMAP_MUX_ERRORS
207         return warn ? -ETXTBSY : 0;
208 #else
209         return 0;
210 #endif
211 }
212 EXPORT_SYMBOL(omap_cfg_reg);
213 #else
214 #define omap_mux_init() do {} while(0)
215 #define omap_cfg_reg(x) do {} while(0)
216 #endif  /* CONFIG_OMAP_MUX */