arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22
  23 #include <asm/delay.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26
  27 #include <asm/arch/dma.h>
  28 #include <asm/arch/mux.h>
  29 #include <asm/arch/irqs.h>
  30 #include <asm/arch/dsp_common.h>
  31 #include <asm/arch/mcbsp.h>
  32
  33 #include <asm/hardware/clock.h>
  34
  35 #ifdef CONFIG_MCBSP_DEBUG
  36 #define DBG(x...)       printk(x)
  37 #else
  38 #define DBG(x...)       do { } while (0)
  39 #endif
  40
  41 struct omap_mcbsp {
  42         u32                          io_base;
  43         u8                           id;
  44         u8                           free;
  45         omap_mcbsp_word_length       rx_word_length;
  46         omap_mcbsp_word_length       tx_word_length;
  47
  48         /* IRQ based TX/RX */
  49         int                          rx_irq;
  50         int                          tx_irq;
  51
  52         /* DMA stuff */
  53         u8                           dma_rx_sync;
  54         short                        dma_rx_lch;
  55         u8                           dma_tx_sync;
  56         short                        dma_tx_lch;
  57
  58         /* Completion queues */
  59         struct completion            tx_irq_completion;
  60         struct completion            rx_irq_completion;
  61         struct completion            tx_dma_completion;
  62         struct completion            rx_dma_completion;
  63
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 static struct clk *mcbsp_dsp_ck = 0;
  69 static struct clk *mcbsp_api_ck = 0;
  70 static struct clk *mcbsp_dspxor_ck = 0;
  71
  72
  73 static void omap_mcbsp_dump_reg(u8 id)
  74 {
  75         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  76         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  77         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  78         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  79         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  80         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  81         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  82         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  83         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  84         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  85         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  86         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  87         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  88         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  89         DBG("***********************\n");
  90 }
  91
  92
  93 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
  94 {
  95         struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
  96
  97         DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
  98
  99         complete(&mcbsp_tx->tx_irq_completion);
 100         return IRQ_HANDLED;
 101 }
 102
 103 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 104 {
 105         struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
 106
 107         DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 108
 109         complete(&mcbsp_rx->rx_irq_completion);
 110         return IRQ_HANDLED;
 111 }
 112
 113
 114 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 115 {
 116         struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
 117
 118         DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 119
 120         /* We can free the channels */
 121         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 122         mcbsp_dma_tx->dma_tx_lch = -1;
 123
 124         complete(&mcbsp_dma_tx->tx_dma_completion);
 125 }
 126
 127 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 128 {
 129         struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
 130
 131         DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 132
 133         /* We can free the channels */
 134         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 135         mcbsp_dma_rx->dma_rx_lch = -1;
 136
 137         complete(&mcbsp_dma_rx->rx_dma_completion);
 138 }
 139
 140
 141 /*
 142  * omap_mcbsp_config simply write a config to the
 143  * appropriate McBSP.
 144  * You either call this function or set the McBSP registers
 145  * by yourself before calling omap_mcbsp_start().
 146  */
 147
 148 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
 149 {
 150         u32 io_base = mcbsp[id].io_base;
 151
 152         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
 153
 154         /* We write the given config */
 155         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 156         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 157         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 158         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 159         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 160         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 161         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 162         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 163         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 164         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 165         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 166 }
 167
 168
 169
 170 static int omap_mcbsp_check(unsigned int id)
 171 {
 172         if (cpu_is_omap730()) {
 173                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 174                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 175                        return -1;
 176                 }
 177                 return 0;
 178         }
 179
 180         if (cpu_is_omap1510() || cpu_is_omap16xx()) {
 181                 if (id > OMAP_MAX_MCBSP_COUNT) {
 182                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 183                         return -1;
 184                 }
 185                 return 0;
 186         }
 187
 188         return -1;
 189 }
 190
 191 static void omap_mcbsp_dsp_request(void)
 192 {
 193         if (cpu_is_omap1510() || cpu_is_omap16xx()) {
 194                 omap_dsp_request_mem();
 195                 clk_use(mcbsp_dsp_ck);
 196                 clk_use(mcbsp_api_ck);
 197
 198                 /* enable 12MHz clock to mcbsp 1 & 3 */
 199                 clk_use(mcbsp_dspxor_ck);
 200
 201                 /*
 202                  * DSP external peripheral reset
 203                  * FIXME: This should be moved to dsp code
 204                  */
 205                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 206                              DSP_RSTCT2);
 207         }
 208 }
 209
 210 static void omap_mcbsp_dsp_free(void)
 211 {
 212         if (cpu_is_omap1510() || cpu_is_omap16xx()) {
 213                 omap_dsp_release_mem();
 214                 clk_unuse(mcbsp_dspxor_ck);
 215                 clk_unuse(mcbsp_dsp_ck);
 216                 clk_unuse(mcbsp_api_ck);
 217         }
 218 }
 219
 220 int omap_mcbsp_request(unsigned int id)
 221 {
 222         int err;
 223
 224         if (omap_mcbsp_check(id) < 0)
 225                 return -EINVAL;
 226
 227         /*
 228          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 229          * are DSP public peripherals.
 230          */
 231         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 232                 omap_mcbsp_dsp_request();
 233
 234         spin_lock(&mcbsp[id].lock);
 235         if (!mcbsp[id].free) {
 236                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 237                 spin_unlock(&mcbsp[id].lock);
 238                 return -1;
 239         }
 240
 241         mcbsp[id].free = 0;
 242         spin_unlock(&mcbsp[id].lock);
 243
 244         /* We need to get IRQs here */
 245         err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
 246                           "McBSP",
 247                           (void *) (&mcbsp[id]));
 248         if (err != 0) {
 249                 printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
 250                        mcbsp[id].tx_irq, mcbsp[id].id);
 251                 return err;
 252         }
 253
 254         init_completion(&(mcbsp[id].tx_irq_completion));
 255
 256
 257         err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
 258                           "McBSP",
 259                           (void *) (&mcbsp[id]));
 260         if (err != 0) {
 261                 printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
 262                        mcbsp[id].rx_irq, mcbsp[id].id);
 263                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 264                 return err;
 265         }
 266
 267         init_completion(&(mcbsp[id].rx_irq_completion));
 268         return 0;
 269
 270 }
 271
 272 void omap_mcbsp_free(unsigned int id)
 273 {
 274         if (omap_mcbsp_check(id) < 0)
 275                 return;
 276
 277         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 278                 omap_mcbsp_dsp_free();
 279
 280         spin_lock(&mcbsp[id].lock);
 281         if (mcbsp[id].free) {
 282                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
 283                 spin_unlock(&mcbsp[id].lock);
 284                 return;
 285         }
 286
 287         mcbsp[id].free = 1;
 288         spin_unlock(&mcbsp[id].lock);
 289
 290         /* Free IRQs */
 291         free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 292         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 293 }
 294
 295 /*
 296  * Here we start the McBSP, by enabling the sample
 297  * generator, both transmitter and receivers,
 298  * and the frame sync.
 299  */
 300 void omap_mcbsp_start(unsigned int id)
 301 {
 302         u32 io_base;
 303         u16 w;
 304
 305         if (omap_mcbsp_check(id) < 0)
 306                 return;
 307
 308         io_base = mcbsp[id].io_base;
 309
 310         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
 311         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
 312
 313         /* Start the sample generator */
 314         w = OMAP_MCBSP_READ(io_base, SPCR2);
 315         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 316
 317         /* Enable transmitter and receiver */
 318         w = OMAP_MCBSP_READ(io_base, SPCR2);
 319         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 320
 321         w = OMAP_MCBSP_READ(io_base, SPCR1);
 322         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 323
 324         udelay(100);
 325
 326         /* Start frame sync */
 327         w = OMAP_MCBSP_READ(io_base, SPCR2);
 328         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 329
 330         /* Dump McBSP Regs */
 331         omap_mcbsp_dump_reg(id);
 332
 333 }
 334
 335 void omap_mcbsp_stop(unsigned int id)
 336 {
 337         u32 io_base;
 338         u16 w;
 339
 340         if (omap_mcbsp_check(id) < 0)
 341                 return;
 342
 343         io_base = mcbsp[id].io_base;
 344
 345         /* Reset transmitter */
 346         w = OMAP_MCBSP_READ(io_base, SPCR2);
 347         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 348
 349         /* Reset receiver */
 350         w = OMAP_MCBSP_READ(io_base, SPCR1);
 351         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 352
 353         /* Reset the sample rate generator */
 354         w = OMAP_MCBSP_READ(io_base, SPCR2);
 355         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 356 }
 357
 358
 359 /* polled mcbsp i/o operations */
 360 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 361 {
 362         u32 base = mcbsp[id].io_base;
 363         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 364         /* if frame sync error - clear the error */
 365         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 366                 /* clear error */
 367                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 368                        base + OMAP_MCBSP_REG_SPCR2);
 369                 /* resend */
 370                 return -1;
 371         } else {
 372                 /* wait for transmit confirmation */
 373                 int attemps = 0;
 374                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 375                         if (attemps++ > 1000) {
 376                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 377                                        (~XRST),
 378                                        base + OMAP_MCBSP_REG_SPCR2);
 379                                 udelay(10);
 380                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 381                                        (XRST),
 382                                        base + OMAP_MCBSP_REG_SPCR2);
 383                                 udelay(10);
 384                                 printk(KERN_ERR
 385                                        " Could not write to McBSP Register\n");
 386                                 return -2;
 387                         }
 388                 }
 389         }
 390         return 0;
 391 }
 392
 393 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 394 {
 395         u32 base = mcbsp[id].io_base;
 396         /* if frame sync error - clear the error */
 397         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 398                 /* clear error */
 399                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 400                        base + OMAP_MCBSP_REG_SPCR1);
 401                 /* resend */
 402                 return -1;
 403         } else {
 404                 /* wait for recieve confirmation */
 405                 int attemps = 0;
 406                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 407                         if (attemps++ > 1000) {
 408                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 409                                        (~RRST),
 410                                        base + OMAP_MCBSP_REG_SPCR1);
 411                                 udelay(10);
 412                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 413                                        (RRST),
 414                                        base + OMAP_MCBSP_REG_SPCR1);
 415                                 udelay(10);
 416                                 printk(KERN_ERR
 417                                        " Could not read from McBSP Register\n");
 418                                 return -2;
 419                         }
 420                 }
 421         }
 422         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 423         return 0;
 424 }
 425
 426 /*
 427  * IRQ based word transmission.
 428  */
 429 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 430 {
 431         u32 io_base;
 432         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 433
 434         if (omap_mcbsp_check(id) < 0)
 435                 return;
 436
 437         io_base = mcbsp[id].io_base;
 438
 439         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 440
 441         if (word_length > OMAP_MCBSP_WORD_16)
 442                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 443         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 444 }
 445
 446 u32 omap_mcbsp_recv_word(unsigned int id)
 447 {
 448         u32 io_base;
 449         u16 word_lsb, word_msb = 0;
 450         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 451
 452         if (omap_mcbsp_check(id) < 0)
 453                 return -EINVAL;
 454
 455         io_base = mcbsp[id].io_base;
 456
 457         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 458
 459         if (word_length > OMAP_MCBSP_WORD_16)
 460                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 461         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 462
 463         return (word_lsb | (word_msb << 16));
 464 }
 465
 466
 467 /*
 468  * Simple DMA based buffer rx/tx routines.
 469  * Nothing fancy, just a single buffer tx/rx through DMA.
 470  * The DMA resources are released once the transfer is done.
 471  * For anything fancier, you should use your own customized DMA
 472  * routines and callbacks.
 473  */
 474 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 475 {
 476         int dma_tx_ch;
 477
 478         if (omap_mcbsp_check(id) < 0)
 479                 return -EINVAL;
 480
 481         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
 482                              &mcbsp[id],
 483                              &dma_tx_ch)) {
 484                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
 485                 return -EAGAIN;
 486         }
 487         mcbsp[id].dma_tx_lch = dma_tx_ch;
 488
 489         DBG("TX DMA on channel %d\n", dma_tx_ch);
 490
 491         init_completion(&(mcbsp[id].tx_dma_completion));
 492
 493         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 494                                      OMAP_DMA_DATA_TYPE_S16,
 495                                      length >> 1, 1,
 496                                      OMAP_DMA_SYNC_ELEMENT,
 497                                      0, 0);
 498
 499         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 500                                  OMAP_DMA_PORT_TIPB,
 501                                  OMAP_DMA_AMODE_CONSTANT,
 502                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 503                                  0, 0);
 504
 505         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 506                                 OMAP_DMA_PORT_EMIFF,
 507                                 OMAP_DMA_AMODE_POST_INC,
 508                                 buffer,
 509                                 0, 0);
 510
 511         omap_start_dma(mcbsp[id].dma_tx_lch);
 512         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 513         return 0;
 514 }
 515
 516
 517 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 518 {
 519         int dma_rx_ch;
 520
 521         if (omap_mcbsp_check(id) < 0)
 522                 return -EINVAL;
 523
 524         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
 525                              &mcbsp[id],
 526                              &dma_rx_ch)) {
 527                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
 528                 return -EAGAIN;
 529         }
 530         mcbsp[id].dma_rx_lch = dma_rx_ch;
 531
 532         DBG("RX DMA on channel %d\n", dma_rx_ch);
 533
 534         init_completion(&(mcbsp[id].rx_dma_completion));
 535
 536         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 537                                      OMAP_DMA_DATA_TYPE_S16,
 538                                      length >> 1, 1,
 539                                      OMAP_DMA_SYNC_ELEMENT,
 540                                      0, 0);
 541
 542         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 543                                 OMAP_DMA_PORT_TIPB,
 544                                 OMAP_DMA_AMODE_CONSTANT,
 545                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 546                                 0, 0);
 547
 548         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 549                                  OMAP_DMA_PORT_EMIFF,
 550                                  OMAP_DMA_AMODE_POST_INC,
 551                                  buffer,
 552                                  0, 0);
 553
 554         omap_start_dma(mcbsp[id].dma_rx_lch);
 555         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 556         return 0;
 557 }
 558
 559
 560 /*
 561  * SPI wrapper.
 562  * Since SPI setup is much simpler than the generic McBSP one,
 563  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 564  * Once this is done, you can call omap_mcbsp_start().
 565  */
 566 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
 567 {
 568         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 569
 570         if (omap_mcbsp_check(id) < 0)
 571                 return;
 572
 573         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 574
 575         /* SPI has only one frame */
 576         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 577         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 578
 579         /* Clock stop mode */
 580         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 581                 mcbsp_cfg.spcr1 |= (1 << 12);
 582         else
 583                 mcbsp_cfg.spcr1 |= (3 << 11);
 584
 585         /* Set clock parities */
 586         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 587                 mcbsp_cfg.pcr0 |= CLKRP;
 588         else
 589                 mcbsp_cfg.pcr0 &= ~CLKRP;
 590
 591         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 592                 mcbsp_cfg.pcr0 &= ~CLKXP;
 593         else
 594                 mcbsp_cfg.pcr0 |= CLKXP;
 595
 596         /* Set SCLKME to 0 and CLKSM to 1 */
 597         mcbsp_cfg.pcr0 &= ~SCLKME;
 598         mcbsp_cfg.srgr2 |= CLKSM;
 599
 600         /* Set FSXP */
 601         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 602                 mcbsp_cfg.pcr0 &= ~FSXP;
 603         else
 604                 mcbsp_cfg.pcr0 |= FSXP;
 605
 606         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 607                 mcbsp_cfg.pcr0 |= CLKXM;
 608                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
 609                 mcbsp_cfg.pcr0 |= FSXM;
 610                 mcbsp_cfg.srgr2 &= ~FSGM;
 611                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 612                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 613         }
 614         else {
 615                 mcbsp_cfg.pcr0 &= ~CLKXM;
 616                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 617                 mcbsp_cfg.pcr0 &= ~FSXM;
 618                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 619                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 620         }
 621
 622         mcbsp_cfg.xcr2 &= ~XPHASE;
 623         mcbsp_cfg.rcr2 &= ~RPHASE;
 624
 625         omap_mcbsp_config(id, &mcbsp_cfg);
 626 }
 627
 628
 629 /*
 630  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 631  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 632  */
 633 struct omap_mcbsp_info {
 634         u32 virt_base;
 635         u8 dma_rx_sync, dma_tx_sync;
 636         u16 rx_irq, tx_irq;
 637 };
 638
 639 #ifdef CONFIG_ARCH_OMAP730
 640 static const struct omap_mcbsp_info mcbsp_730[] = {
 641         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 642                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 643                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 644                 .rx_irq = INT_730_McBSP1RX,
 645                 .tx_irq = INT_730_McBSP1TX },
 646         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 647                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 648                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 649                 .rx_irq = INT_730_McBSP2RX,
 650                 .tx_irq = INT_730_McBSP2TX },
 651 };
 652 #endif
 653
 654 #ifdef CONFIG_ARCH_OMAP15XX
 655 static const struct omap_mcbsp_info mcbsp_1510[] = {
 656         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 657                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 658                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 659                 .rx_irq = INT_McBSP1RX,
 660                 .tx_irq = INT_McBSP1TX },
 661         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 662                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 663                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 664                 .rx_irq = INT_1510_SPI_RX,
 665                 .tx_irq = INT_1510_SPI_TX },
 666         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 667                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 668                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 669                 .rx_irq = INT_McBSP3RX,
 670                 .tx_irq = INT_McBSP3TX },
 671 };
 672 #endif
 673
 674 #if defined(CONFIG_ARCH_OMAP16XX)
 675 static const struct omap_mcbsp_info mcbsp_1610[] = {
 676         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 677                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 678                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 679                 .rx_irq = INT_McBSP1RX,
 680                 .tx_irq = INT_McBSP1TX },
 681         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 682                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 683                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 684                 .rx_irq = INT_1610_McBSP2_RX,
 685                 .tx_irq = INT_1610_McBSP2_TX },
 686         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 687                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 688                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 689                 .rx_irq = INT_McBSP3RX,
 690                 .tx_irq = INT_McBSP3TX },
 691 };
 692 #endif
 693
 694 static int __init omap_mcbsp_init(void)
 695 {
 696         int mcbsp_count = 0, i;
 697         static const struct omap_mcbsp_info *mcbsp_info;
 698
 699         printk("Initializing OMAP McBSP system\n");
 700
 701         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 702         if (IS_ERR(mcbsp_dsp_ck)) {
 703                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 704                 return PTR_ERR(mcbsp_dsp_ck);
 705         }
 706         mcbsp_api_ck = clk_get(0, "api_ck");
 707         if (IS_ERR(mcbsp_api_ck)) {
 708                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 709                 return PTR_ERR(mcbsp_api_ck);
 710         }
 711         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 712         if (IS_ERR(mcbsp_dspxor_ck)) {
 713                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 714                 return PTR_ERR(mcbsp_dspxor_ck);
 715         }
 716
 717 #ifdef CONFIG_ARCH_OMAP730
 718         if (cpu_is_omap730()) {
 719                 mcbsp_info = mcbsp_730;
 720                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
 721         }
 722 #endif
 723 #ifdef CONFIG_ARCH_OMAP15XX
 724         if (cpu_is_omap1510()) {
 725                 mcbsp_info = mcbsp_1510;
 726                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
 727         }
 728 #endif
 729 #if defined(CONFIG_ARCH_OMAP16XX)
 730         if (cpu_is_omap16xx()) {
 731                 mcbsp_info = mcbsp_1610;
 732                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
 733         }
 734 #endif
 735         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
 736                 if (i >= mcbsp_count) {
 737                         mcbsp[i].io_base = 0;
 738                         mcbsp[i].free = 0;
 739                         continue;
 740                 }
 741                 mcbsp[i].id = i + 1;
 742                 mcbsp[i].free = 1;
 743                 mcbsp[i].dma_tx_lch = -1;
 744                 mcbsp[i].dma_rx_lch = -1;
 745
 746                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
 747                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
 748                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
 749                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
 750                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
 751                 spin_lock_init(&mcbsp[i].lock);
 752         }
 753
 754         return 0;
 755 }
 756
 757
 758 arch_initcall(omap_mcbsp_init);
 759
 760 EXPORT_SYMBOL(omap_mcbsp_config);
 761 EXPORT_SYMBOL(omap_mcbsp_request);
 762 EXPORT_SYMBOL(omap_mcbsp_free);
 763 EXPORT_SYMBOL(omap_mcbsp_start);
 764 EXPORT_SYMBOL(omap_mcbsp_stop);
 765 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 766 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 767 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 768 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
 769 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);