arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include <asm/arch/dma.h>
  29 #include <asm/arch/mux.h>
  30 #include <asm/arch/irqs.h>
  31 #include <asm/arch/dsp_common.h>
  32 #include <asm/arch/mcbsp.h>
  33
  34 #ifdef CONFIG_MCBSP_DEBUG
  35 #define DBG(x...)       printk(x)
  36 #else
  37 #define DBG(x...)                       do { } while (0)
  38 #endif
  39
  40 struct omap_mcbsp {
  41         u32                          io_base;
  42         u8                           id;
  43         u8                           free;
  44         omap_mcbsp_word_length       rx_word_length;
  45         omap_mcbsp_word_length       tx_word_length;
  46
  47         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
  48         /* IRQ based TX/RX */
  49         int                          rx_irq;
  50         int                          tx_irq;
  51
  52         /* DMA stuff */
  53         u8                           dma_rx_sync;
  54         short                        dma_rx_lch;
  55         u8                           dma_tx_sync;
  56         short                        dma_tx_lch;
  57
  58         /* Completion queues */
  59         struct completion            tx_irq_completion;
  60         struct completion            rx_irq_completion;
  61         struct completion            tx_dma_completion;
  62         struct completion            rx_dma_completion;
  63
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 #ifdef CONFIG_ARCH_OMAP1
  69 static struct clk *mcbsp_dsp_ck = 0;
  70 static struct clk *mcbsp_api_ck = 0;
  71 static struct clk *mcbsp_dspxor_ck = 0;
  72 #endif
  73 #ifdef CONFIG_ARCH_OMAP2
  74 static struct clk *mcbsp1_ick = 0;
  75 static struct clk *mcbsp1_fck = 0;
  76 static struct clk *mcbsp2_ick = 0;
  77 static struct clk *mcbsp2_fck = 0;
  78 #endif
  79
  80 static void omap_mcbsp_dump_reg(u8 id)
  81 {
  82         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  83         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  84         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  85         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  86         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  87         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  88         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  89         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  90         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  91         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  92         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  93         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  94         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  95         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  96         DBG("***********************\n");
  97 }
  98
  99 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 100 {
 101         struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
 102
 103         DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 104
 105         complete(&mcbsp_tx->tx_irq_completion);
 106         return IRQ_HANDLED;
 107 }
 108
 109 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 110 {
 111         struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
 112
 113         DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 114
 115         complete(&mcbsp_rx->rx_irq_completion);
 116         return IRQ_HANDLED;
 117 }
 118
 119 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 120 {
 121         struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
 122
 123         DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 124
 125         /* We can free the channels */
 126         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 127         mcbsp_dma_tx->dma_tx_lch = -1;
 128
 129         complete(&mcbsp_dma_tx->tx_dma_completion);
 130 }
 131
 132 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 133 {
 134         struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
 135
 136         DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 137
 138         /* We can free the channels */
 139         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 140         mcbsp_dma_rx->dma_rx_lch = -1;
 141
 142         complete(&mcbsp_dma_rx->rx_dma_completion);
 143 }
 144
 145
 146 /*
 147  * omap_mcbsp_config simply write a config to the
 148  * appropriate McBSP.
 149  * You either call this function or set the McBSP registers
 150  * by yourself before calling omap_mcbsp_start().
 151  */
 152
 153 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
 154 {
 155         u32 io_base = mcbsp[id].io_base;
 156
 157         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
 158
 159         /* We write the given config */
 160         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 161         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 162         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 163         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 164         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 165         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 166         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 167         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 168         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 169         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 170         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 171 }
 172
 173
 174
 175 static int omap_mcbsp_check(unsigned int id)
 176 {
 177         if (cpu_is_omap730()) {
 178                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 179                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 180                        return -1;
 181                 }
 182                 return 0;
 183         }
 184
 185         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
 186                 if (id > OMAP_MAX_MCBSP_COUNT) {
 187                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 188                         return -1;
 189                 }
 190                 return 0;
 191         }
 192
 193         return -1;
 194 }
 195
 196 #ifdef CONFIG_ARCH_OMAP1
 197 static void omap_mcbsp_dsp_request(void)
 198 {
 199         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 200                 int ret;
 201
 202                 ret = omap_dsp_request_mem();
 203                 if (ret < 0) {
 204                         printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
 205                         return;
 206                 }
 207
 208                 clk_enable(mcbsp_dsp_ck);
 209                 clk_enable(mcbsp_api_ck);
 210
 211                 /* enable 12MHz clock to mcbsp 1 & 3 */
 212                 clk_enable(mcbsp_dspxor_ck);
 213
 214                 /*
 215                  * DSP external peripheral reset
 216                  * FIXME: This should be moved to dsp code
 217                  */
 218                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 219                              DSP_RSTCT2);
 220         }
 221 }
 222
 223 static void omap_mcbsp_dsp_free(void)
 224 {
 225         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 226                 omap_dsp_release_mem();
 227                 clk_disable(mcbsp_dspxor_ck);
 228                 clk_disable(mcbsp_dsp_ck);
 229                 clk_disable(mcbsp_api_ck);
 230         }
 231 }
 232 #endif
 233
 234 #ifdef CONFIG_ARCH_OMAP2
 235 static void omap2_mcbsp2_mux_setup(void)
 236 {
 237         if (cpu_is_omap2420()) {
 238                 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
 239                 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
 240                 omap_cfg_reg(W15_24XX_MCBSP2_DR);
 241                 omap_cfg_reg(V15_24XX_MCBSP2_DX);
 242                 omap_cfg_reg(V14_24XX_GPIO117);
 243         }
 244         /*
 245          * Need to add MUX settings for OMAP 2430 SDP
 246          */
 247 }
 248 #endif
 249
 250 /*
 251  * We can choose between IRQ based or polled IO.
 252  * This needs to be called before omap_mcbsp_request().
 253  */
 254 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 255 {
 256         if (omap_mcbsp_check(id) < 0)
 257                 return -EINVAL;
 258
 259         spin_lock(&mcbsp[id].lock);
 260
 261         if (!mcbsp[id].free) {
 262                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 263                 spin_unlock(&mcbsp[id].lock);
 264                 return -EINVAL;
 265         }
 266
 267         mcbsp[id].io_type = io_type;
 268
 269         spin_unlock(&mcbsp[id].lock);
 270
 271         return 0;
 272 }
 273
 274 int omap_mcbsp_request(unsigned int id)
 275 {
 276         int err;
 277
 278         if (omap_mcbsp_check(id) < 0)
 279                 return -EINVAL;
 280
 281 #ifdef CONFIG_ARCH_OMAP1
 282         /*
 283          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 284          * are DSP public peripherals.
 285          */
 286         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 287                 omap_mcbsp_dsp_request();
 288 #endif
 289
 290 #ifdef CONFIG_ARCH_OMAP2
 291         if (cpu_is_omap24xx()) {
 292                 if (id == OMAP_MCBSP1) {
 293                         clk_enable(mcbsp1_ick);
 294                         clk_enable(mcbsp1_fck);
 295                 } else {
 296                         clk_enable(mcbsp2_ick);
 297                         clk_enable(mcbsp2_fck);
 298                 }
 299         }
 300 #endif
 301
 302         spin_lock(&mcbsp[id].lock);
 303         if (!mcbsp[id].free) {
 304                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 305                 spin_unlock(&mcbsp[id].lock);
 306                 return -1;
 307         }
 308
 309         mcbsp[id].free = 0;
 310         spin_unlock(&mcbsp[id].lock);
 311
 312         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 313                 /* We need to get IRQs here */
 314                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
 315                                   "McBSP",
 316                                   (void *) (&mcbsp[id]));
 317                 if (err != 0) {
 318                         printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
 319                                mcbsp[id].tx_irq, mcbsp[id].id);
 320                         return err;
 321                 }
 322
 323                 init_completion(&(mcbsp[id].tx_irq_completion));
 324
 325
 326                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
 327                                   "McBSP",
 328                                   (void *) (&mcbsp[id]));
 329                 if (err != 0) {
 330                         printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
 331                                mcbsp[id].rx_irq, mcbsp[id].id);
 332                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 333                         return err;
 334                 }
 335
 336                 init_completion(&(mcbsp[id].rx_irq_completion));
 337         }
 338
 339         return 0;
 340
 341 }
 342
 343 void omap_mcbsp_free(unsigned int id)
 344 {
 345         if (omap_mcbsp_check(id) < 0)
 346                 return;
 347
 348 #ifdef CONFIG_ARCH_OMAP1
 349         if (cpu_class_is_omap1()) {
 350                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 351                         omap_mcbsp_dsp_free();
 352         }
 353 #endif
 354
 355 #ifdef CONFIG_ARCH_OMAP2
 356         if (cpu_is_omap24xx()) {
 357                 if (id == OMAP_MCBSP1) {
 358                         clk_disable(mcbsp1_ick);
 359                         clk_disable(mcbsp1_fck);
 360                 } else {
 361                         clk_disable(mcbsp2_ick);
 362                         clk_disable(mcbsp2_fck);
 363                 }
 364         }
 365 #endif
 366
 367         spin_lock(&mcbsp[id].lock);
 368         if (mcbsp[id].free) {
 369                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
 370                 spin_unlock(&mcbsp[id].lock);
 371                 return;
 372         }
 373
 374         mcbsp[id].free = 1;
 375         spin_unlock(&mcbsp[id].lock);
 376
 377         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 378                 /* Free IRQs */
 379                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 380                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 381         }
 382 }
 383
 384 /*
 385  * Here we start the McBSP, by enabling the sample
 386  * generator, both transmitter and receivers,
 387  * and the frame sync.
 388  */
 389 void omap_mcbsp_start(unsigned int id)
 390 {
 391         u32 io_base;
 392         u16 w;
 393
 394         if (omap_mcbsp_check(id) < 0)
 395                 return;
 396
 397         io_base = mcbsp[id].io_base;
 398
 399         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
 400         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
 401
 402         /* Start the sample generator */
 403         w = OMAP_MCBSP_READ(io_base, SPCR2);
 404         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 405
 406         /* Enable transmitter and receiver */
 407         w = OMAP_MCBSP_READ(io_base, SPCR2);
 408         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 409
 410         w = OMAP_MCBSP_READ(io_base, SPCR1);
 411         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 412
 413         udelay(100);
 414
 415         /* Start frame sync */
 416         w = OMAP_MCBSP_READ(io_base, SPCR2);
 417         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 418
 419         /* Dump McBSP Regs */
 420         omap_mcbsp_dump_reg(id);
 421
 422 }
 423
 424 void omap_mcbsp_stop(unsigned int id)
 425 {
 426         u32 io_base;
 427         u16 w;
 428
 429         if (omap_mcbsp_check(id) < 0)
 430                 return;
 431
 432         io_base = mcbsp[id].io_base;
 433
 434         /* Reset transmitter */
 435         w = OMAP_MCBSP_READ(io_base, SPCR2);
 436         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 437
 438         /* Reset receiver */
 439         w = OMAP_MCBSP_READ(io_base, SPCR1);
 440         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 441
 442         /* Reset the sample rate generator */
 443         w = OMAP_MCBSP_READ(io_base, SPCR2);
 444         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 445 }
 446
 447
 448 /* polled mcbsp i/o operations */
 449 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 450 {
 451         u32 base = mcbsp[id].io_base;
 452         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 453         /* if frame sync error - clear the error */
 454         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 455                 /* clear error */
 456                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 457                        base + OMAP_MCBSP_REG_SPCR2);
 458                 /* resend */
 459                 return -1;
 460         } else {
 461                 /* wait for transmit confirmation */
 462                 int attemps = 0;
 463                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 464                         if (attemps++ > 1000) {
 465                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 466                                        (~XRST),
 467                                        base + OMAP_MCBSP_REG_SPCR2);
 468                                 udelay(10);
 469                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 470                                        (XRST),
 471                                        base + OMAP_MCBSP_REG_SPCR2);
 472                                 udelay(10);
 473                                 printk(KERN_ERR
 474                                        " Could not write to McBSP Register\n");
 475                                 return -2;
 476                         }
 477                 }
 478         }
 479         return 0;
 480 }
 481
 482 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 483 {
 484         u32 base = mcbsp[id].io_base;
 485         /* if frame sync error - clear the error */
 486         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 487                 /* clear error */
 488                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 489                        base + OMAP_MCBSP_REG_SPCR1);
 490                 /* resend */
 491                 return -1;
 492         } else {
 493                 /* wait for recieve confirmation */
 494                 int attemps = 0;
 495                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 496                         if (attemps++ > 1000) {
 497                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 498                                        (~RRST),
 499                                        base + OMAP_MCBSP_REG_SPCR1);
 500                                 udelay(10);
 501                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 502                                        (RRST),
 503                                        base + OMAP_MCBSP_REG_SPCR1);
 504                                 udelay(10);
 505                                 printk(KERN_ERR
 506                                        " Could not read from McBSP Register\n");
 507                                 return -2;
 508                         }
 509                 }
 510         }
 511         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 512         return 0;
 513 }
 514
 515 /*
 516  * IRQ based word transmission.
 517  */
 518 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 519 {
 520         u32 io_base;
 521         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 522
 523         if (omap_mcbsp_check(id) < 0)
 524                 return;
 525
 526         io_base = mcbsp[id].io_base;
 527
 528         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 529
 530         if (word_length > OMAP_MCBSP_WORD_16)
 531                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 532         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 533 }
 534
 535 u32 omap_mcbsp_recv_word(unsigned int id)
 536 {
 537         u32 io_base;
 538         u16 word_lsb, word_msb = 0;
 539         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 540
 541         if (omap_mcbsp_check(id) < 0)
 542                 return -EINVAL;
 543
 544         io_base = mcbsp[id].io_base;
 545
 546         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 547
 548         if (word_length > OMAP_MCBSP_WORD_16)
 549                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 550         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 551
 552         return (word_lsb | (word_msb << 16));
 553 }
 554
 555
 556 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 557 {
 558         u32 io_base = mcbsp[id].io_base;
 559         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 560         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 561         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 562
 563         if (tx_word_length != rx_word_length)
 564                 return -EINVAL;
 565
 566         /* First we wait for the transmitter to be ready */
 567         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 568         while (!(spcr2 & XRDY)) {
 569                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 570                 if (attempts++ > 1000) {
 571                         /* We must reset the transmitter */
 572                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 573                         udelay(10);
 574                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 575                         udelay(10);
 576                         printk("McBSP transmitter not ready\n");
 577                         return -EAGAIN;
 578                 }
 579         }
 580
 581         /* Now we can push the data */
 582         if (tx_word_length > OMAP_MCBSP_WORD_16)
 583                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 584         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 585
 586         /* We wait for the receiver to be ready */
 587         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 588         while (!(spcr1 & RRDY)) {
 589                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 590                 if (attempts++ > 1000) {
 591                         /* We must reset the receiver */
 592                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 593                         udelay(10);
 594                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 595                         udelay(10);
 596                         printk("McBSP receiver not ready\n");
 597                         return -EAGAIN;
 598                 }
 599         }
 600
 601         /* Receiver is ready, let's read the dummy data */
 602         if (rx_word_length > OMAP_MCBSP_WORD_16)
 603                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 604         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 605
 606         return 0;
 607 }
 608
 609 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 610 {
 611         u32 io_base = mcbsp[id].io_base, clock_word = 0;
 612         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 613         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 614         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 615
 616         if (tx_word_length != rx_word_length)
 617                 return -EINVAL;
 618
 619         /* First we wait for the transmitter to be ready */
 620         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 621         while (!(spcr2 & XRDY)) {
 622                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 623                 if (attempts++ > 1000) {
 624                         /* We must reset the transmitter */
 625                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 626                         udelay(10);
 627                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 628                         udelay(10);
 629                         printk("McBSP transmitter not ready\n");
 630                         return -EAGAIN;
 631                 }
 632         }
 633
 634         /* We first need to enable the bus clock */
 635         if (tx_word_length > OMAP_MCBSP_WORD_16)
 636                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 637         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 638
 639         /* We wait for the receiver to be ready */
 640         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 641         while (!(spcr1 & RRDY)) {
 642                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 643                 if (attempts++ > 1000) {
 644                         /* We must reset the receiver */
 645                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 646                         udelay(10);
 647                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 648                         udelay(10);
 649                         printk("McBSP receiver not ready\n");
 650                         return -EAGAIN;
 651                 }
 652         }
 653
 654         /* Receiver is ready, there is something for us */
 655         if (rx_word_length > OMAP_MCBSP_WORD_16)
 656                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 657         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 658
 659         word[0] = (word_lsb | (word_msb << 16));
 660
 661         return 0;
 662 }
 663
 664
 665 /*
 666  * Simple DMA based buffer rx/tx routines.
 667  * Nothing fancy, just a single buffer tx/rx through DMA.
 668  * The DMA resources are released once the transfer is done.
 669  * For anything fancier, you should use your own customized DMA
 670  * routines and callbacks.
 671  */
 672 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 673 {
 674         int dma_tx_ch;
 675         int src_port = 0;
 676         int dest_port = 0;
 677         int sync_dev = 0;
 678
 679         if (omap_mcbsp_check(id) < 0)
 680                 return -EINVAL;
 681
 682         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
 683                              &mcbsp[id],
 684                              &dma_tx_ch)) {
 685                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
 686                 return -EAGAIN;
 687         }
 688         mcbsp[id].dma_tx_lch = dma_tx_ch;
 689
 690         DBG("TX DMA on channel %d\n", dma_tx_ch);
 691
 692         init_completion(&(mcbsp[id].tx_dma_completion));
 693
 694         if (cpu_class_is_omap1()) {
 695                 src_port = OMAP_DMA_PORT_TIPB;
 696                 dest_port = OMAP_DMA_PORT_EMIFF;
 697         }
 698         if (cpu_is_omap24xx())
 699                 sync_dev = mcbsp[id].dma_tx_sync;
 700
 701         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 702                                      OMAP_DMA_DATA_TYPE_S16,
 703                                      length >> 1, 1,
 704                                      OMAP_DMA_SYNC_ELEMENT,
 705          sync_dev, 0);
 706
 707         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 708                                  src_port,
 709                                  OMAP_DMA_AMODE_CONSTANT,
 710                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 711                                  0, 0);
 712
 713         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 714                                 dest_port,
 715                                 OMAP_DMA_AMODE_POST_INC,
 716                                 buffer,
 717                                 0, 0);
 718
 719         omap_start_dma(mcbsp[id].dma_tx_lch);
 720         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 721         return 0;
 722 }
 723
 724
 725 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 726 {
 727         int dma_rx_ch;
 728         int src_port = 0;
 729         int dest_port = 0;
 730         int sync_dev = 0;
 731
 732         if (omap_mcbsp_check(id) < 0)
 733                 return -EINVAL;
 734
 735         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
 736                              &mcbsp[id],
 737                              &dma_rx_ch)) {
 738                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
 739                 return -EAGAIN;
 740         }
 741         mcbsp[id].dma_rx_lch = dma_rx_ch;
 742
 743         DBG("RX DMA on channel %d\n", dma_rx_ch);
 744
 745         init_completion(&(mcbsp[id].rx_dma_completion));
 746
 747         if (cpu_class_is_omap1()) {
 748                 src_port = OMAP_DMA_PORT_TIPB;
 749                 dest_port = OMAP_DMA_PORT_EMIFF;
 750         }
 751         if (cpu_is_omap24xx())
 752                 sync_dev = mcbsp[id].dma_rx_sync;
 753
 754         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 755                                      OMAP_DMA_DATA_TYPE_S16,
 756                                      length >> 1, 1,
 757                                      OMAP_DMA_SYNC_ELEMENT,
 758          sync_dev, 0);
 759
 760         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 761                                 src_port,
 762                                 OMAP_DMA_AMODE_CONSTANT,
 763                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 764                                 0, 0);
 765
 766         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 767                                  dest_port,
 768                                  OMAP_DMA_AMODE_POST_INC,
 769                                  buffer,
 770                                  0, 0);
 771
 772         omap_start_dma(mcbsp[id].dma_rx_lch);
 773         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 774         return 0;
 775 }
 776
 777
 778 /*
 779  * SPI wrapper.
 780  * Since SPI setup is much simpler than the generic McBSP one,
 781  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 782  * Once this is done, you can call omap_mcbsp_start().
 783  */
 784 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
 785 {
 786         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 787
 788         if (omap_mcbsp_check(id) < 0)
 789                 return;
 790
 791         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 792
 793         /* SPI has only one frame */
 794         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 795         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 796
 797         /* Clock stop mode */
 798         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 799                 mcbsp_cfg.spcr1 |= (1 << 12);
 800         else
 801                 mcbsp_cfg.spcr1 |= (3 << 11);
 802
 803         /* Set clock parities */
 804         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 805                 mcbsp_cfg.pcr0 |= CLKRP;
 806         else
 807                 mcbsp_cfg.pcr0 &= ~CLKRP;
 808
 809         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 810                 mcbsp_cfg.pcr0 &= ~CLKXP;
 811         else
 812                 mcbsp_cfg.pcr0 |= CLKXP;
 813
 814         /* Set SCLKME to 0 and CLKSM to 1 */
 815         mcbsp_cfg.pcr0 &= ~SCLKME;
 816         mcbsp_cfg.srgr2 |= CLKSM;
 817
 818         /* Set FSXP */
 819         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 820                 mcbsp_cfg.pcr0 &= ~FSXP;
 821         else
 822                 mcbsp_cfg.pcr0 |= FSXP;
 823
 824         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 825                 mcbsp_cfg.pcr0 |= CLKXM;
 826                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
 827                 mcbsp_cfg.pcr0 |= FSXM;
 828                 mcbsp_cfg.srgr2 &= ~FSGM;
 829                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 830                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 831         }
 832         else {
 833                 mcbsp_cfg.pcr0 &= ~CLKXM;
 834                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 835                 mcbsp_cfg.pcr0 &= ~FSXM;
 836                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 837                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 838         }
 839
 840         mcbsp_cfg.xcr2 &= ~XPHASE;
 841         mcbsp_cfg.rcr2 &= ~RPHASE;
 842
 843         omap_mcbsp_config(id, &mcbsp_cfg);
 844 }
 845
 846
 847 /*
 848  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 849  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 850  */
 851 struct omap_mcbsp_info {
 852         u32 virt_base;
 853         u8 dma_rx_sync, dma_tx_sync;
 854         u16 rx_irq, tx_irq;
 855 };
 856
 857 #ifdef CONFIG_ARCH_OMAP730
 858 static const struct omap_mcbsp_info mcbsp_730[] = {
 859         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 860                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 861                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 862                 .rx_irq = INT_730_McBSP1RX,
 863                 .tx_irq = INT_730_McBSP1TX },
 864         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 865                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 866                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 867                 .rx_irq = INT_730_McBSP2RX,
 868                 .tx_irq = INT_730_McBSP2TX },
 869 };
 870 #endif
 871
 872 #ifdef CONFIG_ARCH_OMAP15XX
 873 static const struct omap_mcbsp_info mcbsp_1510[] = {
 874         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 875                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 876                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 877                 .rx_irq = INT_McBSP1RX,
 878                 .tx_irq = INT_McBSP1TX },
 879         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 880                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 881                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 882                 .rx_irq = INT_1510_SPI_RX,
 883                 .tx_irq = INT_1510_SPI_TX },
 884         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 885                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 886                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 887                 .rx_irq = INT_McBSP3RX,
 888                 .tx_irq = INT_McBSP3TX },
 889 };
 890 #endif
 891
 892 #if defined(CONFIG_ARCH_OMAP16XX)
 893 static const struct omap_mcbsp_info mcbsp_1610[] = {
 894         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 895                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 896                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 897                 .rx_irq = INT_McBSP1RX,
 898                 .tx_irq = INT_McBSP1TX },
 899         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 900                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 901                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 902                 .rx_irq = INT_1610_McBSP2_RX,
 903                 .tx_irq = INT_1610_McBSP2_TX },
 904         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 905                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 906                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 907                 .rx_irq = INT_McBSP3RX,
 908                 .tx_irq = INT_McBSP3TX },
 909 };
 910 #endif
 911
 912 #if defined(CONFIG_ARCH_OMAP24XX)
 913 static const struct omap_mcbsp_info mcbsp_24xx[] = {
 914         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
 915                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
 916                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
 917                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
 918                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
 919                 },
 920         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
 921                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
 922                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
 923                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
 924                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
 925                 },
 926 };
 927 #endif
 928
 929 static int __init omap_mcbsp_init(void)
 930 {
 931         int mcbsp_count = 0, i;
 932         static const struct omap_mcbsp_info *mcbsp_info;
 933
 934         printk("Initializing OMAP McBSP system\n");
 935
 936 #ifdef CONFIG_ARCH_OMAP1
 937         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 938         if (IS_ERR(mcbsp_dsp_ck)) {
 939                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 940                 return PTR_ERR(mcbsp_dsp_ck);
 941         }
 942         mcbsp_api_ck = clk_get(0, "api_ck");
 943         if (IS_ERR(mcbsp_api_ck)) {
 944                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 945                 return PTR_ERR(mcbsp_api_ck);
 946         }
 947         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 948         if (IS_ERR(mcbsp_dspxor_ck)) {
 949                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 950                 return PTR_ERR(mcbsp_dspxor_ck);
 951         }
 952 #endif
 953 #ifdef CONFIG_ARCH_OMAP2
 954         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
 955         if (IS_ERR(mcbsp1_ick)) {
 956                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
 957                 return PTR_ERR(mcbsp1_ick);
 958         }
 959         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
 960         if (IS_ERR(mcbsp1_fck)) {
 961                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
 962                 return PTR_ERR(mcbsp1_fck);
 963         }
 964         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
 965         if (IS_ERR(mcbsp2_ick)) {
 966                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
 967                 return PTR_ERR(mcbsp2_ick);
 968         }
 969         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
 970         if (IS_ERR(mcbsp2_fck)) {
 971                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
 972                 return PTR_ERR(mcbsp2_fck);
 973         }
 974 #endif
 975
 976 #ifdef CONFIG_ARCH_OMAP730
 977         if (cpu_is_omap730()) {
 978                 mcbsp_info = mcbsp_730;
 979                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
 980         }
 981 #endif
 982 #ifdef CONFIG_ARCH_OMAP15XX
 983         if (cpu_is_omap15xx()) {
 984                 mcbsp_info = mcbsp_1510;
 985                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
 986         }
 987 #endif
 988 #if defined(CONFIG_ARCH_OMAP16XX)
 989         if (cpu_is_omap16xx()) {
 990                 mcbsp_info = mcbsp_1610;
 991                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
 992         }
 993 #endif
 994 #if defined(CONFIG_ARCH_OMAP24XX)
 995         if (cpu_is_omap24xx()) {
 996                 mcbsp_info = mcbsp_24xx;
 997                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
 998                 omap2_mcbsp2_mux_setup();
 999         }
1000 #endif
1001         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
1002                 if (i >= mcbsp_count) {
1003                         mcbsp[i].io_base = 0;
1004                         mcbsp[i].free = 0;
1005                         continue;
1006                 }
1007                 mcbsp[i].id = i + 1;
1008                 mcbsp[i].free = 1;
1009                 mcbsp[i].dma_tx_lch = -1;
1010                 mcbsp[i].dma_rx_lch = -1;
1011
1012                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1013                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1014                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1015                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1016                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1017                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1018                 spin_lock_init(&mcbsp[i].lock);
1019         }
1020
1021         return 0;
1022 }
1023
1024 arch_initcall(omap_mcbsp_init);
1025
1026 EXPORT_SYMBOL(omap_mcbsp_config);
1027 EXPORT_SYMBOL(omap_mcbsp_request);
1028 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1029 EXPORT_SYMBOL(omap_mcbsp_free);
1030 EXPORT_SYMBOL(omap_mcbsp_start);
1031 EXPORT_SYMBOL(omap_mcbsp_stop);
1032 EXPORT_SYMBOL(omap_mcbsp_pollread);
1033 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1034 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1035 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1036 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1037 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1038 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1039 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1040 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);