2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/wait.h>
19 #include <linux/completion.h>
20 #include <linux/interrupt.h>
21 #include <linux/err.h>
23 #include <asm/delay.h>
27 #include <asm/arch/dma.h>
28 #include <asm/arch/mux.h>
29 #include <asm/arch/irqs.h>
30 #include <asm/arch/dsp_common.h>
31 #include <asm/arch/mcbsp.h>
33 #include <asm/hardware/clock.h>
35 #ifdef CONFIG_MCBSP_DEBUG
36 #define DBG(x...) printk(x)
38 #define DBG(x...) do { } while (0)
45 omap_mcbsp_word_length rx_word_length;
46 omap_mcbsp_word_length tx_word_length;
58 /* Completion queues */
59 struct completion tx_irq_completion;
60 struct completion rx_irq_completion;
61 struct completion tx_dma_completion;
62 struct completion rx_dma_completion;
67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
68 static struct clk *mcbsp_dsp_ck = 0;
69 static struct clk *mcbsp_api_ck = 0;
70 static struct clk *mcbsp_dspxor_ck = 0;
73 static void omap_mcbsp_dump_reg(u8 id)
75 DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
76 DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
77 DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
78 DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
79 DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
80 DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
81 DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
82 DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
83 DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
84 DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
85 DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
86 DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
87 DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
88 DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
89 DBG("***********************\n");
93 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
95 struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
97 DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
99 complete(&mcbsp_tx->tx_irq_completion);
103 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
105 struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
107 DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
109 complete(&mcbsp_rx->rx_irq_completion);
114 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
116 struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
118 DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
120 /* We can free the channels */
121 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
122 mcbsp_dma_tx->dma_tx_lch = -1;
124 complete(&mcbsp_dma_tx->tx_dma_completion);
127 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
129 struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
131 DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
133 /* We can free the channels */
134 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
135 mcbsp_dma_rx->dma_rx_lch = -1;
137 complete(&mcbsp_dma_rx->rx_dma_completion);
142 * omap_mcbsp_config simply write a config to the
144 * You either call this function or set the McBSP registers
145 * by yourself before calling omap_mcbsp_start().
148 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
150 u32 io_base = mcbsp[id].io_base;
152 DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id+1, io_base);
154 /* We write the given config */
155 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
156 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
157 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
158 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
159 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
160 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
161 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
162 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
163 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
164 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
165 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
170 static int omap_mcbsp_check(unsigned int id)
172 if (cpu_is_omap730()) {
173 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
174 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
180 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
181 if (id > OMAP_MAX_MCBSP_COUNT) {
182 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
191 static void omap_mcbsp_dsp_request(void)
193 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
194 omap_dsp_request_mem();
195 clk_enable(mcbsp_dsp_ck);
196 clk_enable(mcbsp_api_ck);
198 /* enable 12MHz clock to mcbsp 1 & 3 */
199 clk_enable(mcbsp_dspxor_ck);
202 * DSP external peripheral reset
203 * FIXME: This should be moved to dsp code
205 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
210 static void omap_mcbsp_dsp_free(void)
212 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
213 omap_dsp_release_mem();
214 clk_disable(mcbsp_dspxor_ck);
215 clk_disable(mcbsp_dsp_ck);
216 clk_disable(mcbsp_api_ck);
220 int omap_mcbsp_request(unsigned int id)
224 if (omap_mcbsp_check(id) < 0)
228 * On 1510, 1610 and 1710, McBSP1 and McBSP3
229 * are DSP public peripherals.
231 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
232 omap_mcbsp_dsp_request();
234 spin_lock(&mcbsp[id].lock);
235 if (!mcbsp[id].free) {
236 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
237 spin_unlock(&mcbsp[id].lock);
242 spin_unlock(&mcbsp[id].lock);
244 /* We need to get IRQs here */
245 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
247 (void *) (&mcbsp[id]));
249 printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
250 mcbsp[id].tx_irq, mcbsp[id].id);
254 init_completion(&(mcbsp[id].tx_irq_completion));
257 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
259 (void *) (&mcbsp[id]));
261 printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
262 mcbsp[id].rx_irq, mcbsp[id].id);
263 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
267 init_completion(&(mcbsp[id].rx_irq_completion));
272 void omap_mcbsp_free(unsigned int id)
274 if (omap_mcbsp_check(id) < 0)
277 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
278 omap_mcbsp_dsp_free();
280 spin_lock(&mcbsp[id].lock);
281 if (mcbsp[id].free) {
282 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
283 spin_unlock(&mcbsp[id].lock);
288 spin_unlock(&mcbsp[id].lock);
291 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
292 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
296 * Here we start the McBSP, by enabling the sample
297 * generator, both transmitter and receivers,
298 * and the frame sync.
300 void omap_mcbsp_start(unsigned int id)
305 if (omap_mcbsp_check(id) < 0)
308 io_base = mcbsp[id].io_base;
310 mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
311 mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
313 /* Start the sample generator */
314 w = OMAP_MCBSP_READ(io_base, SPCR2);
315 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
317 /* Enable transmitter and receiver */
318 w = OMAP_MCBSP_READ(io_base, SPCR2);
319 OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
321 w = OMAP_MCBSP_READ(io_base, SPCR1);
322 OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
326 /* Start frame sync */
327 w = OMAP_MCBSP_READ(io_base, SPCR2);
328 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
330 /* Dump McBSP Regs */
331 omap_mcbsp_dump_reg(id);
335 void omap_mcbsp_stop(unsigned int id)
340 if (omap_mcbsp_check(id) < 0)
343 io_base = mcbsp[id].io_base;
345 /* Reset transmitter */
346 w = OMAP_MCBSP_READ(io_base, SPCR2);
347 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
350 w = OMAP_MCBSP_READ(io_base, SPCR1);
351 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
353 /* Reset the sample rate generator */
354 w = OMAP_MCBSP_READ(io_base, SPCR2);
355 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
359 /* polled mcbsp i/o operations */
360 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
362 u32 base = mcbsp[id].io_base;
363 writew(buf, base + OMAP_MCBSP_REG_DXR1);
364 /* if frame sync error - clear the error */
365 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
367 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
368 base + OMAP_MCBSP_REG_SPCR2);
372 /* wait for transmit confirmation */
374 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
375 if (attemps++ > 1000) {
376 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
378 base + OMAP_MCBSP_REG_SPCR2);
380 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
382 base + OMAP_MCBSP_REG_SPCR2);
385 " Could not write to McBSP Register\n");
393 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
395 u32 base = mcbsp[id].io_base;
396 /* if frame sync error - clear the error */
397 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
399 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
400 base + OMAP_MCBSP_REG_SPCR1);
404 /* wait for recieve confirmation */
406 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
407 if (attemps++ > 1000) {
408 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
410 base + OMAP_MCBSP_REG_SPCR1);
412 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
414 base + OMAP_MCBSP_REG_SPCR1);
417 " Could not read from McBSP Register\n");
422 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
427 * IRQ based word transmission.
429 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
432 omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
434 if (omap_mcbsp_check(id) < 0)
437 io_base = mcbsp[id].io_base;
439 wait_for_completion(&(mcbsp[id].tx_irq_completion));
441 if (word_length > OMAP_MCBSP_WORD_16)
442 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
443 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
446 u32 omap_mcbsp_recv_word(unsigned int id)
449 u16 word_lsb, word_msb = 0;
450 omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
452 if (omap_mcbsp_check(id) < 0)
455 io_base = mcbsp[id].io_base;
457 wait_for_completion(&(mcbsp[id].rx_irq_completion));
459 if (word_length > OMAP_MCBSP_WORD_16)
460 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
461 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
463 return (word_lsb | (word_msb << 16));
468 * Simple DMA based buffer rx/tx routines.
469 * Nothing fancy, just a single buffer tx/rx through DMA.
470 * The DMA resources are released once the transfer is done.
471 * For anything fancier, you should use your own customized DMA
472 * routines and callbacks.
474 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
478 if (omap_mcbsp_check(id) < 0)
481 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
484 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
487 mcbsp[id].dma_tx_lch = dma_tx_ch;
489 DBG("TX DMA on channel %d\n", dma_tx_ch);
491 init_completion(&(mcbsp[id].tx_dma_completion));
493 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
494 OMAP_DMA_DATA_TYPE_S16,
496 OMAP_DMA_SYNC_ELEMENT,
499 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
501 OMAP_DMA_AMODE_CONSTANT,
502 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
505 omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
507 OMAP_DMA_AMODE_POST_INC,
511 omap_start_dma(mcbsp[id].dma_tx_lch);
512 wait_for_completion(&(mcbsp[id].tx_dma_completion));
517 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
521 if (omap_mcbsp_check(id) < 0)
524 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
527 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
530 mcbsp[id].dma_rx_lch = dma_rx_ch;
532 DBG("RX DMA on channel %d\n", dma_rx_ch);
534 init_completion(&(mcbsp[id].rx_dma_completion));
536 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
537 OMAP_DMA_DATA_TYPE_S16,
539 OMAP_DMA_SYNC_ELEMENT,
542 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
544 OMAP_DMA_AMODE_CONSTANT,
545 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
548 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
550 OMAP_DMA_AMODE_POST_INC,
554 omap_start_dma(mcbsp[id].dma_rx_lch);
555 wait_for_completion(&(mcbsp[id].rx_dma_completion));
562 * Since SPI setup is much simpler than the generic McBSP one,
563 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
564 * Once this is done, you can call omap_mcbsp_start().
566 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
568 struct omap_mcbsp_reg_cfg mcbsp_cfg;
570 if (omap_mcbsp_check(id) < 0)
573 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
575 /* SPI has only one frame */
576 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
577 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
579 /* Clock stop mode */
580 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
581 mcbsp_cfg.spcr1 |= (1 << 12);
583 mcbsp_cfg.spcr1 |= (3 << 11);
585 /* Set clock parities */
586 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
587 mcbsp_cfg.pcr0 |= CLKRP;
589 mcbsp_cfg.pcr0 &= ~CLKRP;
591 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
592 mcbsp_cfg.pcr0 &= ~CLKXP;
594 mcbsp_cfg.pcr0 |= CLKXP;
596 /* Set SCLKME to 0 and CLKSM to 1 */
597 mcbsp_cfg.pcr0 &= ~SCLKME;
598 mcbsp_cfg.srgr2 |= CLKSM;
601 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
602 mcbsp_cfg.pcr0 &= ~FSXP;
604 mcbsp_cfg.pcr0 |= FSXP;
606 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
607 mcbsp_cfg.pcr0 |= CLKXM;
608 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
609 mcbsp_cfg.pcr0 |= FSXM;
610 mcbsp_cfg.srgr2 &= ~FSGM;
611 mcbsp_cfg.xcr2 |= XDATDLY(1);
612 mcbsp_cfg.rcr2 |= RDATDLY(1);
615 mcbsp_cfg.pcr0 &= ~CLKXM;
616 mcbsp_cfg.srgr1 |= CLKGDV(1);
617 mcbsp_cfg.pcr0 &= ~FSXM;
618 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
619 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
622 mcbsp_cfg.xcr2 &= ~XPHASE;
623 mcbsp_cfg.rcr2 &= ~RPHASE;
625 omap_mcbsp_config(id, &mcbsp_cfg);
630 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
631 * 730 has only 2 McBSP, and both of them are MPU peripherals.
633 struct omap_mcbsp_info {
635 u8 dma_rx_sync, dma_tx_sync;
639 #ifdef CONFIG_ARCH_OMAP730
640 static const struct omap_mcbsp_info mcbsp_730[] = {
641 [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
642 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
643 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
644 .rx_irq = INT_730_McBSP1RX,
645 .tx_irq = INT_730_McBSP1TX },
646 [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
647 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
648 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
649 .rx_irq = INT_730_McBSP2RX,
650 .tx_irq = INT_730_McBSP2TX },
654 #ifdef CONFIG_ARCH_OMAP15XX
655 static const struct omap_mcbsp_info mcbsp_1510[] = {
656 [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
657 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
658 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
659 .rx_irq = INT_McBSP1RX,
660 .tx_irq = INT_McBSP1TX },
661 [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
662 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
663 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
664 .rx_irq = INT_1510_SPI_RX,
665 .tx_irq = INT_1510_SPI_TX },
666 [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
667 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
668 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
669 .rx_irq = INT_McBSP3RX,
670 .tx_irq = INT_McBSP3TX },
674 #if defined(CONFIG_ARCH_OMAP16XX)
675 static const struct omap_mcbsp_info mcbsp_1610[] = {
676 [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
677 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
678 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
679 .rx_irq = INT_McBSP1RX,
680 .tx_irq = INT_McBSP1TX },
681 [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
682 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
683 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
684 .rx_irq = INT_1610_McBSP2_RX,
685 .tx_irq = INT_1610_McBSP2_TX },
686 [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
687 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
688 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
689 .rx_irq = INT_McBSP3RX,
690 .tx_irq = INT_McBSP3TX },
694 static int __init omap_mcbsp_init(void)
696 int mcbsp_count = 0, i;
697 static const struct omap_mcbsp_info *mcbsp_info;
699 printk("Initializing OMAP McBSP system\n");
701 mcbsp_dsp_ck = clk_get(0, "dsp_ck");
702 if (IS_ERR(mcbsp_dsp_ck)) {
703 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
704 return PTR_ERR(mcbsp_dsp_ck);
706 mcbsp_api_ck = clk_get(0, "api_ck");
707 if (IS_ERR(mcbsp_api_ck)) {
708 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
709 return PTR_ERR(mcbsp_api_ck);
711 mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
712 if (IS_ERR(mcbsp_dspxor_ck)) {
713 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
714 return PTR_ERR(mcbsp_dspxor_ck);
717 #ifdef CONFIG_ARCH_OMAP730
718 if (cpu_is_omap730()) {
719 mcbsp_info = mcbsp_730;
720 mcbsp_count = ARRAY_SIZE(mcbsp_730);
723 #ifdef CONFIG_ARCH_OMAP15XX
724 if (cpu_is_omap1510()) {
725 mcbsp_info = mcbsp_1510;
726 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
729 #if defined(CONFIG_ARCH_OMAP16XX)
730 if (cpu_is_omap16xx()) {
731 mcbsp_info = mcbsp_1610;
732 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
735 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
736 if (i >= mcbsp_count) {
737 mcbsp[i].io_base = 0;
743 mcbsp[i].dma_tx_lch = -1;
744 mcbsp[i].dma_rx_lch = -1;
746 mcbsp[i].io_base = mcbsp_info[i].virt_base;
747 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
748 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
749 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
750 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
751 spin_lock_init(&mcbsp[i].lock);
758 arch_initcall(omap_mcbsp_init);
760 EXPORT_SYMBOL(omap_mcbsp_config);
761 EXPORT_SYMBOL(omap_mcbsp_request);
762 EXPORT_SYMBOL(omap_mcbsp_free);
763 EXPORT_SYMBOL(omap_mcbsp_start);
764 EXPORT_SYMBOL(omap_mcbsp_stop);
765 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
766 EXPORT_SYMBOL(omap_mcbsp_recv_word);
767 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
768 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
769 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);