arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26
  27 #include <asm/arch/dma.h>
  28 #include <asm/arch/mux.h>
  29 #include <asm/arch/irqs.h>
  30 #include <asm/arch/dsp_common.h>
  31 #include <asm/arch/mcbsp.h>
  32
  33 #ifdef CONFIG_MCBSP_DEBUG
  34 #define DBG(x...)       printk(x)
  35 #else
  36 #define DBG(x...)                       do { } while (0)
  37 #endif
  38
  39 struct omap_mcbsp {
  40         u32                          io_base;
  41         u8                           id;
  42         u8                           free;
  43         omap_mcbsp_word_length       rx_word_length;
  44         omap_mcbsp_word_length       tx_word_length;
  45
  46         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
  47         /* IRQ based TX/RX */
  48         int                          rx_irq;
  49         int                          tx_irq;
  50
  51         /* DMA stuff */
  52         u8                           dma_rx_sync;
  53         short                        dma_rx_lch;
  54         u8                           dma_tx_sync;
  55         short                        dma_tx_lch;
  56
  57         /* Completion queues */
  58         struct completion            tx_irq_completion;
  59         struct completion            rx_irq_completion;
  60         struct completion            tx_dma_completion;
  61         struct completion            rx_dma_completion;
  62
  63         /* Protect the field .free, while checking if the mcbsp is in use */
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 #ifdef CONFIG_ARCH_OMAP1
  69 static struct clk *mcbsp_dsp_ck;
  70 static struct clk *mcbsp_api_ck;
  71 static struct clk *mcbsp_dspxor_ck;
  72 #endif
  73 #ifdef CONFIG_ARCH_OMAP2
  74 static struct clk *mcbsp1_ick;
  75 static struct clk *mcbsp1_fck;
  76 static struct clk *mcbsp2_ick;
  77 static struct clk *mcbsp2_fck;
  78 #endif
  79
  80 static void omap_mcbsp_dump_reg(u8 id)
  81 {
  82         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  83         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  84         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  85         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  86         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  87         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  88         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  89         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  90         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  91         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  92         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  93         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  94         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  95         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  96         DBG("***********************\n");
  97 }
  98
  99 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 100 {
 101         struct omap_mcbsp *mcbsp_tx = dev_id;
 102
 103         DBG("TX IRQ callback : 0x%x\n",
 104             OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 105
 106         complete(&mcbsp_tx->tx_irq_completion);
 107
 108         return IRQ_HANDLED;
 109 }
 110
 111 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 112 {
 113         struct omap_mcbsp *mcbsp_rx = dev_id;
 114
 115         DBG("RX IRQ callback : 0x%x\n",
 116             OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 117
 118         complete(&mcbsp_rx->rx_irq_completion);
 119
 120         return IRQ_HANDLED;
 121 }
 122
 123 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 124 {
 125         struct omap_mcbsp *mcbsp_dma_tx = data;
 126
 127         DBG("TX DMA callback : 0x%x\n",
 128             OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 129
 130         /* We can free the channels */
 131         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 132         mcbsp_dma_tx->dma_tx_lch = -1;
 133
 134         complete(&mcbsp_dma_tx->tx_dma_completion);
 135 }
 136
 137 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 138 {
 139         struct omap_mcbsp *mcbsp_dma_rx = data;
 140
 141         DBG("RX DMA callback : 0x%x\n",
 142             OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 143
 144         /* We can free the channels */
 145         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 146         mcbsp_dma_rx->dma_rx_lch = -1;
 147
 148         complete(&mcbsp_dma_rx->rx_dma_completion);
 149 }
 150
 151 /*
 152  * omap_mcbsp_config simply write a config to the
 153  * appropriate McBSP.
 154  * You either call this function or set the McBSP registers
 155  * by yourself before calling omap_mcbsp_start().
 156  */
 157 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 158 {
 159         u32 io_base = mcbsp[id].io_base;
 160
 161         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id + 1, io_base);
 162
 163         /* We write the given config */
 164         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 165         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 166         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 167         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 168         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 169         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 170         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 171         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 172         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 173         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 174         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 175 }
 176 EXPORT_SYMBOL(omap_mcbsp_config);
 177
 178 static int omap_mcbsp_check(unsigned int id)
 179 {
 180         if (cpu_is_omap730()) {
 181                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 182                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
 183                                 id + 1);
 184                        return -1;
 185                 }
 186                 return 0;
 187         }
 188
 189         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
 190                 if (id > OMAP_MAX_MCBSP_COUNT) {
 191                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
 192                                 id + 1);
 193                         return -1;
 194                 }
 195                 return 0;
 196         }
 197
 198         return -1;
 199 }
 200
 201 #ifdef CONFIG_ARCH_OMAP1
 202 static void omap_mcbsp_dsp_request(void)
 203 {
 204         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 205                 int ret;
 206
 207                 ret = omap_dsp_request_mem();
 208                 if (ret < 0) {
 209                         printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
 210                         return;
 211                 }
 212
 213                 clk_enable(mcbsp_dsp_ck);
 214                 clk_enable(mcbsp_api_ck);
 215
 216                 /* enable 12MHz clock to mcbsp 1 & 3 */
 217                 clk_enable(mcbsp_dspxor_ck);
 218
 219                 /*
 220                  * DSP external peripheral reset
 221                  * FIXME: This should be moved to dsp code
 222                  */
 223                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 224                              DSP_RSTCT2);
 225         }
 226 }
 227
 228 static void omap_mcbsp_dsp_free(void)
 229 {
 230         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 231                 omap_dsp_release_mem();
 232                 clk_disable(mcbsp_dspxor_ck);
 233                 clk_disable(mcbsp_dsp_ck);
 234                 clk_disable(mcbsp_api_ck);
 235         }
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_ARCH_OMAP2
 240 static void omap2_mcbsp2_mux_setup(void)
 241 {
 242         if (cpu_is_omap2420()) {
 243                 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
 244                 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
 245                 omap_cfg_reg(W15_24XX_MCBSP2_DR);
 246                 omap_cfg_reg(V15_24XX_MCBSP2_DX);
 247                 omap_cfg_reg(V14_24XX_GPIO117);
 248         }
 249         /*
 250          * Need to add MUX settings for OMAP 2430 SDP
 251          */
 252 }
 253 #endif
 254
 255 /*
 256  * We can choose between IRQ based or polled IO.
 257  * This needs to be called before omap_mcbsp_request().
 258  */
 259 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 260 {
 261         if (omap_mcbsp_check(id) < 0)
 262                 return -EINVAL;
 263
 264         spin_lock(&mcbsp[id].lock);
 265
 266         if (!mcbsp[id].free) {
 267                 printk(KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n",
 268                         id + 1);
 269                 spin_unlock(&mcbsp[id].lock);
 270                 return -EINVAL;
 271         }
 272
 273         mcbsp[id].io_type = io_type;
 274
 275         spin_unlock(&mcbsp[id].lock);
 276
 277         return 0;
 278 }
 279 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 280
 281 int omap_mcbsp_request(unsigned int id)
 282 {
 283         int err;
 284
 285         if (omap_mcbsp_check(id) < 0)
 286                 return -EINVAL;
 287
 288 #ifdef CONFIG_ARCH_OMAP1
 289         /*
 290          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 291          * are DSP public peripherals.
 292          */
 293         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 294                 omap_mcbsp_dsp_request();
 295 #endif
 296
 297 #ifdef CONFIG_ARCH_OMAP2
 298         if (cpu_is_omap24xx()) {
 299                 if (id == OMAP_MCBSP1) {
 300                         clk_enable(mcbsp1_ick);
 301                         clk_enable(mcbsp1_fck);
 302                 } else {
 303                         clk_enable(mcbsp2_ick);
 304                         clk_enable(mcbsp2_fck);
 305                 }
 306         }
 307 #endif
 308
 309         spin_lock(&mcbsp[id].lock);
 310         if (!mcbsp[id].free) {
 311                 printk(KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n",
 312                         id + 1);
 313                 spin_unlock(&mcbsp[id].lock);
 314                 return -1;
 315         }
 316
 317         mcbsp[id].free = 0;
 318         spin_unlock(&mcbsp[id].lock);
 319
 320         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 321                 /* We need to get IRQs here */
 322                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
 323                                         0, "McBSP", (void *) (&mcbsp[id]));
 324                 if (err != 0) {
 325                         printk(KERN_ERR "OMAP-McBSP: Unable to "
 326                                         "request TX IRQ %d for McBSP%d\n",
 327                                         mcbsp[id].tx_irq, mcbsp[id].id);
 328                         return err;
 329                 }
 330
 331                 init_completion(&(mcbsp[id].tx_irq_completion));
 332
 333                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
 334                                         0, "McBSP", (void *) (&mcbsp[id]));
 335                 if (err != 0) {
 336                         printk(KERN_ERR "OMAP-McBSP: Unable to "
 337                                         "request RX IRQ %d for McBSP%d\n",
 338                                         mcbsp[id].rx_irq, mcbsp[id].id);
 339                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 340                         return err;
 341                 }
 342
 343                 init_completion(&(mcbsp[id].rx_irq_completion));
 344         }
 345
 346         return 0;
 347 }
 348 EXPORT_SYMBOL(omap_mcbsp_request);
 349
 350 void omap_mcbsp_free(unsigned int id)
 351 {
 352         if (omap_mcbsp_check(id) < 0)
 353                 return;
 354
 355 #ifdef CONFIG_ARCH_OMAP1
 356         if (cpu_class_is_omap1()) {
 357                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 358                         omap_mcbsp_dsp_free();
 359         }
 360 #endif
 361
 362 #ifdef CONFIG_ARCH_OMAP2
 363         if (cpu_is_omap24xx()) {
 364                 if (id == OMAP_MCBSP1) {
 365                         clk_disable(mcbsp1_ick);
 366                         clk_disable(mcbsp1_fck);
 367                 } else {
 368                         clk_disable(mcbsp2_ick);
 369                         clk_disable(mcbsp2_fck);
 370                 }
 371         }
 372 #endif
 373
 374         spin_lock(&mcbsp[id].lock);
 375         if (mcbsp[id].free) {
 376                 printk(KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n",
 377                         id + 1);
 378                 spin_unlock(&mcbsp[id].lock);
 379                 return;
 380         }
 381
 382         mcbsp[id].free = 1;
 383         spin_unlock(&mcbsp[id].lock);
 384
 385         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 386                 /* Free IRQs */
 387                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 388                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 389         }
 390 }
 391 EXPORT_SYMBOL(omap_mcbsp_free);
 392
 393 /*
 394  * Here we start the McBSP, by enabling the sample
 395  * generator, both transmitter and receivers,
 396  * and the frame sync.
 397  */
 398 void omap_mcbsp_start(unsigned int id)
 399 {
 400         u32 io_base;
 401         u16 w;
 402
 403         if (omap_mcbsp_check(id) < 0)
 404                 return;
 405
 406         io_base = mcbsp[id].io_base;
 407
 408         mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 409         mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 410
 411         /* Start the sample generator */
 412         w = OMAP_MCBSP_READ(io_base, SPCR2);
 413         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 414
 415         /* Enable transmitter and receiver */
 416         w = OMAP_MCBSP_READ(io_base, SPCR2);
 417         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 418
 419         w = OMAP_MCBSP_READ(io_base, SPCR1);
 420         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 421
 422         udelay(100);
 423
 424         /* Start frame sync */
 425         w = OMAP_MCBSP_READ(io_base, SPCR2);
 426         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 427
 428         /* Dump McBSP Regs */
 429         omap_mcbsp_dump_reg(id);
 430 }
 431 EXPORT_SYMBOL(omap_mcbsp_start);
 432
 433 void omap_mcbsp_stop(unsigned int id)
 434 {
 435         u32 io_base;
 436         u16 w;
 437
 438         if (omap_mcbsp_check(id) < 0)
 439                 return;
 440
 441         io_base = mcbsp[id].io_base;
 442
 443         /* Reset transmitter */
 444         w = OMAP_MCBSP_READ(io_base, SPCR2);
 445         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 446
 447         /* Reset receiver */
 448         w = OMAP_MCBSP_READ(io_base, SPCR1);
 449         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 450
 451         /* Reset the sample rate generator */
 452         w = OMAP_MCBSP_READ(io_base, SPCR2);
 453         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 454 }
 455 EXPORT_SYMBOL(omap_mcbsp_stop);
 456
 457 /* polled mcbsp i/o operations */
 458 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 459 {
 460         u32 base = mcbsp[id].io_base;
 461         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 462         /* if frame sync error - clear the error */
 463         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 464                 /* clear error */
 465                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 466                        base + OMAP_MCBSP_REG_SPCR2);
 467                 /* resend */
 468                 return -1;
 469         } else {
 470                 /* wait for transmit confirmation */
 471                 int attemps = 0;
 472                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 473                         if (attemps++ > 1000) {
 474                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 475                                        (~XRST),
 476                                        base + OMAP_MCBSP_REG_SPCR2);
 477                                 udelay(10);
 478                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 479                                        (XRST),
 480                                        base + OMAP_MCBSP_REG_SPCR2);
 481                                 udelay(10);
 482                                 printk(KERN_ERR
 483                                        " Could not write to McBSP Register\n");
 484                                 return -2;
 485                         }
 486                 }
 487         }
 488
 489         return 0;
 490 }
 491 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 492
 493 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 494 {
 495         u32 base = mcbsp[id].io_base;
 496         /* if frame sync error - clear the error */
 497         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 498                 /* clear error */
 499                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 500                        base + OMAP_MCBSP_REG_SPCR1);
 501                 /* resend */
 502                 return -1;
 503         } else {
 504                 /* wait for recieve confirmation */
 505                 int attemps = 0;
 506                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 507                         if (attemps++ > 1000) {
 508                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 509                                        (~RRST),
 510                                        base + OMAP_MCBSP_REG_SPCR1);
 511                                 udelay(10);
 512                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 513                                        (RRST),
 514                                        base + OMAP_MCBSP_REG_SPCR1);
 515                                 udelay(10);
 516                                 printk(KERN_ERR
 517                                        " Could not read from McBSP Register\n");
 518                                 return -2;
 519                         }
 520                 }
 521         }
 522         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 523
 524         return 0;
 525 }
 526 EXPORT_SYMBOL(omap_mcbsp_pollread);
 527
 528 /*
 529  * IRQ based word transmission.
 530  */
 531 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 532 {
 533         u32 io_base;
 534         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 535
 536         if (omap_mcbsp_check(id) < 0)
 537                 return;
 538
 539         io_base = mcbsp[id].io_base;
 540
 541         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 542
 543         if (word_length > OMAP_MCBSP_WORD_16)
 544                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 545         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 546 }
 547 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 548
 549 u32 omap_mcbsp_recv_word(unsigned int id)
 550 {
 551         u32 io_base;
 552         u16 word_lsb, word_msb = 0;
 553         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 554
 555         if (omap_mcbsp_check(id) < 0)
 556                 return -EINVAL;
 557
 558         io_base = mcbsp[id].io_base;
 559
 560         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 561
 562         if (word_length > OMAP_MCBSP_WORD_16)
 563                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 564         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 565
 566         return (word_lsb | (word_msb << 16));
 567 }
 568 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 569
 570 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 571 {
 572         u32 io_base = mcbsp[id].io_base;
 573         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 574         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 575         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 576
 577         if (tx_word_length != rx_word_length)
 578                 return -EINVAL;
 579
 580         /* First we wait for the transmitter to be ready */
 581         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 582         while (!(spcr2 & XRDY)) {
 583                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 584                 if (attempts++ > 1000) {
 585                         /* We must reset the transmitter */
 586                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 587                         udelay(10);
 588                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 589                         udelay(10);
 590                         printk(KERN_ERR "McBSP transmitter not ready\n");
 591                         return -EAGAIN;
 592                 }
 593         }
 594
 595         /* Now we can push the data */
 596         if (tx_word_length > OMAP_MCBSP_WORD_16)
 597                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 598         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 599
 600         /* We wait for the receiver to be ready */
 601         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 602         while (!(spcr1 & RRDY)) {
 603                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 604                 if (attempts++ > 1000) {
 605                         /* We must reset the receiver */
 606                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 607                         udelay(10);
 608                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 609                         udelay(10);
 610                         printk(KERN_ERR "McBSP receiver not ready\n");
 611                         return -EAGAIN;
 612                 }
 613         }
 614
 615         /* Receiver is ready, let's read the dummy data */
 616         if (rx_word_length > OMAP_MCBSP_WORD_16)
 617                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 618         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 619
 620         return 0;
 621 }
 622 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 623
 624 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 625 {
 626         u32 io_base = mcbsp[id].io_base, clock_word = 0;
 627         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 628         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 629         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 630
 631         if (tx_word_length != rx_word_length)
 632                 return -EINVAL;
 633
 634         /* First we wait for the transmitter to be ready */
 635         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 636         while (!(spcr2 & XRDY)) {
 637                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 638                 if (attempts++ > 1000) {
 639                         /* We must reset the transmitter */
 640                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 641                         udelay(10);
 642                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 643                         udelay(10);
 644                         printk(KERN_ERR "McBSP transmitter not ready\n");
 645                         return -EAGAIN;
 646                 }
 647         }
 648
 649         /* We first need to enable the bus clock */
 650         if (tx_word_length > OMAP_MCBSP_WORD_16)
 651                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 652         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 653
 654         /* We wait for the receiver to be ready */
 655         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 656         while (!(spcr1 & RRDY)) {
 657                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 658                 if (attempts++ > 1000) {
 659                         /* We must reset the receiver */
 660                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 661                         udelay(10);
 662                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 663                         udelay(10);
 664                         printk(KERN_ERR "McBSP receiver not ready\n");
 665                         return -EAGAIN;
 666                 }
 667         }
 668
 669         /* Receiver is ready, there is something for us */
 670         if (rx_word_length > OMAP_MCBSP_WORD_16)
 671                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 672         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 673
 674         word[0] = (word_lsb | (word_msb << 16));
 675
 676         return 0;
 677 }
 678 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 679
 680 /*
 681  * Simple DMA based buffer rx/tx routines.
 682  * Nothing fancy, just a single buffer tx/rx through DMA.
 683  * The DMA resources are released once the transfer is done.
 684  * For anything fancier, you should use your own customized DMA
 685  * routines and callbacks.
 686  */
 687 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 688                                 unsigned int length)
 689 {
 690         int dma_tx_ch;
 691         int src_port = 0;
 692         int dest_port = 0;
 693         int sync_dev = 0;
 694
 695         if (omap_mcbsp_check(id) < 0)
 696                 return -EINVAL;
 697
 698         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
 699                                 omap_mcbsp_tx_dma_callback,
 700                                 &mcbsp[id],
 701                                 &dma_tx_ch)) {
 702                 printk(KERN_ERR "OMAP-McBSP: Unable to request DMA channel for"
 703                                 " McBSP%d TX. Trying IRQ based TX\n", id + 1);
 704                 return -EAGAIN;
 705         }
 706         mcbsp[id].dma_tx_lch = dma_tx_ch;
 707
 708         DBG("TX DMA on channel %d\n", dma_tx_ch);
 709
 710         init_completion(&(mcbsp[id].tx_dma_completion));
 711
 712         if (cpu_class_is_omap1()) {
 713                 src_port = OMAP_DMA_PORT_TIPB;
 714                 dest_port = OMAP_DMA_PORT_EMIFF;
 715         }
 716         if (cpu_is_omap24xx())
 717                 sync_dev = mcbsp[id].dma_tx_sync;
 718
 719         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 720                                      OMAP_DMA_DATA_TYPE_S16,
 721                                      length >> 1, 1,
 722                                      OMAP_DMA_SYNC_ELEMENT,
 723          sync_dev, 0);
 724
 725         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 726                                  src_port,
 727                                  OMAP_DMA_AMODE_CONSTANT,
 728                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 729                                  0, 0);
 730
 731         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 732                                 dest_port,
 733                                 OMAP_DMA_AMODE_POST_INC,
 734                                 buffer,
 735                                 0, 0);
 736
 737         omap_start_dma(mcbsp[id].dma_tx_lch);
 738         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 739
 740         return 0;
 741 }
 742 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 743
 744 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 745                                 unsigned int length)
 746 {
 747         int dma_rx_ch;
 748         int src_port = 0;
 749         int dest_port = 0;
 750         int sync_dev = 0;
 751
 752         if (omap_mcbsp_check(id) < 0)
 753                 return -EINVAL;
 754
 755         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
 756                                 omap_mcbsp_rx_dma_callback,
 757                                 &mcbsp[id],
 758                                 &dma_rx_ch)) {
 759                 printk(KERN_ERR "Unable to request DMA channel for McBSP%d RX."
 760                                 " Trying IRQ based RX\n", id + 1);
 761                 return -EAGAIN;
 762         }
 763         mcbsp[id].dma_rx_lch = dma_rx_ch;
 764
 765         DBG("RX DMA on channel %d\n", dma_rx_ch);
 766
 767         init_completion(&(mcbsp[id].rx_dma_completion));
 768
 769         if (cpu_class_is_omap1()) {
 770                 src_port = OMAP_DMA_PORT_TIPB;
 771                 dest_port = OMAP_DMA_PORT_EMIFF;
 772         }
 773         if (cpu_is_omap24xx())
 774                 sync_dev = mcbsp[id].dma_rx_sync;
 775
 776         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 777                                         OMAP_DMA_DATA_TYPE_S16,
 778                                         length >> 1, 1,
 779                                         OMAP_DMA_SYNC_ELEMENT,
 780                                         sync_dev, 0);
 781
 782         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 783                                 src_port,
 784                                 OMAP_DMA_AMODE_CONSTANT,
 785                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 786                                 0, 0);
 787
 788         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 789                                         dest_port,
 790                                         OMAP_DMA_AMODE_POST_INC,
 791                                         buffer,
 792                                         0, 0);
 793
 794         omap_start_dma(mcbsp[id].dma_rx_lch);
 795         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 796
 797         return 0;
 798 }
 799 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
 800
 801 /*
 802  * SPI wrapper.
 803  * Since SPI setup is much simpler than the generic McBSP one,
 804  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 805  * Once this is done, you can call omap_mcbsp_start().
 806  */
 807 void omap_mcbsp_set_spi_mode(unsigned int id,
 808                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
 809 {
 810         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 811
 812         if (omap_mcbsp_check(id) < 0)
 813                 return;
 814
 815         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 816
 817         /* SPI has only one frame */
 818         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 819         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 820
 821         /* Clock stop mode */
 822         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 823                 mcbsp_cfg.spcr1 |= (1 << 12);
 824         else
 825                 mcbsp_cfg.spcr1 |= (3 << 11);
 826
 827         /* Set clock parities */
 828         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 829                 mcbsp_cfg.pcr0 |= CLKRP;
 830         else
 831                 mcbsp_cfg.pcr0 &= ~CLKRP;
 832
 833         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 834                 mcbsp_cfg.pcr0 &= ~CLKXP;
 835         else
 836                 mcbsp_cfg.pcr0 |= CLKXP;
 837
 838         /* Set SCLKME to 0 and CLKSM to 1 */
 839         mcbsp_cfg.pcr0 &= ~SCLKME;
 840         mcbsp_cfg.srgr2 |= CLKSM;
 841
 842         /* Set FSXP */
 843         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 844                 mcbsp_cfg.pcr0 &= ~FSXP;
 845         else
 846                 mcbsp_cfg.pcr0 |= FSXP;
 847
 848         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 849                 mcbsp_cfg.pcr0 |= CLKXM;
 850                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
 851                 mcbsp_cfg.pcr0 |= FSXM;
 852                 mcbsp_cfg.srgr2 &= ~FSGM;
 853                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 854                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 855         } else {
 856                 mcbsp_cfg.pcr0 &= ~CLKXM;
 857                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 858                 mcbsp_cfg.pcr0 &= ~FSXM;
 859                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 860                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 861         }
 862
 863         mcbsp_cfg.xcr2 &= ~XPHASE;
 864         mcbsp_cfg.rcr2 &= ~RPHASE;
 865
 866         omap_mcbsp_config(id, &mcbsp_cfg);
 867 }
 868 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 869
 870 /*
 871  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 872  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 873  */
 874 struct omap_mcbsp_info {
 875         u32 virt_base;
 876         u8 dma_rx_sync, dma_tx_sync;
 877         u16 rx_irq, tx_irq;
 878 };
 879
 880 #ifdef CONFIG_ARCH_OMAP730
 881 static const struct omap_mcbsp_info mcbsp_730[] = {
 882         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 883                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 884                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 885                 .rx_irq = INT_730_McBSP1RX,
 886                 .tx_irq = INT_730_McBSP1TX },
 887         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 888                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 889                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 890                 .rx_irq = INT_730_McBSP2RX,
 891                 .tx_irq = INT_730_McBSP2TX },
 892 };
 893 #endif
 894
 895 #ifdef CONFIG_ARCH_OMAP15XX
 896 static const struct omap_mcbsp_info mcbsp_1510[] = {
 897         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 898                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 899                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 900                 .rx_irq = INT_McBSP1RX,
 901                 .tx_irq = INT_McBSP1TX },
 902         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 903                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 904                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 905                 .rx_irq = INT_1510_SPI_RX,
 906                 .tx_irq = INT_1510_SPI_TX },
 907         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 908                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 909                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 910                 .rx_irq = INT_McBSP3RX,
 911                 .tx_irq = INT_McBSP3TX },
 912 };
 913 #endif
 914
 915 #if defined(CONFIG_ARCH_OMAP16XX)
 916 static const struct omap_mcbsp_info mcbsp_1610[] = {
 917         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 918                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 919                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 920                 .rx_irq = INT_McBSP1RX,
 921                 .tx_irq = INT_McBSP1TX },
 922         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 923                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 924                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 925                 .rx_irq = INT_1610_McBSP2_RX,
 926                 .tx_irq = INT_1610_McBSP2_TX },
 927         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 928                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 929                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 930                 .rx_irq = INT_McBSP3RX,
 931                 .tx_irq = INT_McBSP3TX },
 932 };
 933 #endif
 934
 935 #if defined(CONFIG_ARCH_OMAP24XX)
 936 static const struct omap_mcbsp_info mcbsp_24xx[] = {
 937         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
 938                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
 939                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
 940                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
 941                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
 942                 },
 943         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
 944                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
 945                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
 946                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
 947                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
 948                 },
 949 };
 950 #endif
 951
 952 static int __init omap_mcbsp_init(void)
 953 {
 954         int mcbsp_count = 0, i;
 955         static const struct omap_mcbsp_info *mcbsp_info;
 956
 957         printk(KERN_INFO "Initializing OMAP McBSP system\n");
 958
 959 #ifdef CONFIG_ARCH_OMAP1
 960         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 961         if (IS_ERR(mcbsp_dsp_ck)) {
 962                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 963                 return PTR_ERR(mcbsp_dsp_ck);
 964         }
 965         mcbsp_api_ck = clk_get(0, "api_ck");
 966         if (IS_ERR(mcbsp_api_ck)) {
 967                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 968                 return PTR_ERR(mcbsp_api_ck);
 969         }
 970         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 971         if (IS_ERR(mcbsp_dspxor_ck)) {
 972                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 973                 return PTR_ERR(mcbsp_dspxor_ck);
 974         }
 975 #endif
 976 #ifdef CONFIG_ARCH_OMAP2
 977         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
 978         if (IS_ERR(mcbsp1_ick)) {
 979                 printk(KERN_ERR "mcbsp: could not acquire "
 980                                 "mcbsp1_ick handle.\n");
 981                 return PTR_ERR(mcbsp1_ick);
 982         }
 983         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
 984         if (IS_ERR(mcbsp1_fck)) {
 985                 printk(KERN_ERR "mcbsp: could not acquire "
 986                                 "mcbsp1_fck handle.\n");
 987                 return PTR_ERR(mcbsp1_fck);
 988         }
 989         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
 990         if (IS_ERR(mcbsp2_ick)) {
 991                 printk(KERN_ERR "mcbsp: could not acquire "
 992                                 "mcbsp2_ick handle.\n");
 993                 return PTR_ERR(mcbsp2_ick);
 994         }
 995         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
 996         if (IS_ERR(mcbsp2_fck)) {
 997                 printk(KERN_ERR "mcbsp: could not acquire "
 998                                 "mcbsp2_fck handle.\n");
 999                 return PTR_ERR(mcbsp2_fck);
1000         }
1001 #endif
1002
1003 #ifdef CONFIG_ARCH_OMAP730
1004         if (cpu_is_omap730()) {
1005                 mcbsp_info = mcbsp_730;
1006                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
1007         }
1008 #endif
1009 #ifdef CONFIG_ARCH_OMAP15XX
1010         if (cpu_is_omap15xx()) {
1011                 mcbsp_info = mcbsp_1510;
1012                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
1013         }
1014 #endif
1015 #if defined(CONFIG_ARCH_OMAP16XX)
1016         if (cpu_is_omap16xx()) {
1017                 mcbsp_info = mcbsp_1610;
1018                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
1019         }
1020 #endif
1021 #if defined(CONFIG_ARCH_OMAP24XX)
1022         if (cpu_is_omap24xx()) {
1023                 mcbsp_info = mcbsp_24xx;
1024                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
1025                 omap2_mcbsp2_mux_setup();
1026         }
1027 #endif
1028         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
1029                 if (i >= mcbsp_count) {
1030                         mcbsp[i].io_base = 0;
1031                         mcbsp[i].free = 0;
1032                         continue;
1033                 }
1034                 mcbsp[i].id = i + 1;
1035                 mcbsp[i].free = 1;
1036                 mcbsp[i].dma_tx_lch = -1;
1037                 mcbsp[i].dma_rx_lch = -1;
1038
1039                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1040                 /* Default I/O is IRQ based */
1041                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO;
1042                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1043                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1044                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1045                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1046                 spin_lock_init(&mcbsp[i].lock);
1047         }
1048
1049         return 0;
1050 }
1051
1052 arch_initcall(omap_mcbsp_init);