2 * arch/arm/plat-omap/include/mach/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
14 #define __ARCH_ARM_OMAP_CLOCK_H
20 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
30 const struct clksel_rate *rates;
34 void __iomem *mult_div1_reg;
39 unsigned long last_rounded_rate;
40 unsigned int rate_tolerance;
44 # if defined(CONFIG_ARCH_OMAP3)
47 void __iomem *control_reg;
52 void __iomem *autoidle_reg;
54 void __iomem *idlest_reg;
62 struct list_head node;
69 void __iomem *enable_reg;
72 void (*recalc)(struct clk *);
73 int (*set_rate)(struct clk *, unsigned long);
74 long (*round_rate)(struct clk *, unsigned long);
75 void (*init)(struct clk *);
76 int (*enable)(struct clk *);
77 void (*disable)(struct clk *);
78 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
80 void __iomem *clksel_reg;
82 const struct clksel *clksel;
83 struct dpll_data *dpll_data;
86 struct clockdomain *ptr;
92 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
93 struct dentry *dent; /* For visible tree hierarchy */
97 struct cpufreq_frequency_table;
99 struct clk_functions {
100 int (*clk_enable)(struct clk *clk);
101 void (*clk_disable)(struct clk *clk);
102 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
103 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
104 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
105 struct clk * (*clk_get_parent)(struct clk *clk);
106 void (*clk_allow_idle)(struct clk *clk);
107 void (*clk_deny_idle)(struct clk *clk);
108 void (*clk_disable_unused)(struct clk *clk);
109 #ifdef CONFIG_CPU_FREQ
110 void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
114 extern unsigned int mpurate;
116 extern int clk_init(struct clk_functions *custom_clocks);
117 extern int clk_register(struct clk *clk);
118 extern void clk_unregister(struct clk *clk);
119 extern void propagate_rate(struct clk *clk);
120 extern void recalculate_root_clocks(void);
121 extern void followparent_recalc(struct clk *clk);
122 extern void clk_allow_idle(struct clk *clk);
123 extern void clk_deny_idle(struct clk *clk);
124 extern int clk_get_usecount(struct clk *clk);
125 extern void clk_enable_init_clocks(void);
126 #ifdef CONFIG_CPU_FREQ
127 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
131 #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
132 #define RATE_FIXED (1 << 1) /* Fixed clock rate */
133 #define RATE_PROPAGATES (1 << 2) /* Program children too */
134 #define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
135 #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
136 #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
137 #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
138 #define CLOCK_IDLE_CONTROL (1 << 7)
139 #define CLOCK_NO_IDLE_PARENT (1 << 8)
140 #define DELAYED_APP (1 << 9) /* Delay application of clock */
141 #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
142 #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
143 #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
144 #define OFFSET_GR_MOD (1 << 13) /* 24xx GR_MOD reg as offset */
145 /* bits 14-20 are currently free */
146 #define CLOCK_IN_OMAP310 (1 << 21)
147 #define CLOCK_IN_OMAP730 (1 << 22)
148 #define CLOCK_IN_OMAP1510 (1 << 23)
149 #define CLOCK_IN_OMAP16XX (1 << 24)
150 #define CLOCK_IN_OMAP242X (1 << 25)
151 #define CLOCK_IN_OMAP243X (1 << 26)
152 #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
153 #define PARENT_CONTROLS_CLOCK (1 << 28)
154 #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
155 #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
157 /* Clksel_rate flags */
158 #define DEFAULT_RATE (1 << 0)
159 #define RATE_IN_242X (1 << 1)
160 #define RATE_IN_243X (1 << 2)
161 #define RATE_IN_343X (1 << 3) /* rates common to all 343X */
162 #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
164 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
167 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
168 #define CORE_CLK_SRC_32K 0
169 #define CORE_CLK_SRC_DPLL 1
170 #define CORE_CLK_SRC_DPLL_X2 2