2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <asm/hardware.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * omap24xx specific GPIO registers
89 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP24XX_GPIO_REVISION 0x0000
94 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
95 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
96 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
98 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
99 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
100 #define OMAP24XX_GPIO_CTRL 0x0030
101 #define OMAP24XX_GPIO_OE 0x0034
102 #define OMAP24XX_GPIO_DATAIN 0x0038
103 #define OMAP24XX_GPIO_DATAOUT 0x003c
104 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
105 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
106 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
107 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
108 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
109 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
110 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
111 #define OMAP24XX_GPIO_SETWKUENA 0x0084
112 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
113 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
118 u16 virtual_irq_start;
121 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
125 #ifdef CONFIG_ARCH_OMAP24XX
126 u32 non_wakeup_gpios;
127 u32 enabled_non_wakeup_gpios;
130 u32 saved_fallingdetect;
131 u32 saved_risingdetect;
136 #define METHOD_MPUIO 0
137 #define METHOD_GPIO_1510 1
138 #define METHOD_GPIO_1610 2
139 #define METHOD_GPIO_730 3
140 #define METHOD_GPIO_24XX 4
142 #ifdef CONFIG_ARCH_OMAP16XX
143 static struct gpio_bank gpio_bank_1610[5] = {
144 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
145 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
146 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
147 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
148 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
152 #ifdef CONFIG_ARCH_OMAP15XX
153 static struct gpio_bank gpio_bank_1510[2] = {
154 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
155 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
159 #ifdef CONFIG_ARCH_OMAP730
160 static struct gpio_bank gpio_bank_730[7] = {
161 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
162 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
163 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
164 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
165 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
166 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
167 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
171 #ifdef CONFIG_ARCH_OMAP24XX
172 static struct gpio_bank gpio_bank_24xx[4] = {
173 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
174 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
175 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
176 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
180 static struct gpio_bank *gpio_bank;
181 static int gpio_bank_count;
183 static inline struct gpio_bank *get_gpio_bank(int gpio)
185 #ifdef CONFIG_ARCH_OMAP15XX
186 if (cpu_is_omap15xx()) {
187 if (OMAP_GPIO_IS_MPUIO(gpio))
188 return &gpio_bank[0];
189 return &gpio_bank[1];
192 #if defined(CONFIG_ARCH_OMAP16XX)
193 if (cpu_is_omap16xx()) {
194 if (OMAP_GPIO_IS_MPUIO(gpio))
195 return &gpio_bank[0];
196 return &gpio_bank[1 + (gpio >> 4)];
199 #ifdef CONFIG_ARCH_OMAP730
200 if (cpu_is_omap730()) {
201 if (OMAP_GPIO_IS_MPUIO(gpio))
202 return &gpio_bank[0];
203 return &gpio_bank[1 + (gpio >> 5)];
206 #ifdef CONFIG_ARCH_OMAP24XX
207 if (cpu_is_omap24xx())
208 return &gpio_bank[gpio >> 5];
212 static inline int get_gpio_index(int gpio)
214 #ifdef CONFIG_ARCH_OMAP730
215 if (cpu_is_omap730())
218 #ifdef CONFIG_ARCH_OMAP24XX
219 if (cpu_is_omap24xx())
225 static inline int gpio_valid(int gpio)
229 #ifndef CONFIG_ARCH_OMAP24XX
230 if (OMAP_GPIO_IS_MPUIO(gpio)) {
231 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
236 #ifdef CONFIG_ARCH_OMAP15XX
237 if (cpu_is_omap15xx() && gpio < 16)
240 #if defined(CONFIG_ARCH_OMAP16XX)
241 if ((cpu_is_omap16xx()) && gpio < 64)
244 #ifdef CONFIG_ARCH_OMAP730
245 if (cpu_is_omap730() && gpio < 192)
248 #ifdef CONFIG_ARCH_OMAP24XX
249 if (cpu_is_omap24xx() && gpio < 128)
255 static int check_gpio(int gpio)
257 if (unlikely(gpio_valid(gpio)) < 0) {
258 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
265 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
267 void __iomem *reg = bank->base;
270 switch (bank->method) {
272 reg += OMAP_MPUIO_IO_CNTL;
274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
277 case METHOD_GPIO_1610:
278 reg += OMAP1610_GPIO_DIRECTION;
280 case METHOD_GPIO_730:
281 reg += OMAP730_GPIO_DIR_CONTROL;
283 case METHOD_GPIO_24XX:
284 reg += OMAP24XX_GPIO_OE;
287 l = __raw_readl(reg);
292 __raw_writel(l, reg);
295 void omap_set_gpio_direction(int gpio, int is_input)
297 struct gpio_bank *bank;
299 if (check_gpio(gpio) < 0)
301 bank = get_gpio_bank(gpio);
302 spin_lock(&bank->lock);
303 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
304 spin_unlock(&bank->lock);
307 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
309 void __iomem *reg = bank->base;
312 switch (bank->method) {
314 reg += OMAP_MPUIO_OUTPUT;
315 l = __raw_readl(reg);
321 case METHOD_GPIO_1510:
322 reg += OMAP1510_GPIO_DATA_OUTPUT;
323 l = __raw_readl(reg);
329 case METHOD_GPIO_1610:
331 reg += OMAP1610_GPIO_SET_DATAOUT;
333 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
336 case METHOD_GPIO_730:
337 reg += OMAP730_GPIO_DATA_OUTPUT;
338 l = __raw_readl(reg);
344 case METHOD_GPIO_24XX:
346 reg += OMAP24XX_GPIO_SETDATAOUT;
348 reg += OMAP24XX_GPIO_CLEARDATAOUT;
355 __raw_writel(l, reg);
358 void omap_set_gpio_dataout(int gpio, int enable)
360 struct gpio_bank *bank;
362 if (check_gpio(gpio) < 0)
364 bank = get_gpio_bank(gpio);
365 spin_lock(&bank->lock);
366 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
367 spin_unlock(&bank->lock);
370 int omap_get_gpio_datain(int gpio)
372 struct gpio_bank *bank;
375 if (check_gpio(gpio) < 0)
377 bank = get_gpio_bank(gpio);
379 switch (bank->method) {
381 reg += OMAP_MPUIO_INPUT_LATCH;
383 case METHOD_GPIO_1510:
384 reg += OMAP1510_GPIO_DATA_INPUT;
386 case METHOD_GPIO_1610:
387 reg += OMAP1610_GPIO_DATAIN;
389 case METHOD_GPIO_730:
390 reg += OMAP730_GPIO_DATA_INPUT;
392 case METHOD_GPIO_24XX:
393 reg += OMAP24XX_GPIO_DATAIN;
399 return (__raw_readl(reg)
400 & (1 << get_gpio_index(gpio))) != 0;
403 #define MOD_REG_BIT(reg, bit_mask, set) \
405 int l = __raw_readl(base + reg); \
406 if (set) l |= bit_mask; \
407 else l &= ~bit_mask; \
408 __raw_writel(l, base + reg); \
411 #ifdef CONFIG_ARCH_OMAP24XX
412 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
414 void __iomem *base = bank->base;
415 u32 gpio_bit = 1 << gpio;
417 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
418 trigger & __IRQT_LOWLVL);
419 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
420 trigger & __IRQT_HIGHLVL);
421 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
422 trigger & __IRQT_RISEDGE);
423 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
424 trigger & __IRQT_FALEDGE);
425 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
427 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
429 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
432 bank->enabled_non_wakeup_gpios |= gpio_bit;
434 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
436 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
437 * triggering requested. */
441 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
443 void __iomem *reg = bank->base;
446 switch (bank->method) {
448 reg += OMAP_MPUIO_GPIO_INT_EDGE;
449 l = __raw_readl(reg);
450 if (trigger & __IRQT_RISEDGE)
452 else if (trigger & __IRQT_FALEDGE)
457 case METHOD_GPIO_1510:
458 reg += OMAP1510_GPIO_INT_CONTROL;
459 l = __raw_readl(reg);
460 if (trigger & __IRQT_RISEDGE)
462 else if (trigger & __IRQT_FALEDGE)
467 #ifdef CONFIG_ARCH_OMAP16XX
468 case METHOD_GPIO_1610:
470 reg += OMAP1610_GPIO_EDGE_CTRL2;
472 reg += OMAP1610_GPIO_EDGE_CTRL1;
474 /* We allow only edge triggering, i.e. two lowest bits */
475 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
477 l = __raw_readl(reg);
478 l &= ~(3 << (gpio << 1));
479 if (trigger & __IRQT_RISEDGE)
480 l |= 2 << (gpio << 1);
481 if (trigger & __IRQT_FALEDGE)
482 l |= 1 << (gpio << 1);
484 /* Enable wake-up during idle for dynamic tick */
485 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
487 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
490 #ifdef CONFIG_ARCH_OMAP730
491 case METHOD_GPIO_730:
492 reg += OMAP730_GPIO_INT_CONTROL;
493 l = __raw_readl(reg);
494 if (trigger & __IRQT_RISEDGE)
496 else if (trigger & __IRQT_FALEDGE)
502 #ifdef CONFIG_ARCH_OMAP24XX
503 case METHOD_GPIO_24XX:
504 set_24xx_gpio_triggering(bank, gpio, trigger);
511 __raw_writel(l, reg);
517 static int gpio_irq_type(unsigned irq, unsigned type)
519 struct gpio_bank *bank;
523 if (irq > IH_MPUIO_BASE)
524 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
526 gpio = irq - IH_GPIO_BASE;
528 if (check_gpio(gpio) < 0)
531 if (type & IRQT_PROBE)
533 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
536 bank = get_gpio_bank(gpio);
537 spin_lock(&bank->lock);
538 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
539 spin_unlock(&bank->lock);
543 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
545 void __iomem *reg = bank->base;
547 switch (bank->method) {
549 /* MPUIO irqstatus is reset by reading the status register,
550 * so do nothing here */
552 case METHOD_GPIO_1510:
553 reg += OMAP1510_GPIO_INT_STATUS;
555 case METHOD_GPIO_1610:
556 reg += OMAP1610_GPIO_IRQSTATUS1;
558 case METHOD_GPIO_730:
559 reg += OMAP730_GPIO_INT_STATUS;
561 case METHOD_GPIO_24XX:
562 reg += OMAP24XX_GPIO_IRQSTATUS1;
568 __raw_writel(gpio_mask, reg);
570 /* Workaround for clearing DSP GPIO interrupts to allow retention */
571 if (cpu_is_omap2420())
572 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
575 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
577 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
580 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
582 void __iomem *reg = bank->base;
587 switch (bank->method) {
589 reg += OMAP_MPUIO_GPIO_MASKIT;
593 case METHOD_GPIO_1510:
594 reg += OMAP1510_GPIO_INT_MASK;
598 case METHOD_GPIO_1610:
599 reg += OMAP1610_GPIO_IRQENABLE1;
602 case METHOD_GPIO_730:
603 reg += OMAP730_GPIO_INT_MASK;
607 case METHOD_GPIO_24XX:
608 reg += OMAP24XX_GPIO_IRQENABLE1;
616 l = __raw_readl(reg);
623 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
625 void __iomem *reg = bank->base;
628 switch (bank->method) {
630 reg += OMAP_MPUIO_GPIO_MASKIT;
631 l = __raw_readl(reg);
637 case METHOD_GPIO_1510:
638 reg += OMAP1510_GPIO_INT_MASK;
639 l = __raw_readl(reg);
645 case METHOD_GPIO_1610:
647 reg += OMAP1610_GPIO_SET_IRQENABLE1;
649 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
652 case METHOD_GPIO_730:
653 reg += OMAP730_GPIO_INT_MASK;
654 l = __raw_readl(reg);
660 case METHOD_GPIO_24XX:
662 reg += OMAP24XX_GPIO_SETIRQENABLE1;
664 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
671 __raw_writel(l, reg);
674 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
676 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
680 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
681 * 1510 does not seem to have a wake-up register. If JTAG is connected
682 * to the target, system will wake up always on GPIO events. While
683 * system is running all registered GPIO interrupts need to have wake-up
684 * enabled. When system is suspended, only selected GPIO interrupts need
685 * to have wake-up enabled.
687 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
689 switch (bank->method) {
690 #ifdef CONFIG_ARCH_OMAP16XX
691 case METHOD_GPIO_1610:
692 spin_lock(&bank->lock);
694 bank->suspend_wakeup |= (1 << gpio);
696 bank->suspend_wakeup &= ~(1 << gpio);
697 spin_unlock(&bank->lock);
700 #ifdef CONFIG_ARCH_OMAP24XX
701 case METHOD_GPIO_24XX:
702 spin_lock(&bank->lock);
704 if (bank->non_wakeup_gpios & (1 << gpio)) {
705 printk(KERN_ERR "Unable to enable wakeup on"
706 "non-wakeup GPIO%d\n",
707 (bank - gpio_bank) * 32 + gpio);
708 spin_unlock(&bank->lock);
711 bank->suspend_wakeup |= (1 << gpio);
713 bank->suspend_wakeup &= ~(1 << gpio);
714 spin_unlock(&bank->lock);
718 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
724 static void _reset_gpio(struct gpio_bank *bank, int gpio)
726 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
727 _set_gpio_irqenable(bank, gpio, 0);
728 _clear_gpio_irqstatus(bank, gpio);
729 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
732 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
733 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
735 unsigned int gpio = irq - IH_GPIO_BASE;
736 struct gpio_bank *bank;
739 if (check_gpio(gpio) < 0)
741 bank = get_gpio_bank(gpio);
742 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
747 int omap_request_gpio(int gpio)
749 struct gpio_bank *bank;
751 if (check_gpio(gpio) < 0)
754 bank = get_gpio_bank(gpio);
755 spin_lock(&bank->lock);
756 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
757 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
759 spin_unlock(&bank->lock);
762 bank->reserved_map |= (1 << get_gpio_index(gpio));
764 /* Set trigger to none. You need to enable the desired trigger with
765 * request_irq() or set_irq_type().
767 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
769 #ifdef CONFIG_ARCH_OMAP15XX
770 if (bank->method == METHOD_GPIO_1510) {
773 /* Claim the pin for MPU */
774 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
775 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
778 spin_unlock(&bank->lock);
783 void omap_free_gpio(int gpio)
785 struct gpio_bank *bank;
787 if (check_gpio(gpio) < 0)
789 bank = get_gpio_bank(gpio);
790 spin_lock(&bank->lock);
791 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
792 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
794 spin_unlock(&bank->lock);
797 #ifdef CONFIG_ARCH_OMAP16XX
798 if (bank->method == METHOD_GPIO_1610) {
799 /* Disable wake-up during idle for dynamic tick */
800 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
801 __raw_writel(1 << get_gpio_index(gpio), reg);
804 #ifdef CONFIG_ARCH_OMAP24XX
805 if (bank->method == METHOD_GPIO_24XX) {
806 /* Disable wake-up during idle for dynamic tick */
807 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
808 __raw_writel(1 << get_gpio_index(gpio), reg);
811 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
812 _reset_gpio(bank, gpio);
813 spin_unlock(&bank->lock);
817 * We need to unmask the GPIO bank interrupt as soon as possible to
818 * avoid missing GPIO interrupts for other lines in the bank.
819 * Then we need to mask-read-clear-unmask the triggered GPIO lines
820 * in the bank to avoid missing nested interrupts for a GPIO line.
821 * If we wait to unmask individual GPIO lines in the bank after the
822 * line's interrupt handler has been run, we may miss some nested
825 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
827 void __iomem *isr_reg = NULL;
829 unsigned int gpio_irq;
830 struct gpio_bank *bank;
834 desc->chip->ack(irq);
836 bank = get_irq_data(irq);
837 if (bank->method == METHOD_MPUIO)
838 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
839 #ifdef CONFIG_ARCH_OMAP15XX
840 if (bank->method == METHOD_GPIO_1510)
841 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
843 #if defined(CONFIG_ARCH_OMAP16XX)
844 if (bank->method == METHOD_GPIO_1610)
845 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
847 #ifdef CONFIG_ARCH_OMAP730
848 if (bank->method == METHOD_GPIO_730)
849 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
851 #ifdef CONFIG_ARCH_OMAP24XX
852 if (bank->method == METHOD_GPIO_24XX)
853 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
856 u32 isr_saved, level_mask = 0;
859 enabled = _get_gpio_irqbank_mask(bank);
860 isr_saved = isr = __raw_readl(isr_reg) & enabled;
862 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
865 if (cpu_is_omap24xx()) {
867 __raw_readl(bank->base +
868 OMAP24XX_GPIO_LEVELDETECT0) |
869 __raw_readl(bank->base +
870 OMAP24XX_GPIO_LEVELDETECT1);
871 level_mask &= enabled;
874 /* clear edge sensitive interrupts before handler(s) are
875 called so that we don't miss any interrupt occurred while
877 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
878 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
879 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
881 /* if there is only edge sensitive GPIO pin interrupts
882 configured, we could unmask GPIO bank interrupt immediately */
883 if (!level_mask && !unmasked) {
885 desc->chip->unmask(irq);
893 gpio_irq = bank->virtual_irq_start;
894 for (; isr != 0; isr >>= 1, gpio_irq++) {
899 d = irq_desc + gpio_irq;
900 /* Don't run the handler if it's already running
901 * or was disabled lazely.
903 if (unlikely((d->depth ||
904 (d->status & IRQ_INPROGRESS)))) {
906 (gpio_irq - bank->virtual_irq_start);
907 /* The unmasking will be done by
908 * enable_irq in case it is disabled or
909 * after returning from the handler if
910 * it's already running.
912 _enable_gpio_irqbank(bank, irq_mask, 0);
914 /* Level triggered interrupts
915 * won't ever be reentered
917 BUG_ON(level_mask & irq_mask);
918 d->status |= IRQ_PENDING;
923 desc_handle_irq(gpio_irq, d);
925 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
927 (gpio_irq - bank->virtual_irq_start);
928 d->status &= ~IRQ_PENDING;
929 _enable_gpio_irqbank(bank, irq_mask, 1);
930 retrigger |= irq_mask;
934 if (cpu_is_omap24xx()) {
935 /* clear level sensitive interrupts after handler(s) */
936 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
937 _clear_gpio_irqbank(bank, isr_saved & level_mask);
938 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
942 /* if bank has any level sensitive GPIO pin interrupt
943 configured, we must unmask the bank interrupt only after
944 handler(s) are executed in order to avoid spurious bank
947 desc->chip->unmask(irq);
951 static void gpio_irq_shutdown(unsigned int irq)
953 unsigned int gpio = irq - IH_GPIO_BASE;
954 struct gpio_bank *bank = get_gpio_bank(gpio);
956 _reset_gpio(bank, gpio);
959 static void gpio_ack_irq(unsigned int irq)
961 unsigned int gpio = irq - IH_GPIO_BASE;
962 struct gpio_bank *bank = get_gpio_bank(gpio);
964 _clear_gpio_irqstatus(bank, gpio);
967 static void gpio_mask_irq(unsigned int irq)
969 unsigned int gpio = irq - IH_GPIO_BASE;
970 struct gpio_bank *bank = get_gpio_bank(gpio);
972 _set_gpio_irqenable(bank, gpio, 0);
975 static void gpio_unmask_irq(unsigned int irq)
977 unsigned int gpio = irq - IH_GPIO_BASE;
978 unsigned int gpio_idx = get_gpio_index(gpio);
979 struct gpio_bank *bank = get_gpio_bank(gpio);
981 _set_gpio_irqenable(bank, gpio_idx, 1);
984 static void mpuio_ack_irq(unsigned int irq)
986 /* The ISR is reset automatically, so do nothing here. */
989 static void mpuio_mask_irq(unsigned int irq)
991 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
992 struct gpio_bank *bank = get_gpio_bank(gpio);
994 _set_gpio_irqenable(bank, gpio, 0);
997 static void mpuio_unmask_irq(unsigned int irq)
999 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1000 struct gpio_bank *bank = get_gpio_bank(gpio);
1002 _set_gpio_irqenable(bank, gpio, 1);
1005 static struct irq_chip gpio_irq_chip = {
1007 .shutdown = gpio_irq_shutdown,
1008 .ack = gpio_ack_irq,
1009 .mask = gpio_mask_irq,
1010 .unmask = gpio_unmask_irq,
1011 .set_type = gpio_irq_type,
1012 .set_wake = gpio_wake_enable,
1015 static struct irq_chip mpuio_irq_chip = {
1017 .ack = mpuio_ack_irq,
1018 .mask = mpuio_mask_irq,
1019 .unmask = mpuio_unmask_irq,
1020 .set_type = gpio_irq_type,
1023 static int initialized;
1024 static struct clk * gpio_ick;
1025 static struct clk * gpio_fck;
1027 static int __init _omap_gpio_init(void)
1030 struct gpio_bank *bank;
1034 if (cpu_is_omap15xx()) {
1035 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1036 if (IS_ERR(gpio_ick))
1037 printk("Could not get arm_gpio_ck\n");
1039 clk_enable(gpio_ick);
1041 if (cpu_is_omap24xx()) {
1042 gpio_ick = clk_get(NULL, "gpios_ick");
1043 if (IS_ERR(gpio_ick))
1044 printk("Could not get gpios_ick\n");
1046 clk_enable(gpio_ick);
1047 gpio_fck = clk_get(NULL, "gpios_fck");
1048 if (IS_ERR(gpio_fck))
1049 printk("Could not get gpios_fck\n");
1051 clk_enable(gpio_fck);
1054 #ifdef CONFIG_ARCH_OMAP15XX
1055 if (cpu_is_omap15xx()) {
1056 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1057 gpio_bank_count = 2;
1058 gpio_bank = gpio_bank_1510;
1061 #if defined(CONFIG_ARCH_OMAP16XX)
1062 if (cpu_is_omap16xx()) {
1065 gpio_bank_count = 5;
1066 gpio_bank = gpio_bank_1610;
1067 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1068 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1069 (rev >> 4) & 0x0f, rev & 0x0f);
1072 #ifdef CONFIG_ARCH_OMAP730
1073 if (cpu_is_omap730()) {
1074 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1075 gpio_bank_count = 7;
1076 gpio_bank = gpio_bank_730;
1079 #ifdef CONFIG_ARCH_OMAP24XX
1080 if (cpu_is_omap24xx()) {
1083 gpio_bank_count = 4;
1084 gpio_bank = gpio_bank_24xx;
1085 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1086 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1087 (rev >> 4) & 0x0f, rev & 0x0f);
1090 for (i = 0; i < gpio_bank_count; i++) {
1091 int j, gpio_count = 16;
1093 bank = &gpio_bank[i];
1094 bank->reserved_map = 0;
1095 bank->base = IO_ADDRESS(bank->base);
1096 spin_lock_init(&bank->lock);
1097 if (bank->method == METHOD_MPUIO) {
1098 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1100 #ifdef CONFIG_ARCH_OMAP15XX
1101 if (bank->method == METHOD_GPIO_1510) {
1102 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1103 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1106 #if defined(CONFIG_ARCH_OMAP16XX)
1107 if (bank->method == METHOD_GPIO_1610) {
1108 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1109 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1110 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1113 #ifdef CONFIG_ARCH_OMAP730
1114 if (bank->method == METHOD_GPIO_730) {
1115 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1116 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1118 gpio_count = 32; /* 730 has 32-bit GPIOs */
1121 #ifdef CONFIG_ARCH_OMAP24XX
1122 if (bank->method == METHOD_GPIO_24XX) {
1123 static const u32 non_wakeup_gpios[] = {
1124 0xe203ffc0, 0x08700040
1127 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1128 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1129 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1131 /* Initialize interface clock ungated, module enabled */
1132 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1133 if (i < ARRAY_SIZE(non_wakeup_gpios))
1134 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1138 for (j = bank->virtual_irq_start;
1139 j < bank->virtual_irq_start + gpio_count; j++) {
1140 if (bank->method == METHOD_MPUIO)
1141 set_irq_chip(j, &mpuio_irq_chip);
1143 set_irq_chip(j, &gpio_irq_chip);
1144 set_irq_handler(j, handle_simple_irq);
1145 set_irq_flags(j, IRQF_VALID);
1147 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1148 set_irq_data(bank->irq, bank);
1151 /* Enable system clock for GPIO module.
1152 * The CAM_CLK_CTRL *is* really the right place. */
1153 if (cpu_is_omap16xx())
1154 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1156 #ifdef CONFIG_ARCH_OMAP24XX
1157 /* Enable autoidle for the OCP interface */
1158 if (cpu_is_omap24xx())
1159 omap_writel(1 << 0, 0x48019010);
1165 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1166 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1170 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1173 for (i = 0; i < gpio_bank_count; i++) {
1174 struct gpio_bank *bank = &gpio_bank[i];
1175 void __iomem *wake_status;
1176 void __iomem *wake_clear;
1177 void __iomem *wake_set;
1179 switch (bank->method) {
1180 case METHOD_GPIO_1610:
1181 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1182 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1183 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1185 case METHOD_GPIO_24XX:
1186 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1187 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1188 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1194 spin_lock(&bank->lock);
1195 bank->saved_wakeup = __raw_readl(wake_status);
1196 __raw_writel(0xffffffff, wake_clear);
1197 __raw_writel(bank->suspend_wakeup, wake_set);
1198 spin_unlock(&bank->lock);
1204 static int omap_gpio_resume(struct sys_device *dev)
1208 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1211 for (i = 0; i < gpio_bank_count; i++) {
1212 struct gpio_bank *bank = &gpio_bank[i];
1213 void __iomem *wake_clear;
1214 void __iomem *wake_set;
1216 switch (bank->method) {
1217 case METHOD_GPIO_1610:
1218 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1219 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1221 case METHOD_GPIO_24XX:
1222 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1223 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1229 spin_lock(&bank->lock);
1230 __raw_writel(0xffffffff, wake_clear);
1231 __raw_writel(bank->saved_wakeup, wake_set);
1232 spin_unlock(&bank->lock);
1238 static struct sysdev_class omap_gpio_sysclass = {
1239 set_kset_name("gpio"),
1240 .suspend = omap_gpio_suspend,
1241 .resume = omap_gpio_resume,
1244 static struct sys_device omap_gpio_device = {
1246 .cls = &omap_gpio_sysclass,
1251 #ifdef CONFIG_ARCH_OMAP24XX
1253 static int workaround_enabled;
1255 void omap2_gpio_prepare_for_retention(void)
1259 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1260 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1261 for (i = 0; i < gpio_bank_count; i++) {
1262 struct gpio_bank *bank = &gpio_bank[i];
1265 if (!(bank->enabled_non_wakeup_gpios))
1267 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1268 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1269 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1270 bank->saved_fallingdetect = l1;
1271 bank->saved_risingdetect = l2;
1272 l1 &= ~bank->enabled_non_wakeup_gpios;
1273 l2 &= ~bank->enabled_non_wakeup_gpios;
1274 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1275 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1279 workaround_enabled = 0;
1282 workaround_enabled = 1;
1285 void omap2_gpio_resume_after_retention(void)
1289 if (!workaround_enabled)
1291 for (i = 0; i < gpio_bank_count; i++) {
1292 struct gpio_bank *bank = &gpio_bank[i];
1295 if (!(bank->enabled_non_wakeup_gpios))
1297 __raw_writel(bank->saved_fallingdetect,
1298 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1299 __raw_writel(bank->saved_risingdetect,
1300 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1301 /* Check if any of the non-wakeup interrupt GPIOs have changed
1302 * state. If so, generate an IRQ by software. This is
1303 * horribly racy, but it's the best we can do to work around
1304 * this silicon bug. */
1305 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1306 l ^= bank->saved_datain;
1307 l &= bank->non_wakeup_gpios;
1311 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1312 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1313 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1314 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1315 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1316 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1325 * This may get called early from board specific init
1326 * for boards that have interrupts routed via FPGA.
1328 int omap_gpio_init(void)
1331 return _omap_gpio_init();
1336 static int __init omap_gpio_sysinit(void)
1341 ret = _omap_gpio_init();
1343 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1344 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1346 ret = sysdev_class_register(&omap_gpio_sysclass);
1348 ret = sysdev_register(&omap_gpio_device);
1356 EXPORT_SYMBOL(omap_request_gpio);
1357 EXPORT_SYMBOL(omap_free_gpio);
1358 EXPORT_SYMBOL(omap_set_gpio_direction);
1359 EXPORT_SYMBOL(omap_set_gpio_dataout);
1360 EXPORT_SYMBOL(omap_get_gpio_datain);
1362 arch_initcall(omap_gpio_sysinit);