2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ptrace.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70 * OMAP730 specific GPIO registers
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
86 * omap24xx specific GPIO registers
88 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
94 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
95 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
96 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
97 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
99 #define OMAP24XX_GPIO_REVISION 0x0000
100 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
101 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
102 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
103 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
104 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
105 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
106 #define OMAP24XX_GPIO_CTRL 0x0030
107 #define OMAP24XX_GPIO_OE 0x0034
108 #define OMAP24XX_GPIO_DATAIN 0x0038
109 #define OMAP24XX_GPIO_DATAOUT 0x003c
110 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
111 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
112 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
113 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
114 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
115 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
116 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
117 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
118 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
119 #define OMAP24XX_GPIO_SETWKUENA 0x0084
120 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
121 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
126 u16 virtual_irq_start;
129 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
133 #ifdef CONFIG_ARCH_OMAP24XX
134 u32 non_wakeup_gpios;
135 u32 enabled_non_wakeup_gpios;
138 u32 saved_fallingdetect;
139 u32 saved_risingdetect;
144 #define METHOD_MPUIO 0
145 #define METHOD_GPIO_1510 1
146 #define METHOD_GPIO_1610 2
147 #define METHOD_GPIO_730 3
148 #define METHOD_GPIO_24XX 4
150 #ifdef CONFIG_ARCH_OMAP16XX
151 static struct gpio_bank gpio_bank_1610[5] = {
152 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
153 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
154 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
155 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
156 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
160 #ifdef CONFIG_ARCH_OMAP15XX
161 static struct gpio_bank gpio_bank_1510[2] = {
162 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
163 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
167 #ifdef CONFIG_ARCH_OMAP730
168 static struct gpio_bank gpio_bank_730[7] = {
169 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
170 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
171 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
172 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
173 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
174 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
175 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
179 #ifdef CONFIG_ARCH_OMAP24XX
181 static struct gpio_bank gpio_bank_242x[4] = {
182 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
183 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
184 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
185 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
188 static struct gpio_bank gpio_bank_243x[5] = {
189 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
190 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
191 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
192 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
193 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
198 static struct gpio_bank *gpio_bank;
199 static int gpio_bank_count;
201 static inline struct gpio_bank *get_gpio_bank(int gpio)
203 #ifdef CONFIG_ARCH_OMAP15XX
204 if (cpu_is_omap15xx()) {
205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1];
210 #if defined(CONFIG_ARCH_OMAP16XX)
211 if (cpu_is_omap16xx()) {
212 if (OMAP_GPIO_IS_MPUIO(gpio))
213 return &gpio_bank[0];
214 return &gpio_bank[1 + (gpio >> 4)];
217 #ifdef CONFIG_ARCH_OMAP730
218 if (cpu_is_omap730()) {
219 if (OMAP_GPIO_IS_MPUIO(gpio))
220 return &gpio_bank[0];
221 return &gpio_bank[1 + (gpio >> 5)];
224 #ifdef CONFIG_ARCH_OMAP24XX
225 if (cpu_is_omap24xx())
226 return &gpio_bank[gpio >> 5];
230 static inline int get_gpio_index(int gpio)
232 #ifdef CONFIG_ARCH_OMAP730
233 if (cpu_is_omap730())
236 #ifdef CONFIG_ARCH_OMAP24XX
237 if (cpu_is_omap24xx())
243 static inline int gpio_valid(int gpio)
247 #ifndef CONFIG_ARCH_OMAP24XX
248 if (OMAP_GPIO_IS_MPUIO(gpio)) {
249 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
254 #ifdef CONFIG_ARCH_OMAP15XX
255 if (cpu_is_omap15xx() && gpio < 16)
258 #if defined(CONFIG_ARCH_OMAP16XX)
259 if ((cpu_is_omap16xx()) && gpio < 64)
262 #ifdef CONFIG_ARCH_OMAP730
263 if (cpu_is_omap730() && gpio < 192)
266 #ifdef CONFIG_ARCH_OMAP24XX
267 if (cpu_is_omap24xx() && gpio < 128)
273 static int check_gpio(int gpio)
275 if (unlikely(gpio_valid(gpio)) < 0) {
276 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
283 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
285 void __iomem *reg = bank->base;
288 switch (bank->method) {
289 #ifdef CONFIG_ARCH_OMAP1
291 reg += OMAP_MPUIO_IO_CNTL;
294 #ifdef CONFIG_ARCH_OMAP15XX
295 case METHOD_GPIO_1510:
296 reg += OMAP1510_GPIO_DIR_CONTROL;
299 #ifdef CONFIG_ARCH_OMAP16XX
300 case METHOD_GPIO_1610:
301 reg += OMAP1610_GPIO_DIRECTION;
304 #ifdef CONFIG_ARCH_OMAP730
305 case METHOD_GPIO_730:
306 reg += OMAP730_GPIO_DIR_CONTROL;
309 #ifdef CONFIG_ARCH_OMAP24XX
310 case METHOD_GPIO_24XX:
311 reg += OMAP24XX_GPIO_OE;
318 l = __raw_readl(reg);
323 __raw_writel(l, reg);
326 void omap_set_gpio_direction(int gpio, int is_input)
328 struct gpio_bank *bank;
330 if (check_gpio(gpio) < 0)
332 bank = get_gpio_bank(gpio);
333 spin_lock(&bank->lock);
334 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
335 spin_unlock(&bank->lock);
338 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
340 void __iomem *reg = bank->base;
343 switch (bank->method) {
344 #ifdef CONFIG_ARCH_OMAP1
346 reg += OMAP_MPUIO_OUTPUT;
347 l = __raw_readl(reg);
354 #ifdef CONFIG_ARCH_OMAP15XX
355 case METHOD_GPIO_1510:
356 reg += OMAP1510_GPIO_DATA_OUTPUT;
357 l = __raw_readl(reg);
364 #ifdef CONFIG_ARCH_OMAP16XX
365 case METHOD_GPIO_1610:
367 reg += OMAP1610_GPIO_SET_DATAOUT;
369 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
373 #ifdef CONFIG_ARCH_OMAP730
374 case METHOD_GPIO_730:
375 reg += OMAP730_GPIO_DATA_OUTPUT;
376 l = __raw_readl(reg);
383 #ifdef CONFIG_ARCH_OMAP24XX
384 case METHOD_GPIO_24XX:
386 reg += OMAP24XX_GPIO_SETDATAOUT;
388 reg += OMAP24XX_GPIO_CLEARDATAOUT;
396 __raw_writel(l, reg);
399 void omap_set_gpio_dataout(int gpio, int enable)
401 struct gpio_bank *bank;
403 if (check_gpio(gpio) < 0)
405 bank = get_gpio_bank(gpio);
406 spin_lock(&bank->lock);
407 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
408 spin_unlock(&bank->lock);
411 int omap_get_gpio_datain(int gpio)
413 struct gpio_bank *bank;
416 if (check_gpio(gpio) < 0)
418 bank = get_gpio_bank(gpio);
420 switch (bank->method) {
421 #ifdef CONFIG_ARCH_OMAP1
423 reg += OMAP_MPUIO_INPUT_LATCH;
426 #ifdef CONFIG_ARCH_OMAP15XX
427 case METHOD_GPIO_1510:
428 reg += OMAP1510_GPIO_DATA_INPUT;
431 #ifdef CONFIG_ARCH_OMAP16XX
432 case METHOD_GPIO_1610:
433 reg += OMAP1610_GPIO_DATAIN;
436 #ifdef CONFIG_ARCH_OMAP730
437 case METHOD_GPIO_730:
438 reg += OMAP730_GPIO_DATA_INPUT;
441 #ifdef CONFIG_ARCH_OMAP24XX
442 case METHOD_GPIO_24XX:
443 reg += OMAP24XX_GPIO_DATAIN;
449 return (__raw_readl(reg)
450 & (1 << get_gpio_index(gpio))) != 0;
453 #define MOD_REG_BIT(reg, bit_mask, set) \
455 int l = __raw_readl(base + reg); \
456 if (set) l |= bit_mask; \
457 else l &= ~bit_mask; \
458 __raw_writel(l, base + reg); \
461 #ifdef CONFIG_ARCH_OMAP24XX
462 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
464 void __iomem *base = bank->base;
465 u32 gpio_bit = 1 << gpio;
467 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
468 trigger & __IRQT_LOWLVL);
469 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
470 trigger & __IRQT_HIGHLVL);
471 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
472 trigger & __IRQT_RISEDGE);
473 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
474 trigger & __IRQT_FALEDGE);
475 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
477 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
479 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
482 bank->enabled_non_wakeup_gpios |= gpio_bit;
484 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
486 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
487 * triggering requested. */
491 omap_set_gpio_debounce(int gpio, int enable)
493 struct gpio_bank *bank;
495 u32 val, l = 1 << get_gpio_index(gpio);
497 bank = get_gpio_bank(gpio);
500 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
501 val = __raw_readl(reg);
508 __raw_writel(val, reg);
510 EXPORT_SYMBOL(omap_set_gpio_debounce);
513 omap_set_gpio_debounce_time(int gpio, int enc_time)
515 struct gpio_bank *bank;
518 bank = get_gpio_bank(gpio);
522 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
523 __raw_writel(enc_time, reg);
525 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
528 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
530 void __iomem *reg = bank->base;
533 switch (bank->method) {
534 #ifdef CONFIG_ARCH_OMAP1
536 reg += OMAP_MPUIO_GPIO_INT_EDGE;
537 l = __raw_readl(reg);
538 if (trigger & __IRQT_RISEDGE)
540 else if (trigger & __IRQT_FALEDGE)
546 #ifdef CONFIG_ARCH_OMAP15XX
547 case METHOD_GPIO_1510:
548 reg += OMAP1510_GPIO_INT_CONTROL;
549 l = __raw_readl(reg);
550 if (trigger & __IRQT_RISEDGE)
552 else if (trigger & __IRQT_FALEDGE)
558 #ifdef CONFIG_ARCH_OMAP16XX
559 case METHOD_GPIO_1610:
561 reg += OMAP1610_GPIO_EDGE_CTRL2;
563 reg += OMAP1610_GPIO_EDGE_CTRL1;
565 l = __raw_readl(reg);
566 l &= ~(3 << (gpio << 1));
567 if (trigger & __IRQT_RISEDGE)
568 l |= 2 << (gpio << 1);
569 if (trigger & __IRQT_FALEDGE)
570 l |= 1 << (gpio << 1);
572 /* Enable wake-up during idle for dynamic tick */
573 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
575 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
578 #ifdef CONFIG_ARCH_OMAP730
579 case METHOD_GPIO_730:
580 reg += OMAP730_GPIO_INT_CONTROL;
581 l = __raw_readl(reg);
582 if (trigger & __IRQT_RISEDGE)
584 else if (trigger & __IRQT_FALEDGE)
590 #ifdef CONFIG_ARCH_OMAP24XX
591 case METHOD_GPIO_24XX:
592 set_24xx_gpio_triggering(bank, gpio, trigger);
598 __raw_writel(l, reg);
604 static int gpio_irq_type(unsigned irq, unsigned type)
606 struct gpio_bank *bank;
610 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
611 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
613 gpio = irq - IH_GPIO_BASE;
615 if (check_gpio(gpio) < 0)
618 if (type & ~IRQ_TYPE_SENSE_MASK)
621 /* OMAP1 allows only only edge triggering */
622 if (!cpu_is_omap24xx()
623 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
626 bank = get_irq_chip_data(irq);
627 spin_lock(&bank->lock);
628 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
630 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
631 irq_desc[irq].status |= type;
633 spin_unlock(&bank->lock);
637 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
639 void __iomem *reg = bank->base;
641 switch (bank->method) {
642 #ifdef CONFIG_ARCH_OMAP1
644 /* MPUIO irqstatus is reset by reading the status register,
645 * so do nothing here */
648 #ifdef CONFIG_ARCH_OMAP15XX
649 case METHOD_GPIO_1510:
650 reg += OMAP1510_GPIO_INT_STATUS;
653 #ifdef CONFIG_ARCH_OMAP16XX
654 case METHOD_GPIO_1610:
655 reg += OMAP1610_GPIO_IRQSTATUS1;
658 #ifdef CONFIG_ARCH_OMAP730
659 case METHOD_GPIO_730:
660 reg += OMAP730_GPIO_INT_STATUS;
663 #ifdef CONFIG_ARCH_OMAP24XX
664 case METHOD_GPIO_24XX:
665 reg += OMAP24XX_GPIO_IRQSTATUS1;
672 __raw_writel(gpio_mask, reg);
674 /* Workaround for clearing DSP GPIO interrupts to allow retention */
675 if (cpu_is_omap2420())
676 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
679 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
681 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
684 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
686 void __iomem *reg = bank->base;
691 switch (bank->method) {
692 #ifdef CONFIG_ARCH_OMAP1
694 reg += OMAP_MPUIO_GPIO_MASKIT;
699 #ifdef CONFIG_ARCH_OMAP15XX
700 case METHOD_GPIO_1510:
701 reg += OMAP1510_GPIO_INT_MASK;
706 #ifdef CONFIG_ARCH_OMAP16XX
707 case METHOD_GPIO_1610:
708 reg += OMAP1610_GPIO_IRQENABLE1;
712 #ifdef CONFIG_ARCH_OMAP730
713 case METHOD_GPIO_730:
714 reg += OMAP730_GPIO_INT_MASK;
719 #ifdef CONFIG_ARCH_OMAP24XX
720 case METHOD_GPIO_24XX:
721 reg += OMAP24XX_GPIO_IRQENABLE1;
730 l = __raw_readl(reg);
737 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
739 void __iomem *reg = bank->base;
742 switch (bank->method) {
743 #ifdef CONFIG_ARCH_OMAP1
745 reg += OMAP_MPUIO_GPIO_MASKIT;
746 l = __raw_readl(reg);
753 #ifdef CONFIG_ARCH_OMAP15XX
754 case METHOD_GPIO_1510:
755 reg += OMAP1510_GPIO_INT_MASK;
756 l = __raw_readl(reg);
763 #ifdef CONFIG_ARCH_OMAP16XX
764 case METHOD_GPIO_1610:
766 reg += OMAP1610_GPIO_SET_IRQENABLE1;
768 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
772 #ifdef CONFIG_ARCH_OMAP730
773 case METHOD_GPIO_730:
774 reg += OMAP730_GPIO_INT_MASK;
775 l = __raw_readl(reg);
782 #ifdef CONFIG_ARCH_OMAP24XX
783 case METHOD_GPIO_24XX:
785 reg += OMAP24XX_GPIO_SETIRQENABLE1;
787 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
795 __raw_writel(l, reg);
798 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
800 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
804 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
805 * 1510 does not seem to have a wake-up register. If JTAG is connected
806 * to the target, system will wake up always on GPIO events. While
807 * system is running all registered GPIO interrupts need to have wake-up
808 * enabled. When system is suspended, only selected GPIO interrupts need
809 * to have wake-up enabled.
811 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
813 switch (bank->method) {
814 #ifdef CONFIG_ARCH_OMAP16XX
816 case METHOD_GPIO_1610:
817 spin_lock(&bank->lock);
819 bank->suspend_wakeup |= (1 << gpio);
820 enable_irq_wake(bank->irq);
822 disable_irq_wake(bank->irq);
823 bank->suspend_wakeup &= ~(1 << gpio);
825 spin_unlock(&bank->lock);
828 #ifdef CONFIG_ARCH_OMAP24XX
829 case METHOD_GPIO_24XX:
830 if (bank->non_wakeup_gpios & (1 << gpio)) {
831 printk(KERN_ERR "Unable to modify wakeup on "
832 "non-wakeup GPIO%d\n",
833 (bank - gpio_bank) * 32 + gpio);
836 spin_lock(&bank->lock);
838 bank->suspend_wakeup |= (1 << gpio);
839 enable_irq_wake(bank->irq);
841 disable_irq_wake(bank->irq);
842 bank->suspend_wakeup &= ~(1 << gpio);
844 spin_unlock(&bank->lock);
848 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
854 static void _reset_gpio(struct gpio_bank *bank, int gpio)
856 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
857 _set_gpio_irqenable(bank, gpio, 0);
858 _clear_gpio_irqstatus(bank, gpio);
859 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
862 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
863 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
865 unsigned int gpio = irq - IH_GPIO_BASE;
866 struct gpio_bank *bank;
869 if (check_gpio(gpio) < 0)
871 bank = get_irq_chip_data(irq);
872 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
877 int omap_request_gpio(int gpio)
879 struct gpio_bank *bank;
881 if (check_gpio(gpio) < 0)
884 bank = get_gpio_bank(gpio);
885 spin_lock(&bank->lock);
886 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
887 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
889 spin_unlock(&bank->lock);
892 bank->reserved_map |= (1 << get_gpio_index(gpio));
894 /* Set trigger to none. You need to enable the desired trigger with
895 * request_irq() or set_irq_type().
897 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
899 #ifdef CONFIG_ARCH_OMAP15XX
900 if (bank->method == METHOD_GPIO_1510) {
903 /* Claim the pin for MPU */
904 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
905 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
908 spin_unlock(&bank->lock);
913 void omap_free_gpio(int gpio)
915 struct gpio_bank *bank;
917 if (check_gpio(gpio) < 0)
919 bank = get_gpio_bank(gpio);
920 spin_lock(&bank->lock);
921 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
922 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
924 spin_unlock(&bank->lock);
927 #ifdef CONFIG_ARCH_OMAP16XX
928 if (bank->method == METHOD_GPIO_1610) {
929 /* Disable wake-up during idle for dynamic tick */
930 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
931 __raw_writel(1 << get_gpio_index(gpio), reg);
934 #ifdef CONFIG_ARCH_OMAP24XX
935 if (bank->method == METHOD_GPIO_24XX) {
936 /* Disable wake-up during idle for dynamic tick */
937 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
938 __raw_writel(1 << get_gpio_index(gpio), reg);
941 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
942 _reset_gpio(bank, gpio);
943 spin_unlock(&bank->lock);
947 * We need to unmask the GPIO bank interrupt as soon as possible to
948 * avoid missing GPIO interrupts for other lines in the bank.
949 * Then we need to mask-read-clear-unmask the triggered GPIO lines
950 * in the bank to avoid missing nested interrupts for a GPIO line.
951 * If we wait to unmask individual GPIO lines in the bank after the
952 * line's interrupt handler has been run, we may miss some nested
955 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
957 void __iomem *isr_reg = NULL;
959 unsigned int gpio_irq;
960 struct gpio_bank *bank;
964 desc->chip->ack(irq);
966 bank = get_irq_data(irq);
967 #ifdef CONFIG_ARCH_OMAP1
968 if (bank->method == METHOD_MPUIO)
969 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
971 #ifdef CONFIG_ARCH_OMAP15XX
972 if (bank->method == METHOD_GPIO_1510)
973 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
975 #if defined(CONFIG_ARCH_OMAP16XX)
976 if (bank->method == METHOD_GPIO_1610)
977 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
979 #ifdef CONFIG_ARCH_OMAP730
980 if (bank->method == METHOD_GPIO_730)
981 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
983 #ifdef CONFIG_ARCH_OMAP24XX
984 if (bank->method == METHOD_GPIO_24XX)
985 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
988 u32 isr_saved, level_mask = 0;
991 enabled = _get_gpio_irqbank_mask(bank);
992 isr_saved = isr = __raw_readl(isr_reg) & enabled;
994 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
997 if (cpu_is_omap24xx()) {
999 __raw_readl(bank->base +
1000 OMAP24XX_GPIO_LEVELDETECT0) |
1001 __raw_readl(bank->base +
1002 OMAP24XX_GPIO_LEVELDETECT1);
1003 level_mask &= enabled;
1006 /* clear edge sensitive interrupts before handler(s) are
1007 called so that we don't miss any interrupt occurred while
1009 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1010 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1011 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1013 /* if there is only edge sensitive GPIO pin interrupts
1014 configured, we could unmask GPIO bank interrupt immediately */
1015 if (!level_mask && !unmasked) {
1017 desc->chip->unmask(irq);
1025 gpio_irq = bank->virtual_irq_start;
1026 for (; isr != 0; isr >>= 1, gpio_irq++) {
1031 d = irq_desc + gpio_irq;
1032 /* Don't run the handler if it's already running
1033 * or was disabled lazely.
1035 if (unlikely((d->depth ||
1036 (d->status & IRQ_INPROGRESS)))) {
1038 (gpio_irq - bank->virtual_irq_start);
1039 /* The unmasking will be done by
1040 * enable_irq in case it is disabled or
1041 * after returning from the handler if
1042 * it's already running.
1044 _enable_gpio_irqbank(bank, irq_mask, 0);
1046 /* Level triggered interrupts
1047 * won't ever be reentered
1049 BUG_ON(level_mask & irq_mask);
1050 d->status |= IRQ_PENDING;
1055 desc_handle_irq(gpio_irq, d);
1057 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1059 (gpio_irq - bank->virtual_irq_start);
1060 d->status &= ~IRQ_PENDING;
1061 _enable_gpio_irqbank(bank, irq_mask, 1);
1062 retrigger |= irq_mask;
1066 if (cpu_is_omap24xx()) {
1067 /* clear level sensitive interrupts after handler(s) */
1068 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1069 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1070 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1074 /* if bank has any level sensitive GPIO pin interrupt
1075 configured, we must unmask the bank interrupt only after
1076 handler(s) are executed in order to avoid spurious bank
1079 desc->chip->unmask(irq);
1083 static void gpio_irq_shutdown(unsigned int irq)
1085 unsigned int gpio = irq - IH_GPIO_BASE;
1086 struct gpio_bank *bank = get_irq_chip_data(irq);
1088 _reset_gpio(bank, gpio);
1091 static void gpio_ack_irq(unsigned int irq)
1093 unsigned int gpio = irq - IH_GPIO_BASE;
1094 struct gpio_bank *bank = get_irq_chip_data(irq);
1096 _clear_gpio_irqstatus(bank, gpio);
1099 static void gpio_mask_irq(unsigned int irq)
1101 unsigned int gpio = irq - IH_GPIO_BASE;
1102 struct gpio_bank *bank = get_irq_chip_data(irq);
1104 _set_gpio_irqenable(bank, gpio, 0);
1107 static void gpio_unmask_irq(unsigned int irq)
1109 unsigned int gpio = irq - IH_GPIO_BASE;
1110 unsigned int gpio_idx = get_gpio_index(gpio);
1111 struct gpio_bank *bank = get_irq_chip_data(irq);
1113 _set_gpio_irqenable(bank, gpio_idx, 1);
1116 static struct irq_chip gpio_irq_chip = {
1118 .shutdown = gpio_irq_shutdown,
1119 .ack = gpio_ack_irq,
1120 .mask = gpio_mask_irq,
1121 .unmask = gpio_unmask_irq,
1122 .set_type = gpio_irq_type,
1123 .set_wake = gpio_wake_enable,
1126 /*---------------------------------------------------------------------*/
1128 #ifdef CONFIG_ARCH_OMAP1
1130 /* MPUIO uses the always-on 32k clock */
1132 static void mpuio_ack_irq(unsigned int irq)
1134 /* The ISR is reset automatically, so do nothing here. */
1137 static void mpuio_mask_irq(unsigned int irq)
1139 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1140 struct gpio_bank *bank = get_irq_chip_data(irq);
1142 _set_gpio_irqenable(bank, gpio, 0);
1145 static void mpuio_unmask_irq(unsigned int irq)
1147 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1148 struct gpio_bank *bank = get_irq_chip_data(irq);
1150 _set_gpio_irqenable(bank, gpio, 1);
1153 static struct irq_chip mpuio_irq_chip = {
1155 .ack = mpuio_ack_irq,
1156 .mask = mpuio_mask_irq,
1157 .unmask = mpuio_unmask_irq,
1158 .set_type = gpio_irq_type,
1159 #ifdef CONFIG_ARCH_OMAP16XX
1160 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1161 .set_wake = gpio_wake_enable,
1166 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1169 #ifdef CONFIG_ARCH_OMAP16XX
1171 #include <linux/platform_device.h>
1173 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1175 struct gpio_bank *bank = platform_get_drvdata(pdev);
1176 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1178 spin_lock(&bank->lock);
1179 bank->saved_wakeup = __raw_readl(mask_reg);
1180 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1181 spin_unlock(&bank->lock);
1186 static int omap_mpuio_resume_early(struct platform_device *pdev)
1188 struct gpio_bank *bank = platform_get_drvdata(pdev);
1189 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1191 spin_lock(&bank->lock);
1192 __raw_writel(bank->saved_wakeup, mask_reg);
1193 spin_unlock(&bank->lock);
1198 /* use platform_driver for this, now that there's no longer any
1199 * point to sys_device (other than not disturbing old code).
1201 static struct platform_driver omap_mpuio_driver = {
1202 .suspend_late = omap_mpuio_suspend_late,
1203 .resume_early = omap_mpuio_resume_early,
1209 static struct platform_device omap_mpuio_device = {
1213 .driver = &omap_mpuio_driver.driver,
1215 /* could list the /proc/iomem resources */
1218 static inline void mpuio_init(void)
1220 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1222 if (platform_driver_register(&omap_mpuio_driver) == 0)
1223 (void) platform_device_register(&omap_mpuio_device);
1227 static inline void mpuio_init(void) {}
1232 extern struct irq_chip mpuio_irq_chip;
1234 #define bank_is_mpuio(bank) 0
1235 static inline void mpuio_init(void) {}
1239 /*---------------------------------------------------------------------*/
1241 static int initialized;
1242 static struct clk * gpio_ick;
1243 static struct clk * gpio_fck;
1245 #ifdef CONFIG_ARCH_OMAP2430
1246 static struct clk * gpio5_ick;
1247 static struct clk * gpio5_fck;
1250 static int __init _omap_gpio_init(void)
1253 struct gpio_bank *bank;
1257 if (cpu_is_omap15xx()) {
1258 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1259 if (IS_ERR(gpio_ick))
1260 printk("Could not get arm_gpio_ck\n");
1262 clk_enable(gpio_ick);
1264 if (cpu_is_omap24xx()) {
1265 gpio_ick = clk_get(NULL, "gpios_ick");
1266 if (IS_ERR(gpio_ick))
1267 printk("Could not get gpios_ick\n");
1269 clk_enable(gpio_ick);
1270 gpio_fck = clk_get(NULL, "gpios_fck");
1271 if (IS_ERR(gpio_fck))
1272 printk("Could not get gpios_fck\n");
1274 clk_enable(gpio_fck);
1277 * On 2430 GPIO 5 uses CORE L4 ICLK
1279 #ifdef CONFIG_ARCH_OMAP2430
1280 if (cpu_is_omap2430()) {
1281 gpio5_ick = clk_get(NULL, "gpio5_ick");
1282 if (IS_ERR(gpio5_ick))
1283 printk("Could not get gpio5_ick\n");
1285 clk_enable(gpio5_ick);
1286 gpio5_fck = clk_get(NULL, "gpio5_fck");
1287 if (IS_ERR(gpio5_fck))
1288 printk("Could not get gpio5_fck\n");
1290 clk_enable(gpio5_fck);
1295 #ifdef CONFIG_ARCH_OMAP15XX
1296 if (cpu_is_omap15xx()) {
1297 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1298 gpio_bank_count = 2;
1299 gpio_bank = gpio_bank_1510;
1302 #if defined(CONFIG_ARCH_OMAP16XX)
1303 if (cpu_is_omap16xx()) {
1306 gpio_bank_count = 5;
1307 gpio_bank = gpio_bank_1610;
1308 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1309 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1310 (rev >> 4) & 0x0f, rev & 0x0f);
1313 #ifdef CONFIG_ARCH_OMAP730
1314 if (cpu_is_omap730()) {
1315 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1316 gpio_bank_count = 7;
1317 gpio_bank = gpio_bank_730;
1321 #ifdef CONFIG_ARCH_OMAP24XX
1322 if (cpu_is_omap242x()) {
1325 gpio_bank_count = 4;
1326 gpio_bank = gpio_bank_242x;
1327 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1328 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1329 (rev >> 4) & 0x0f, rev & 0x0f);
1331 if (cpu_is_omap243x()) {
1334 gpio_bank_count = 5;
1335 gpio_bank = gpio_bank_243x;
1336 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1337 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1338 (rev >> 4) & 0x0f, rev & 0x0f);
1341 for (i = 0; i < gpio_bank_count; i++) {
1342 int j, gpio_count = 16;
1344 bank = &gpio_bank[i];
1345 bank->reserved_map = 0;
1346 bank->base = IO_ADDRESS(bank->base);
1347 spin_lock_init(&bank->lock);
1348 if (bank_is_mpuio(bank))
1349 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1350 #ifdef CONFIG_ARCH_OMAP15XX
1351 if (bank->method == METHOD_GPIO_1510) {
1352 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1353 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1356 #if defined(CONFIG_ARCH_OMAP16XX)
1357 if (bank->method == METHOD_GPIO_1610) {
1358 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1359 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1360 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1363 #ifdef CONFIG_ARCH_OMAP730
1364 if (bank->method == METHOD_GPIO_730) {
1365 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1366 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1368 gpio_count = 32; /* 730 has 32-bit GPIOs */
1371 #ifdef CONFIG_ARCH_OMAP24XX
1372 if (bank->method == METHOD_GPIO_24XX) {
1373 static const u32 non_wakeup_gpios[] = {
1374 0xe203ffc0, 0x08700040
1377 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1378 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1379 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1381 /* Initialize interface clock ungated, module enabled */
1382 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1383 if (i < ARRAY_SIZE(non_wakeup_gpios))
1384 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1388 for (j = bank->virtual_irq_start;
1389 j < bank->virtual_irq_start + gpio_count; j++) {
1390 set_irq_chip_data(j, bank);
1391 if (bank_is_mpuio(bank))
1392 set_irq_chip(j, &mpuio_irq_chip);
1394 set_irq_chip(j, &gpio_irq_chip);
1395 set_irq_handler(j, handle_simple_irq);
1396 set_irq_flags(j, IRQF_VALID);
1398 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1399 set_irq_data(bank->irq, bank);
1402 /* Enable system clock for GPIO module.
1403 * The CAM_CLK_CTRL *is* really the right place. */
1404 if (cpu_is_omap16xx())
1405 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1407 #ifdef CONFIG_ARCH_OMAP24XX
1408 /* Enable autoidle for the OCP interface */
1409 if (cpu_is_omap24xx())
1410 omap_writel(1 << 0, 0x48019010);
1416 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1417 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1421 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1424 for (i = 0; i < gpio_bank_count; i++) {
1425 struct gpio_bank *bank = &gpio_bank[i];
1426 void __iomem *wake_status;
1427 void __iomem *wake_clear;
1428 void __iomem *wake_set;
1430 switch (bank->method) {
1431 #ifdef CONFIG_ARCH_OMAP16XX
1432 case METHOD_GPIO_1610:
1433 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1434 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1435 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1438 #ifdef CONFIG_ARCH_OMAP24XX
1439 case METHOD_GPIO_24XX:
1440 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1441 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1442 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1449 spin_lock(&bank->lock);
1450 bank->saved_wakeup = __raw_readl(wake_status);
1451 __raw_writel(0xffffffff, wake_clear);
1452 __raw_writel(bank->suspend_wakeup, wake_set);
1453 spin_unlock(&bank->lock);
1459 static int omap_gpio_resume(struct sys_device *dev)
1463 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1466 for (i = 0; i < gpio_bank_count; i++) {
1467 struct gpio_bank *bank = &gpio_bank[i];
1468 void __iomem *wake_clear;
1469 void __iomem *wake_set;
1471 switch (bank->method) {
1472 #ifdef CONFIG_ARCH_OMAP16XX
1473 case METHOD_GPIO_1610:
1474 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1475 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1478 #ifdef CONFIG_ARCH_OMAP24XX
1479 case METHOD_GPIO_24XX:
1480 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1481 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1488 spin_lock(&bank->lock);
1489 __raw_writel(0xffffffff, wake_clear);
1490 __raw_writel(bank->saved_wakeup, wake_set);
1491 spin_unlock(&bank->lock);
1497 static struct sysdev_class omap_gpio_sysclass = {
1498 set_kset_name("gpio"),
1499 .suspend = omap_gpio_suspend,
1500 .resume = omap_gpio_resume,
1503 static struct sys_device omap_gpio_device = {
1505 .cls = &omap_gpio_sysclass,
1510 #ifdef CONFIG_ARCH_OMAP24XX
1512 static int workaround_enabled;
1514 void omap2_gpio_prepare_for_retention(void)
1518 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1519 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1520 for (i = 0; i < gpio_bank_count; i++) {
1521 struct gpio_bank *bank = &gpio_bank[i];
1524 if (!(bank->enabled_non_wakeup_gpios))
1526 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1527 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1528 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1529 bank->saved_fallingdetect = l1;
1530 bank->saved_risingdetect = l2;
1531 l1 &= ~bank->enabled_non_wakeup_gpios;
1532 l2 &= ~bank->enabled_non_wakeup_gpios;
1533 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1534 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1538 workaround_enabled = 0;
1541 workaround_enabled = 1;
1544 void omap2_gpio_resume_after_retention(void)
1548 if (!workaround_enabled)
1550 for (i = 0; i < gpio_bank_count; i++) {
1551 struct gpio_bank *bank = &gpio_bank[i];
1554 if (!(bank->enabled_non_wakeup_gpios))
1556 __raw_writel(bank->saved_fallingdetect,
1557 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1558 __raw_writel(bank->saved_risingdetect,
1559 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1560 /* Check if any of the non-wakeup interrupt GPIOs have changed
1561 * state. If so, generate an IRQ by software. This is
1562 * horribly racy, but it's the best we can do to work around
1563 * this silicon bug. */
1564 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1565 l ^= bank->saved_datain;
1566 l &= bank->non_wakeup_gpios;
1570 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1571 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1572 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1573 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1574 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1575 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1584 * This may get called early from board specific init
1585 * for boards that have interrupts routed via FPGA.
1587 int __init omap_gpio_init(void)
1590 return _omap_gpio_init();
1595 static int __init omap_gpio_sysinit(void)
1600 ret = _omap_gpio_init();
1604 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1605 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1607 ret = sysdev_class_register(&omap_gpio_sysclass);
1609 ret = sysdev_register(&omap_gpio_device);
1617 EXPORT_SYMBOL(omap_request_gpio);
1618 EXPORT_SYMBOL(omap_free_gpio);
1619 EXPORT_SYMBOL(omap_set_gpio_direction);
1620 EXPORT_SYMBOL(omap_set_gpio_dataout);
1621 EXPORT_SYMBOL(omap_get_gpio_datain);
1623 arch_initcall(omap_gpio_sysinit);
1626 #ifdef CONFIG_DEBUG_FS
1628 #include <linux/debugfs.h>
1629 #include <linux/seq_file.h>
1631 static int gpio_is_input(struct gpio_bank *bank, int mask)
1633 void __iomem *reg = bank->base;
1635 switch (bank->method) {
1637 reg += OMAP_MPUIO_IO_CNTL;
1639 case METHOD_GPIO_1510:
1640 reg += OMAP1510_GPIO_DIR_CONTROL;
1642 case METHOD_GPIO_1610:
1643 reg += OMAP1610_GPIO_DIRECTION;
1645 case METHOD_GPIO_730:
1646 reg += OMAP730_GPIO_DIR_CONTROL;
1648 case METHOD_GPIO_24XX:
1649 reg += OMAP24XX_GPIO_OE;
1652 return __raw_readl(reg) & mask;
1656 static int dbg_gpio_show(struct seq_file *s, void *unused)
1658 unsigned i, j, gpio;
1660 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1661 struct gpio_bank *bank = gpio_bank + i;
1662 unsigned bankwidth = 16;
1665 if (bank_is_mpuio(bank))
1666 gpio = OMAP_MPUIO(0);
1667 else if (cpu_is_omap24xx() || cpu_is_omap730())
1670 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1671 unsigned irq, value, is_in, irqstat;
1673 if (!(bank->reserved_map & mask))
1676 irq = bank->virtual_irq_start + j;
1677 value = omap_get_gpio_datain(gpio);
1678 is_in = gpio_is_input(bank, mask);
1680 if (bank_is_mpuio(bank))
1681 seq_printf(s, "MPUIO %2d: ", j);
1683 seq_printf(s, "GPIO %3d: ", gpio);
1684 seq_printf(s, "%s %s",
1685 is_in ? "in " : "out",
1686 value ? "hi" : "lo");
1688 irqstat = irq_desc[irq].status;
1689 if (is_in && ((bank->suspend_wakeup & mask)
1690 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1691 char *trigger = NULL;
1693 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1694 case IRQ_TYPE_EDGE_FALLING:
1695 trigger = "falling";
1697 case IRQ_TYPE_EDGE_RISING:
1700 case IRQ_TYPE_EDGE_BOTH:
1701 trigger = "bothedge";
1703 case IRQ_TYPE_LEVEL_LOW:
1706 case IRQ_TYPE_LEVEL_HIGH:
1710 trigger = "(unspecified)";
1713 seq_printf(s, ", irq-%d %s%s",
1715 (bank->suspend_wakeup & mask)
1718 seq_printf(s, "\n");
1721 if (bank_is_mpuio(bank)) {
1722 seq_printf(s, "\n");
1729 static int dbg_gpio_open(struct inode *inode, struct file *file)
1731 return single_open(file, dbg_gpio_show, &inode->i_private);
1734 static const struct file_operations debug_fops = {
1735 .open = dbg_gpio_open,
1737 .llseek = seq_lseek,
1738 .release = single_release,
1741 static int __init omap_gpio_debuginit(void)
1743 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1744 NULL, NULL, &debug_fops);
1747 late_initcall(omap_gpio_debuginit);