2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70 * OMAP730 specific GPIO registers
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
86 * omap24xx specific GPIO registers
88 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP24XX_GPIO_REVISION 0x0000
93 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
94 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
95 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
96 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
97 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
117 u16 virtual_irq_start;
120 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
124 #ifdef CONFIG_ARCH_OMAP24XX
125 u32 non_wakeup_gpios;
126 u32 enabled_non_wakeup_gpios;
129 u32 saved_fallingdetect;
130 u32 saved_risingdetect;
135 #define METHOD_MPUIO 0
136 #define METHOD_GPIO_1510 1
137 #define METHOD_GPIO_1610 2
138 #define METHOD_GPIO_730 3
139 #define METHOD_GPIO_24XX 4
141 #ifdef CONFIG_ARCH_OMAP16XX
142 static struct gpio_bank gpio_bank_1610[5] = {
143 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
144 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
145 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
146 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
147 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
151 #ifdef CONFIG_ARCH_OMAP15XX
152 static struct gpio_bank gpio_bank_1510[2] = {
153 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
154 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
158 #ifdef CONFIG_ARCH_OMAP730
159 static struct gpio_bank gpio_bank_730[7] = {
160 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
161 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
162 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
163 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
164 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
165 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
166 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
170 #ifdef CONFIG_ARCH_OMAP24XX
171 static struct gpio_bank gpio_bank_24xx[4] = {
172 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
173 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
174 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
175 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
179 static struct gpio_bank *gpio_bank;
180 static int gpio_bank_count;
182 static inline struct gpio_bank *get_gpio_bank(int gpio)
184 #ifdef CONFIG_ARCH_OMAP15XX
185 if (cpu_is_omap15xx()) {
186 if (OMAP_GPIO_IS_MPUIO(gpio))
187 return &gpio_bank[0];
188 return &gpio_bank[1];
191 #if defined(CONFIG_ARCH_OMAP16XX)
192 if (cpu_is_omap16xx()) {
193 if (OMAP_GPIO_IS_MPUIO(gpio))
194 return &gpio_bank[0];
195 return &gpio_bank[1 + (gpio >> 4)];
198 #ifdef CONFIG_ARCH_OMAP730
199 if (cpu_is_omap730()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 5)];
205 #ifdef CONFIG_ARCH_OMAP24XX
206 if (cpu_is_omap24xx())
207 return &gpio_bank[gpio >> 5];
211 static inline int get_gpio_index(int gpio)
213 #ifdef CONFIG_ARCH_OMAP730
214 if (cpu_is_omap730())
217 #ifdef CONFIG_ARCH_OMAP24XX
218 if (cpu_is_omap24xx())
224 static inline int gpio_valid(int gpio)
228 #ifndef CONFIG_ARCH_OMAP24XX
229 if (OMAP_GPIO_IS_MPUIO(gpio)) {
230 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
235 #ifdef CONFIG_ARCH_OMAP15XX
236 if (cpu_is_omap15xx() && gpio < 16)
239 #if defined(CONFIG_ARCH_OMAP16XX)
240 if ((cpu_is_omap16xx()) && gpio < 64)
243 #ifdef CONFIG_ARCH_OMAP730
244 if (cpu_is_omap730() && gpio < 192)
247 #ifdef CONFIG_ARCH_OMAP24XX
248 if (cpu_is_omap24xx() && gpio < 128)
254 static int check_gpio(int gpio)
256 if (unlikely(gpio_valid(gpio)) < 0) {
257 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
264 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
266 void __iomem *reg = bank->base;
269 switch (bank->method) {
270 #ifdef CONFIG_ARCH_OMAP1
272 reg += OMAP_MPUIO_IO_CNTL;
275 #ifdef CONFIG_ARCH_OMAP15XX
276 case METHOD_GPIO_1510:
277 reg += OMAP1510_GPIO_DIR_CONTROL;
280 #ifdef CONFIG_ARCH_OMAP16XX
281 case METHOD_GPIO_1610:
282 reg += OMAP1610_GPIO_DIRECTION;
285 #ifdef CONFIG_ARCH_OMAP730
286 case METHOD_GPIO_730:
287 reg += OMAP730_GPIO_DIR_CONTROL;
290 #ifdef CONFIG_ARCH_OMAP24XX
291 case METHOD_GPIO_24XX:
292 reg += OMAP24XX_GPIO_OE;
299 l = __raw_readl(reg);
304 __raw_writel(l, reg);
307 void omap_set_gpio_direction(int gpio, int is_input)
309 struct gpio_bank *bank;
311 if (check_gpio(gpio) < 0)
313 bank = get_gpio_bank(gpio);
314 spin_lock(&bank->lock);
315 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
316 spin_unlock(&bank->lock);
319 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
321 void __iomem *reg = bank->base;
324 switch (bank->method) {
325 #ifdef CONFIG_ARCH_OMAP1
327 reg += OMAP_MPUIO_OUTPUT;
328 l = __raw_readl(reg);
335 #ifdef CONFIG_ARCH_OMAP15XX
336 case METHOD_GPIO_1510:
337 reg += OMAP1510_GPIO_DATA_OUTPUT;
338 l = __raw_readl(reg);
345 #ifdef CONFIG_ARCH_OMAP16XX
346 case METHOD_GPIO_1610:
348 reg += OMAP1610_GPIO_SET_DATAOUT;
350 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
354 #ifdef CONFIG_ARCH_OMAP730
355 case METHOD_GPIO_730:
356 reg += OMAP730_GPIO_DATA_OUTPUT;
357 l = __raw_readl(reg);
364 #ifdef CONFIG_ARCH_OMAP24XX
365 case METHOD_GPIO_24XX:
367 reg += OMAP24XX_GPIO_SETDATAOUT;
369 reg += OMAP24XX_GPIO_CLEARDATAOUT;
377 __raw_writel(l, reg);
380 void omap_set_gpio_dataout(int gpio, int enable)
382 struct gpio_bank *bank;
384 if (check_gpio(gpio) < 0)
386 bank = get_gpio_bank(gpio);
387 spin_lock(&bank->lock);
388 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
389 spin_unlock(&bank->lock);
392 int omap_get_gpio_datain(int gpio)
394 struct gpio_bank *bank;
397 if (check_gpio(gpio) < 0)
399 bank = get_gpio_bank(gpio);
401 switch (bank->method) {
402 #ifdef CONFIG_ARCH_OMAP1
404 reg += OMAP_MPUIO_INPUT_LATCH;
407 #ifdef CONFIG_ARCH_OMAP15XX
408 case METHOD_GPIO_1510:
409 reg += OMAP1510_GPIO_DATA_INPUT;
412 #ifdef CONFIG_ARCH_OMAP16XX
413 case METHOD_GPIO_1610:
414 reg += OMAP1610_GPIO_DATAIN;
417 #ifdef CONFIG_ARCH_OMAP730
418 case METHOD_GPIO_730:
419 reg += OMAP730_GPIO_DATA_INPUT;
422 #ifdef CONFIG_ARCH_OMAP24XX
423 case METHOD_GPIO_24XX:
424 reg += OMAP24XX_GPIO_DATAIN;
430 return (__raw_readl(reg)
431 & (1 << get_gpio_index(gpio))) != 0;
434 #define MOD_REG_BIT(reg, bit_mask, set) \
436 int l = __raw_readl(base + reg); \
437 if (set) l |= bit_mask; \
438 else l &= ~bit_mask; \
439 __raw_writel(l, base + reg); \
442 #ifdef CONFIG_ARCH_OMAP24XX
443 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
445 void __iomem *base = bank->base;
446 u32 gpio_bit = 1 << gpio;
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
449 trigger & __IRQT_LOWLVL);
450 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
451 trigger & __IRQT_HIGHLVL);
452 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
453 trigger & __IRQT_RISEDGE);
454 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
455 trigger & __IRQT_FALEDGE);
456 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
458 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
460 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
463 bank->enabled_non_wakeup_gpios |= gpio_bit;
465 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
467 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
468 * triggering requested. */
472 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
474 void __iomem *reg = bank->base;
477 switch (bank->method) {
478 #ifdef CONFIG_ARCH_OMAP1
480 reg += OMAP_MPUIO_GPIO_INT_EDGE;
481 l = __raw_readl(reg);
482 if (trigger & __IRQT_RISEDGE)
484 else if (trigger & __IRQT_FALEDGE)
490 #ifdef CONFIG_ARCH_OMAP15XX
491 case METHOD_GPIO_1510:
492 reg += OMAP1510_GPIO_INT_CONTROL;
493 l = __raw_readl(reg);
494 if (trigger & __IRQT_RISEDGE)
496 else if (trigger & __IRQT_FALEDGE)
502 #ifdef CONFIG_ARCH_OMAP16XX
503 case METHOD_GPIO_1610:
505 reg += OMAP1610_GPIO_EDGE_CTRL2;
507 reg += OMAP1610_GPIO_EDGE_CTRL1;
509 l = __raw_readl(reg);
510 l &= ~(3 << (gpio << 1));
511 if (trigger & __IRQT_RISEDGE)
512 l |= 2 << (gpio << 1);
513 if (trigger & __IRQT_FALEDGE)
514 l |= 1 << (gpio << 1);
516 /* Enable wake-up during idle for dynamic tick */
517 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
519 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
522 #ifdef CONFIG_ARCH_OMAP730
523 case METHOD_GPIO_730:
524 reg += OMAP730_GPIO_INT_CONTROL;
525 l = __raw_readl(reg);
526 if (trigger & __IRQT_RISEDGE)
528 else if (trigger & __IRQT_FALEDGE)
534 #ifdef CONFIG_ARCH_OMAP24XX
535 case METHOD_GPIO_24XX:
536 set_24xx_gpio_triggering(bank, gpio, trigger);
542 __raw_writel(l, reg);
548 static int gpio_irq_type(unsigned irq, unsigned type)
550 struct gpio_bank *bank;
554 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
555 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
557 gpio = irq - IH_GPIO_BASE;
559 if (check_gpio(gpio) < 0)
562 if (type & ~IRQ_TYPE_SENSE_MASK)
565 /* OMAP1 allows only only edge triggering */
566 if (!cpu_is_omap24xx()
567 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
570 bank = get_gpio_bank(gpio);
571 spin_lock(&bank->lock);
572 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
574 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
575 irq_desc[irq].status |= type;
577 spin_unlock(&bank->lock);
581 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
583 void __iomem *reg = bank->base;
585 switch (bank->method) {
586 #ifdef CONFIG_ARCH_OMAP1
588 /* MPUIO irqstatus is reset by reading the status register,
589 * so do nothing here */
592 #ifdef CONFIG_ARCH_OMAP15XX
593 case METHOD_GPIO_1510:
594 reg += OMAP1510_GPIO_INT_STATUS;
597 #ifdef CONFIG_ARCH_OMAP16XX
598 case METHOD_GPIO_1610:
599 reg += OMAP1610_GPIO_IRQSTATUS1;
602 #ifdef CONFIG_ARCH_OMAP730
603 case METHOD_GPIO_730:
604 reg += OMAP730_GPIO_INT_STATUS;
607 #ifdef CONFIG_ARCH_OMAP24XX
608 case METHOD_GPIO_24XX:
609 reg += OMAP24XX_GPIO_IRQSTATUS1;
616 __raw_writel(gpio_mask, reg);
618 /* Workaround for clearing DSP GPIO interrupts to allow retention */
619 if (cpu_is_omap2420())
620 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
623 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
625 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
628 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
630 void __iomem *reg = bank->base;
635 switch (bank->method) {
636 #ifdef CONFIG_ARCH_OMAP1
638 reg += OMAP_MPUIO_GPIO_MASKIT;
643 #ifdef CONFIG_ARCH_OMAP15XX
644 case METHOD_GPIO_1510:
645 reg += OMAP1510_GPIO_INT_MASK;
650 #ifdef CONFIG_ARCH_OMAP16XX
651 case METHOD_GPIO_1610:
652 reg += OMAP1610_GPIO_IRQENABLE1;
656 #ifdef CONFIG_ARCH_OMAP730
657 case METHOD_GPIO_730:
658 reg += OMAP730_GPIO_INT_MASK;
663 #ifdef CONFIG_ARCH_OMAP24XX
664 case METHOD_GPIO_24XX:
665 reg += OMAP24XX_GPIO_IRQENABLE1;
674 l = __raw_readl(reg);
681 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
683 void __iomem *reg = bank->base;
686 switch (bank->method) {
687 #ifdef CONFIG_ARCH_OMAP1
689 reg += OMAP_MPUIO_GPIO_MASKIT;
690 l = __raw_readl(reg);
697 #ifdef CONFIG_ARCH_OMAP15XX
698 case METHOD_GPIO_1510:
699 reg += OMAP1510_GPIO_INT_MASK;
700 l = __raw_readl(reg);
707 #ifdef CONFIG_ARCH_OMAP16XX
708 case METHOD_GPIO_1610:
710 reg += OMAP1610_GPIO_SET_IRQENABLE1;
712 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
716 #ifdef CONFIG_ARCH_OMAP730
717 case METHOD_GPIO_730:
718 reg += OMAP730_GPIO_INT_MASK;
719 l = __raw_readl(reg);
726 #ifdef CONFIG_ARCH_OMAP24XX
727 case METHOD_GPIO_24XX:
729 reg += OMAP24XX_GPIO_SETIRQENABLE1;
731 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
739 __raw_writel(l, reg);
742 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
744 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
748 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
749 * 1510 does not seem to have a wake-up register. If JTAG is connected
750 * to the target, system will wake up always on GPIO events. While
751 * system is running all registered GPIO interrupts need to have wake-up
752 * enabled. When system is suspended, only selected GPIO interrupts need
753 * to have wake-up enabled.
755 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
757 switch (bank->method) {
758 #ifdef CONFIG_ARCH_OMAP16XX
759 case METHOD_GPIO_1610:
760 spin_lock(&bank->lock);
762 bank->suspend_wakeup |= (1 << gpio);
764 bank->suspend_wakeup &= ~(1 << gpio);
765 spin_unlock(&bank->lock);
768 #ifdef CONFIG_ARCH_OMAP24XX
769 case METHOD_GPIO_24XX:
770 spin_lock(&bank->lock);
772 if (bank->non_wakeup_gpios & (1 << gpio)) {
773 printk(KERN_ERR "Unable to enable wakeup on "
774 "non-wakeup GPIO%d\n",
775 (bank - gpio_bank) * 32 + gpio);
776 spin_unlock(&bank->lock);
779 bank->suspend_wakeup |= (1 << gpio);
781 bank->suspend_wakeup &= ~(1 << gpio);
782 spin_unlock(&bank->lock);
786 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
792 static void _reset_gpio(struct gpio_bank *bank, int gpio)
794 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
795 _set_gpio_irqenable(bank, gpio, 0);
796 _clear_gpio_irqstatus(bank, gpio);
797 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
800 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
801 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
803 unsigned int gpio = irq - IH_GPIO_BASE;
804 struct gpio_bank *bank;
807 if (check_gpio(gpio) < 0)
809 bank = get_gpio_bank(gpio);
810 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
815 int omap_request_gpio(int gpio)
817 struct gpio_bank *bank;
819 if (check_gpio(gpio) < 0)
822 bank = get_gpio_bank(gpio);
823 spin_lock(&bank->lock);
824 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
825 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
827 spin_unlock(&bank->lock);
830 bank->reserved_map |= (1 << get_gpio_index(gpio));
832 /* Set trigger to none. You need to enable the desired trigger with
833 * request_irq() or set_irq_type().
835 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
837 #ifdef CONFIG_ARCH_OMAP15XX
838 if (bank->method == METHOD_GPIO_1510) {
841 /* Claim the pin for MPU */
842 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
843 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
846 spin_unlock(&bank->lock);
851 void omap_free_gpio(int gpio)
853 struct gpio_bank *bank;
855 if (check_gpio(gpio) < 0)
857 bank = get_gpio_bank(gpio);
858 spin_lock(&bank->lock);
859 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
860 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
862 spin_unlock(&bank->lock);
865 #ifdef CONFIG_ARCH_OMAP16XX
866 if (bank->method == METHOD_GPIO_1610) {
867 /* Disable wake-up during idle for dynamic tick */
868 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
869 __raw_writel(1 << get_gpio_index(gpio), reg);
872 #ifdef CONFIG_ARCH_OMAP24XX
873 if (bank->method == METHOD_GPIO_24XX) {
874 /* Disable wake-up during idle for dynamic tick */
875 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
876 __raw_writel(1 << get_gpio_index(gpio), reg);
879 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
880 _reset_gpio(bank, gpio);
881 spin_unlock(&bank->lock);
885 * We need to unmask the GPIO bank interrupt as soon as possible to
886 * avoid missing GPIO interrupts for other lines in the bank.
887 * Then we need to mask-read-clear-unmask the triggered GPIO lines
888 * in the bank to avoid missing nested interrupts for a GPIO line.
889 * If we wait to unmask individual GPIO lines in the bank after the
890 * line's interrupt handler has been run, we may miss some nested
893 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
895 void __iomem *isr_reg = NULL;
897 unsigned int gpio_irq;
898 struct gpio_bank *bank;
902 desc->chip->ack(irq);
904 bank = get_irq_data(irq);
905 #ifdef CONFIG_ARCH_OMAP1
906 if (bank->method == METHOD_MPUIO)
907 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
909 #ifdef CONFIG_ARCH_OMAP15XX
910 if (bank->method == METHOD_GPIO_1510)
911 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
913 #if defined(CONFIG_ARCH_OMAP16XX)
914 if (bank->method == METHOD_GPIO_1610)
915 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
917 #ifdef CONFIG_ARCH_OMAP730
918 if (bank->method == METHOD_GPIO_730)
919 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
921 #ifdef CONFIG_ARCH_OMAP24XX
922 if (bank->method == METHOD_GPIO_24XX)
923 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
926 u32 isr_saved, level_mask = 0;
929 enabled = _get_gpio_irqbank_mask(bank);
930 isr_saved = isr = __raw_readl(isr_reg) & enabled;
932 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
935 if (cpu_is_omap24xx()) {
937 __raw_readl(bank->base +
938 OMAP24XX_GPIO_LEVELDETECT0) |
939 __raw_readl(bank->base +
940 OMAP24XX_GPIO_LEVELDETECT1);
941 level_mask &= enabled;
944 /* clear edge sensitive interrupts before handler(s) are
945 called so that we don't miss any interrupt occurred while
947 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
948 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
949 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
951 /* if there is only edge sensitive GPIO pin interrupts
952 configured, we could unmask GPIO bank interrupt immediately */
953 if (!level_mask && !unmasked) {
955 desc->chip->unmask(irq);
963 gpio_irq = bank->virtual_irq_start;
964 for (; isr != 0; isr >>= 1, gpio_irq++) {
969 d = irq_desc + gpio_irq;
970 /* Don't run the handler if it's already running
971 * or was disabled lazely.
973 if (unlikely((d->depth ||
974 (d->status & IRQ_INPROGRESS)))) {
976 (gpio_irq - bank->virtual_irq_start);
977 /* The unmasking will be done by
978 * enable_irq in case it is disabled or
979 * after returning from the handler if
980 * it's already running.
982 _enable_gpio_irqbank(bank, irq_mask, 0);
984 /* Level triggered interrupts
985 * won't ever be reentered
987 BUG_ON(level_mask & irq_mask);
988 d->status |= IRQ_PENDING;
993 desc_handle_irq(gpio_irq, d);
995 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
997 (gpio_irq - bank->virtual_irq_start);
998 d->status &= ~IRQ_PENDING;
999 _enable_gpio_irqbank(bank, irq_mask, 1);
1000 retrigger |= irq_mask;
1004 if (cpu_is_omap24xx()) {
1005 /* clear level sensitive interrupts after handler(s) */
1006 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1007 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1008 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1012 /* if bank has any level sensitive GPIO pin interrupt
1013 configured, we must unmask the bank interrupt only after
1014 handler(s) are executed in order to avoid spurious bank
1017 desc->chip->unmask(irq);
1021 static void gpio_irq_shutdown(unsigned int irq)
1023 unsigned int gpio = irq - IH_GPIO_BASE;
1024 struct gpio_bank *bank = get_gpio_bank(gpio);
1026 _reset_gpio(bank, gpio);
1029 static void gpio_ack_irq(unsigned int irq)
1031 unsigned int gpio = irq - IH_GPIO_BASE;
1032 struct gpio_bank *bank = get_gpio_bank(gpio);
1034 _clear_gpio_irqstatus(bank, gpio);
1037 static void gpio_mask_irq(unsigned int irq)
1039 unsigned int gpio = irq - IH_GPIO_BASE;
1040 struct gpio_bank *bank = get_gpio_bank(gpio);
1042 _set_gpio_irqenable(bank, gpio, 0);
1045 static void gpio_unmask_irq(unsigned int irq)
1047 unsigned int gpio = irq - IH_GPIO_BASE;
1048 unsigned int gpio_idx = get_gpio_index(gpio);
1049 struct gpio_bank *bank = get_gpio_bank(gpio);
1051 _set_gpio_irqenable(bank, gpio_idx, 1);
1054 static struct irq_chip gpio_irq_chip = {
1056 .shutdown = gpio_irq_shutdown,
1057 .ack = gpio_ack_irq,
1058 .mask = gpio_mask_irq,
1059 .unmask = gpio_unmask_irq,
1060 .set_type = gpio_irq_type,
1061 .set_wake = gpio_wake_enable,
1064 /*---------------------------------------------------------------------*/
1066 #ifdef CONFIG_ARCH_OMAP1
1068 /* MPUIO uses the always-on 32k clock */
1070 static void mpuio_ack_irq(unsigned int irq)
1072 /* The ISR is reset automatically, so do nothing here. */
1075 static void mpuio_mask_irq(unsigned int irq)
1077 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1078 struct gpio_bank *bank = get_gpio_bank(gpio);
1080 _set_gpio_irqenable(bank, gpio, 0);
1083 static void mpuio_unmask_irq(unsigned int irq)
1085 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1086 struct gpio_bank *bank = get_gpio_bank(gpio);
1088 _set_gpio_irqenable(bank, gpio, 1);
1091 static struct irq_chip mpuio_irq_chip = {
1093 .ack = mpuio_ack_irq,
1094 .mask = mpuio_mask_irq,
1095 .unmask = mpuio_unmask_irq,
1096 .set_type = gpio_irq_type,
1100 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1104 extern struct irq_chip mpuio_irq_chip;
1106 #define bank_is_mpuio(bank) 0
1110 /*---------------------------------------------------------------------*/
1112 static int initialized;
1113 static struct clk * gpio_ick;
1114 static struct clk * gpio_fck;
1116 static int __init _omap_gpio_init(void)
1119 struct gpio_bank *bank;
1123 if (cpu_is_omap15xx()) {
1124 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1125 if (IS_ERR(gpio_ick))
1126 printk("Could not get arm_gpio_ck\n");
1128 clk_enable(gpio_ick);
1130 if (cpu_is_omap24xx()) {
1131 gpio_ick = clk_get(NULL, "gpios_ick");
1132 if (IS_ERR(gpio_ick))
1133 printk("Could not get gpios_ick\n");
1135 clk_enable(gpio_ick);
1136 gpio_fck = clk_get(NULL, "gpios_fck");
1137 if (IS_ERR(gpio_fck))
1138 printk("Could not get gpios_fck\n");
1140 clk_enable(gpio_fck);
1143 #ifdef CONFIG_ARCH_OMAP15XX
1144 if (cpu_is_omap15xx()) {
1145 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1146 gpio_bank_count = 2;
1147 gpio_bank = gpio_bank_1510;
1150 #if defined(CONFIG_ARCH_OMAP16XX)
1151 if (cpu_is_omap16xx()) {
1154 gpio_bank_count = 5;
1155 gpio_bank = gpio_bank_1610;
1156 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1157 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1158 (rev >> 4) & 0x0f, rev & 0x0f);
1161 #ifdef CONFIG_ARCH_OMAP730
1162 if (cpu_is_omap730()) {
1163 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1164 gpio_bank_count = 7;
1165 gpio_bank = gpio_bank_730;
1168 #ifdef CONFIG_ARCH_OMAP24XX
1169 if (cpu_is_omap24xx()) {
1172 gpio_bank_count = 4;
1173 gpio_bank = gpio_bank_24xx;
1174 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1175 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1176 (rev >> 4) & 0x0f, rev & 0x0f);
1179 for (i = 0; i < gpio_bank_count; i++) {
1180 int j, gpio_count = 16;
1182 bank = &gpio_bank[i];
1183 bank->reserved_map = 0;
1184 bank->base = IO_ADDRESS(bank->base);
1185 spin_lock_init(&bank->lock);
1186 if (bank_is_mpuio(bank))
1187 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1188 #ifdef CONFIG_ARCH_OMAP15XX
1189 if (bank->method == METHOD_GPIO_1510) {
1190 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1191 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1194 #if defined(CONFIG_ARCH_OMAP16XX)
1195 if (bank->method == METHOD_GPIO_1610) {
1196 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1197 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1198 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1201 #ifdef CONFIG_ARCH_OMAP730
1202 if (bank->method == METHOD_GPIO_730) {
1203 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1204 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1206 gpio_count = 32; /* 730 has 32-bit GPIOs */
1209 #ifdef CONFIG_ARCH_OMAP24XX
1210 if (bank->method == METHOD_GPIO_24XX) {
1211 static const u32 non_wakeup_gpios[] = {
1212 0xe203ffc0, 0x08700040
1215 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1216 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1217 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1219 /* Initialize interface clock ungated, module enabled */
1220 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1221 if (i < ARRAY_SIZE(non_wakeup_gpios))
1222 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1226 for (j = bank->virtual_irq_start;
1227 j < bank->virtual_irq_start + gpio_count; j++) {
1228 if (bank_is_mpuio(bank))
1229 set_irq_chip(j, &mpuio_irq_chip);
1231 set_irq_chip(j, &gpio_irq_chip);
1232 set_irq_handler(j, handle_simple_irq);
1233 set_irq_flags(j, IRQF_VALID);
1235 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1236 set_irq_data(bank->irq, bank);
1239 /* Enable system clock for GPIO module.
1240 * The CAM_CLK_CTRL *is* really the right place. */
1241 if (cpu_is_omap16xx())
1242 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1244 #ifdef CONFIG_ARCH_OMAP24XX
1245 /* Enable autoidle for the OCP interface */
1246 if (cpu_is_omap24xx())
1247 omap_writel(1 << 0, 0x48019010);
1253 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1254 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1258 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1261 for (i = 0; i < gpio_bank_count; i++) {
1262 struct gpio_bank *bank = &gpio_bank[i];
1263 void __iomem *wake_status;
1264 void __iomem *wake_clear;
1265 void __iomem *wake_set;
1267 switch (bank->method) {
1268 #ifdef CONFIG_ARCH_OMAP16XX
1269 case METHOD_GPIO_1610:
1270 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1271 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1272 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1275 #ifdef CONFIG_ARCH_OMAP24XX
1276 case METHOD_GPIO_24XX:
1277 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1278 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1279 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1286 spin_lock(&bank->lock);
1287 bank->saved_wakeup = __raw_readl(wake_status);
1288 __raw_writel(0xffffffff, wake_clear);
1289 __raw_writel(bank->suspend_wakeup, wake_set);
1290 spin_unlock(&bank->lock);
1296 static int omap_gpio_resume(struct sys_device *dev)
1300 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1303 for (i = 0; i < gpio_bank_count; i++) {
1304 struct gpio_bank *bank = &gpio_bank[i];
1305 void __iomem *wake_clear;
1306 void __iomem *wake_set;
1308 switch (bank->method) {
1309 #ifdef CONFIG_ARCH_OMAP16XX
1310 case METHOD_GPIO_1610:
1311 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1312 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1315 #ifdef CONFIG_ARCH_OMAP24XX
1316 case METHOD_GPIO_24XX:
1317 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1318 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1325 spin_lock(&bank->lock);
1326 __raw_writel(0xffffffff, wake_clear);
1327 __raw_writel(bank->saved_wakeup, wake_set);
1328 spin_unlock(&bank->lock);
1334 static struct sysdev_class omap_gpio_sysclass = {
1335 set_kset_name("gpio"),
1336 .suspend = omap_gpio_suspend,
1337 .resume = omap_gpio_resume,
1340 static struct sys_device omap_gpio_device = {
1342 .cls = &omap_gpio_sysclass,
1347 #ifdef CONFIG_ARCH_OMAP24XX
1349 static int workaround_enabled;
1351 void omap2_gpio_prepare_for_retention(void)
1355 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1356 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1357 for (i = 0; i < gpio_bank_count; i++) {
1358 struct gpio_bank *bank = &gpio_bank[i];
1361 if (!(bank->enabled_non_wakeup_gpios))
1363 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1364 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1365 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1366 bank->saved_fallingdetect = l1;
1367 bank->saved_risingdetect = l2;
1368 l1 &= ~bank->enabled_non_wakeup_gpios;
1369 l2 &= ~bank->enabled_non_wakeup_gpios;
1370 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1371 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1375 workaround_enabled = 0;
1378 workaround_enabled = 1;
1381 void omap2_gpio_resume_after_retention(void)
1385 if (!workaround_enabled)
1387 for (i = 0; i < gpio_bank_count; i++) {
1388 struct gpio_bank *bank = &gpio_bank[i];
1391 if (!(bank->enabled_non_wakeup_gpios))
1393 __raw_writel(bank->saved_fallingdetect,
1394 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1395 __raw_writel(bank->saved_risingdetect,
1396 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1397 /* Check if any of the non-wakeup interrupt GPIOs have changed
1398 * state. If so, generate an IRQ by software. This is
1399 * horribly racy, but it's the best we can do to work around
1400 * this silicon bug. */
1401 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1402 l ^= bank->saved_datain;
1403 l &= bank->non_wakeup_gpios;
1407 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1408 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1409 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1410 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1411 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1412 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1421 * This may get called early from board specific init
1422 * for boards that have interrupts routed via FPGA.
1424 int omap_gpio_init(void)
1427 return _omap_gpio_init();
1432 static int __init omap_gpio_sysinit(void)
1437 ret = _omap_gpio_init();
1439 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1440 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1442 ret = sysdev_class_register(&omap_gpio_sysclass);
1444 ret = sysdev_register(&omap_gpio_device);
1452 EXPORT_SYMBOL(omap_request_gpio);
1453 EXPORT_SYMBOL(omap_free_gpio);
1454 EXPORT_SYMBOL(omap_set_gpio_direction);
1455 EXPORT_SYMBOL(omap_set_gpio_dataout);
1456 EXPORT_SYMBOL(omap_get_gpio_datain);
1458 arch_initcall(omap_gpio_sysinit);
1461 #ifdef CONFIG_DEBUG_FS
1463 #include <linux/debugfs.h>
1464 #include <linux/seq_file.h>
1466 static int gpio_is_input(struct gpio_bank *bank, int mask)
1468 void __iomem *reg = bank->base;
1470 switch (bank->method) {
1472 reg += OMAP_MPUIO_IO_CNTL;
1474 case METHOD_GPIO_1510:
1475 reg += OMAP1510_GPIO_DIR_CONTROL;
1477 case METHOD_GPIO_1610:
1478 reg += OMAP1610_GPIO_DIRECTION;
1480 case METHOD_GPIO_730:
1481 reg += OMAP730_GPIO_DIR_CONTROL;
1483 case METHOD_GPIO_24XX:
1484 reg += OMAP24XX_GPIO_OE;
1487 return __raw_readl(reg) & mask;
1491 static int dbg_gpio_show(struct seq_file *s, void *unused)
1493 unsigned i, j, gpio;
1495 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1496 struct gpio_bank *bank = gpio_bank + i;
1497 unsigned bankwidth = 16;
1500 if (bank_is_mpuio(bank))
1501 gpio = OMAP_MPUIO(0);
1502 else if (cpu_is_omap24xx() || cpu_is_omap730())
1505 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1506 unsigned irq, value, is_in, irqstat;
1508 if (!(bank->reserved_map & mask))
1511 irq = bank->virtual_irq_start + j;
1512 value = omap_get_gpio_datain(gpio);
1513 is_in = gpio_is_input(bank, mask);
1515 if (bank_is_mpuio(bank))
1516 seq_printf(s, "MPUIO %2d: ", j);
1518 seq_printf(s, "GPIO %3d: ", gpio);
1519 seq_printf(s, "%s %s",
1520 is_in ? "in " : "out",
1521 value ? "hi" : "lo");
1523 irqstat = irq_desc[irq].status;
1524 if (is_in && ((bank->suspend_wakeup & mask)
1525 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1526 char *trigger = NULL;
1528 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1529 case IRQ_TYPE_EDGE_FALLING:
1530 trigger = "falling";
1532 case IRQ_TYPE_EDGE_RISING:
1535 case IRQ_TYPE_EDGE_BOTH:
1536 trigger = "bothedge";
1538 case IRQ_TYPE_LEVEL_LOW:
1541 case IRQ_TYPE_LEVEL_HIGH:
1545 trigger = "(unspecified)";
1548 seq_printf(s, ", irq-%d %s%s",
1550 (bank->suspend_wakeup & mask)
1553 seq_printf(s, "\n");
1556 if (bank_is_mpuio(bank)) {
1557 seq_printf(s, "\n");
1564 static int dbg_gpio_open(struct inode *inode, struct file *file)
1566 return single_open(file, dbg_gpio_show, &inode->i_private);
1569 static const struct file_operations debug_fops = {
1570 .open = dbg_gpio_open,
1572 .llseek = seq_lseek,
1573 .release = single_release,
1576 static int __init omap_gpio_debuginit(void)
1578 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1579 NULL, NULL, &debug_fops);
1582 late_initcall(omap_gpio_debuginit);