2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_CTRL 0x0030
105 #define OMAP24XX_GPIO_OE 0x0034
106 #define OMAP24XX_GPIO_DATAIN 0x0038
107 #define OMAP24XX_GPIO_DATAOUT 0x003c
108 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
109 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
110 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
111 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
112 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
113 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
122 * omap34xx specific GPIO registers
125 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
126 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
127 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
128 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
129 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
130 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
132 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
137 u16 virtual_irq_start;
139 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
143 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 u32 non_wakeup_gpios;
145 u32 enabled_non_wakeup_gpios;
148 u32 saved_fallingdetect;
149 u32 saved_risingdetect;
153 struct gpio_chip chip;
157 #define METHOD_MPUIO 0
158 #define METHOD_GPIO_1510 1
159 #define METHOD_GPIO_1610 2
160 #define METHOD_GPIO_730 3
161 #define METHOD_GPIO_24XX 4
163 #ifdef CONFIG_ARCH_OMAP16XX
164 static struct gpio_bank gpio_bank_1610[5] = {
165 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
166 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
173 #ifdef CONFIG_ARCH_OMAP15XX
174 static struct gpio_bank gpio_bank_1510[2] = {
175 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
176 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
180 #ifdef CONFIG_ARCH_OMAP730
181 static struct gpio_bank gpio_bank_730[7] = {
182 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
183 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
184 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
185 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
186 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
187 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
188 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
192 #ifdef CONFIG_ARCH_OMAP24XX
194 static struct gpio_bank gpio_bank_242x[4] = {
195 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
201 static struct gpio_bank gpio_bank_243x[5] = {
202 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
211 #ifdef CONFIG_ARCH_OMAP34XX
212 static struct gpio_bank gpio_bank_34xx[6] = {
213 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
223 static struct gpio_bank *gpio_bank;
224 static int gpio_bank_count;
226 static inline struct gpio_bank *get_gpio_bank(int gpio)
228 if (cpu_is_omap15xx()) {
229 if (OMAP_GPIO_IS_MPUIO(gpio))
230 return &gpio_bank[0];
231 return &gpio_bank[1];
233 if (cpu_is_omap16xx()) {
234 if (OMAP_GPIO_IS_MPUIO(gpio))
235 return &gpio_bank[0];
236 return &gpio_bank[1 + (gpio >> 4)];
238 if (cpu_is_omap730()) {
239 if (OMAP_GPIO_IS_MPUIO(gpio))
240 return &gpio_bank[0];
241 return &gpio_bank[1 + (gpio >> 5)];
243 if (cpu_is_omap24xx())
244 return &gpio_bank[gpio >> 5];
245 if (cpu_is_omap34xx())
246 return &gpio_bank[gpio >> 5];
249 static inline int get_gpio_index(int gpio)
251 if (cpu_is_omap730())
253 if (cpu_is_omap24xx())
255 if (cpu_is_omap34xx())
260 static inline int gpio_valid(int gpio)
264 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
265 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
269 if (cpu_is_omap15xx() && gpio < 16)
271 if ((cpu_is_omap16xx()) && gpio < 64)
273 if (cpu_is_omap730() && gpio < 192)
275 if (cpu_is_omap24xx() && gpio < 128)
277 if (cpu_is_omap34xx() && gpio < 160)
282 static int check_gpio(int gpio)
284 if (unlikely(gpio_valid(gpio)) < 0) {
285 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
292 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
294 void __iomem *reg = bank->base;
297 switch (bank->method) {
298 #ifdef CONFIG_ARCH_OMAP1
300 reg += OMAP_MPUIO_IO_CNTL;
303 #ifdef CONFIG_ARCH_OMAP15XX
304 case METHOD_GPIO_1510:
305 reg += OMAP1510_GPIO_DIR_CONTROL;
308 #ifdef CONFIG_ARCH_OMAP16XX
309 case METHOD_GPIO_1610:
310 reg += OMAP1610_GPIO_DIRECTION;
313 #ifdef CONFIG_ARCH_OMAP730
314 case METHOD_GPIO_730:
315 reg += OMAP730_GPIO_DIR_CONTROL;
318 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
319 case METHOD_GPIO_24XX:
320 reg += OMAP24XX_GPIO_OE;
327 l = __raw_readl(reg);
332 __raw_writel(l, reg);
335 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
337 void __iomem *reg = bank->base;
340 switch (bank->method) {
341 #ifdef CONFIG_ARCH_OMAP1
343 reg += OMAP_MPUIO_OUTPUT;
344 l = __raw_readl(reg);
351 #ifdef CONFIG_ARCH_OMAP15XX
352 case METHOD_GPIO_1510:
353 reg += OMAP1510_GPIO_DATA_OUTPUT;
354 l = __raw_readl(reg);
361 #ifdef CONFIG_ARCH_OMAP16XX
362 case METHOD_GPIO_1610:
364 reg += OMAP1610_GPIO_SET_DATAOUT;
366 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
370 #ifdef CONFIG_ARCH_OMAP730
371 case METHOD_GPIO_730:
372 reg += OMAP730_GPIO_DATA_OUTPUT;
373 l = __raw_readl(reg);
380 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
381 case METHOD_GPIO_24XX:
383 reg += OMAP24XX_GPIO_SETDATAOUT;
385 reg += OMAP24XX_GPIO_CLEARDATAOUT;
393 __raw_writel(l, reg);
396 static int __omap_get_gpio_datain(int gpio)
398 struct gpio_bank *bank;
401 if (check_gpio(gpio) < 0)
403 bank = get_gpio_bank(gpio);
405 switch (bank->method) {
406 #ifdef CONFIG_ARCH_OMAP1
408 reg += OMAP_MPUIO_INPUT_LATCH;
411 #ifdef CONFIG_ARCH_OMAP15XX
412 case METHOD_GPIO_1510:
413 reg += OMAP1510_GPIO_DATA_INPUT;
416 #ifdef CONFIG_ARCH_OMAP16XX
417 case METHOD_GPIO_1610:
418 reg += OMAP1610_GPIO_DATAIN;
421 #ifdef CONFIG_ARCH_OMAP730
422 case METHOD_GPIO_730:
423 reg += OMAP730_GPIO_DATA_INPUT;
426 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
427 case METHOD_GPIO_24XX:
428 reg += OMAP24XX_GPIO_DATAIN;
434 return (__raw_readl(reg)
435 & (1 << get_gpio_index(gpio))) != 0;
438 #define MOD_REG_BIT(reg, bit_mask, set) \
440 int l = __raw_readl(base + reg); \
441 if (set) l |= bit_mask; \
442 else l &= ~bit_mask; \
443 __raw_writel(l, base + reg); \
446 void omap_set_gpio_debounce(int gpio, int enable)
448 struct gpio_bank *bank;
450 u32 val, l = 1 << get_gpio_index(gpio);
452 if (cpu_class_is_omap1())
455 bank = get_gpio_bank(gpio);
458 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
459 val = __raw_readl(reg);
461 if (enable && !(val & l))
463 else if (!enable && val & l)
468 if (cpu_is_omap34xx())
469 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
471 __raw_writel(val, reg);
473 EXPORT_SYMBOL(omap_set_gpio_debounce);
475 void omap_set_gpio_debounce_time(int gpio, int enc_time)
477 struct gpio_bank *bank;
480 if (cpu_class_is_omap1())
483 bank = get_gpio_bank(gpio);
487 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
488 __raw_writel(enc_time, reg);
490 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
492 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
493 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
496 void __iomem *base = bank->base;
497 u32 gpio_bit = 1 << gpio;
499 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
500 trigger & IRQ_TYPE_LEVEL_LOW);
501 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
502 trigger & IRQ_TYPE_LEVEL_HIGH);
503 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
504 trigger & IRQ_TYPE_EDGE_RISING);
505 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
506 trigger & IRQ_TYPE_EDGE_FALLING);
508 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
510 __raw_writel(1 << gpio, bank->base
511 + OMAP24XX_GPIO_SETWKUENA);
513 __raw_writel(1 << gpio, bank->base
514 + OMAP24XX_GPIO_CLEARWKUENA);
517 bank->enabled_non_wakeup_gpios |= gpio_bit;
519 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
523 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
524 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
528 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
530 void __iomem *reg = bank->base;
533 switch (bank->method) {
534 #ifdef CONFIG_ARCH_OMAP1
536 reg += OMAP_MPUIO_GPIO_INT_EDGE;
537 l = __raw_readl(reg);
538 if (trigger & IRQ_TYPE_EDGE_RISING)
540 else if (trigger & IRQ_TYPE_EDGE_FALLING)
546 #ifdef CONFIG_ARCH_OMAP15XX
547 case METHOD_GPIO_1510:
548 reg += OMAP1510_GPIO_INT_CONTROL;
549 l = __raw_readl(reg);
550 if (trigger & IRQ_TYPE_EDGE_RISING)
552 else if (trigger & IRQ_TYPE_EDGE_FALLING)
558 #ifdef CONFIG_ARCH_OMAP16XX
559 case METHOD_GPIO_1610:
561 reg += OMAP1610_GPIO_EDGE_CTRL2;
563 reg += OMAP1610_GPIO_EDGE_CTRL1;
565 l = __raw_readl(reg);
566 l &= ~(3 << (gpio << 1));
567 if (trigger & IRQ_TYPE_EDGE_RISING)
568 l |= 2 << (gpio << 1);
569 if (trigger & IRQ_TYPE_EDGE_FALLING)
570 l |= 1 << (gpio << 1);
572 /* Enable wake-up during idle for dynamic tick */
573 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
575 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
578 #ifdef CONFIG_ARCH_OMAP730
579 case METHOD_GPIO_730:
580 reg += OMAP730_GPIO_INT_CONTROL;
581 l = __raw_readl(reg);
582 if (trigger & IRQ_TYPE_EDGE_RISING)
584 else if (trigger & IRQ_TYPE_EDGE_FALLING)
590 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
591 case METHOD_GPIO_24XX:
592 set_24xx_gpio_triggering(bank, gpio, trigger);
598 __raw_writel(l, reg);
604 static int gpio_irq_type(unsigned irq, unsigned type)
606 struct gpio_bank *bank;
611 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
612 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
614 gpio = irq - IH_GPIO_BASE;
616 if (check_gpio(gpio) < 0)
619 if (type & ~IRQ_TYPE_SENSE_MASK)
622 /* OMAP1 allows only only edge triggering */
623 if (!cpu_class_is_omap2()
624 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
627 bank = get_irq_chip_data(irq);
628 spin_lock_irqsave(&bank->lock, flags);
629 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
631 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
632 irq_desc[irq].status |= type;
634 spin_unlock_irqrestore(&bank->lock, flags);
636 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
637 __set_irq_handler_unlocked(irq, handle_level_irq);
638 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
639 __set_irq_handler_unlocked(irq, handle_edge_irq);
644 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
646 void __iomem *reg = bank->base;
648 switch (bank->method) {
649 #ifdef CONFIG_ARCH_OMAP1
651 /* MPUIO irqstatus is reset by reading the status register,
652 * so do nothing here */
655 #ifdef CONFIG_ARCH_OMAP15XX
656 case METHOD_GPIO_1510:
657 reg += OMAP1510_GPIO_INT_STATUS;
660 #ifdef CONFIG_ARCH_OMAP16XX
661 case METHOD_GPIO_1610:
662 reg += OMAP1610_GPIO_IRQSTATUS1;
665 #ifdef CONFIG_ARCH_OMAP730
666 case METHOD_GPIO_730:
667 reg += OMAP730_GPIO_INT_STATUS;
670 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
671 case METHOD_GPIO_24XX:
672 reg += OMAP24XX_GPIO_IRQSTATUS1;
679 __raw_writel(gpio_mask, reg);
681 /* Workaround for clearing DSP GPIO interrupts to allow retention */
682 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
683 if (cpu_is_omap24xx() || cpu_is_omap34xx())
684 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
688 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
690 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
693 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
695 void __iomem *reg = bank->base;
700 switch (bank->method) {
701 #ifdef CONFIG_ARCH_OMAP1
703 reg += OMAP_MPUIO_GPIO_MASKIT;
708 #ifdef CONFIG_ARCH_OMAP15XX
709 case METHOD_GPIO_1510:
710 reg += OMAP1510_GPIO_INT_MASK;
715 #ifdef CONFIG_ARCH_OMAP16XX
716 case METHOD_GPIO_1610:
717 reg += OMAP1610_GPIO_IRQENABLE1;
721 #ifdef CONFIG_ARCH_OMAP730
722 case METHOD_GPIO_730:
723 reg += OMAP730_GPIO_INT_MASK;
728 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
729 case METHOD_GPIO_24XX:
730 reg += OMAP24XX_GPIO_IRQENABLE1;
739 l = __raw_readl(reg);
746 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
748 void __iomem *reg = bank->base;
751 switch (bank->method) {
752 #ifdef CONFIG_ARCH_OMAP1
754 reg += OMAP_MPUIO_GPIO_MASKIT;
755 l = __raw_readl(reg);
762 #ifdef CONFIG_ARCH_OMAP15XX
763 case METHOD_GPIO_1510:
764 reg += OMAP1510_GPIO_INT_MASK;
765 l = __raw_readl(reg);
772 #ifdef CONFIG_ARCH_OMAP16XX
773 case METHOD_GPIO_1610:
775 reg += OMAP1610_GPIO_SET_IRQENABLE1;
777 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
781 #ifdef CONFIG_ARCH_OMAP730
782 case METHOD_GPIO_730:
783 reg += OMAP730_GPIO_INT_MASK;
784 l = __raw_readl(reg);
791 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
792 case METHOD_GPIO_24XX:
794 reg += OMAP24XX_GPIO_SETIRQENABLE1;
796 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
804 __raw_writel(l, reg);
807 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
809 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
813 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
814 * 1510 does not seem to have a wake-up register. If JTAG is connected
815 * to the target, system will wake up always on GPIO events. While
816 * system is running all registered GPIO interrupts need to have wake-up
817 * enabled. When system is suspended, only selected GPIO interrupts need
818 * to have wake-up enabled.
820 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
824 switch (bank->method) {
825 #ifdef CONFIG_ARCH_OMAP16XX
827 case METHOD_GPIO_1610:
828 spin_lock_irqsave(&bank->lock, flags);
830 bank->suspend_wakeup |= (1 << gpio);
831 enable_irq_wake(bank->irq);
833 disable_irq_wake(bank->irq);
834 bank->suspend_wakeup &= ~(1 << gpio);
836 spin_unlock_irqrestore(&bank->lock, flags);
839 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
840 case METHOD_GPIO_24XX:
841 if (bank->non_wakeup_gpios & (1 << gpio)) {
842 printk(KERN_ERR "Unable to modify wakeup on "
843 "non-wakeup GPIO%d\n",
844 (bank - gpio_bank) * 32 + gpio);
847 spin_lock_irqsave(&bank->lock, flags);
849 bank->suspend_wakeup |= (1 << gpio);
850 enable_irq_wake(bank->irq);
852 disable_irq_wake(bank->irq);
853 bank->suspend_wakeup &= ~(1 << gpio);
855 spin_unlock_irqrestore(&bank->lock, flags);
859 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
865 static void _reset_gpio(struct gpio_bank *bank, int gpio)
867 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
868 _set_gpio_irqenable(bank, gpio, 0);
869 _clear_gpio_irqstatus(bank, gpio);
870 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
873 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
874 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
876 unsigned int gpio = irq - IH_GPIO_BASE;
877 struct gpio_bank *bank;
880 if (check_gpio(gpio) < 0)
882 bank = get_irq_chip_data(irq);
883 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
888 int omap_request_gpio(int gpio)
890 struct gpio_bank *bank;
894 if (check_gpio(gpio) < 0)
897 status = gpio_request(gpio, NULL);
901 bank = get_gpio_bank(gpio);
902 spin_lock_irqsave(&bank->lock, flags);
904 /* Set trigger to none. You need to enable the desired trigger with
905 * request_irq() or set_irq_type().
907 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
909 #ifdef CONFIG_ARCH_OMAP15XX
910 if (bank->method == METHOD_GPIO_1510) {
913 /* Claim the pin for MPU */
914 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
915 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
918 spin_unlock_irqrestore(&bank->lock, flags);
923 void omap_free_gpio(int gpio)
925 struct gpio_bank *bank;
928 if (check_gpio(gpio) < 0)
930 bank = get_gpio_bank(gpio);
931 spin_lock_irqsave(&bank->lock, flags);
932 if (unlikely(!gpiochip_is_requested(&bank->chip,
933 get_gpio_index(gpio)))) {
934 spin_unlock_irqrestore(&bank->lock, flags);
935 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
939 #ifdef CONFIG_ARCH_OMAP16XX
940 if (bank->method == METHOD_GPIO_1610) {
941 /* Disable wake-up during idle for dynamic tick */
942 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
943 __raw_writel(1 << get_gpio_index(gpio), reg);
946 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
947 if (bank->method == METHOD_GPIO_24XX) {
948 /* Disable wake-up during idle for dynamic tick */
949 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
950 __raw_writel(1 << get_gpio_index(gpio), reg);
953 _reset_gpio(bank, gpio);
954 spin_unlock_irqrestore(&bank->lock, flags);
959 * We need to unmask the GPIO bank interrupt as soon as possible to
960 * avoid missing GPIO interrupts for other lines in the bank.
961 * Then we need to mask-read-clear-unmask the triggered GPIO lines
962 * in the bank to avoid missing nested interrupts for a GPIO line.
963 * If we wait to unmask individual GPIO lines in the bank after the
964 * line's interrupt handler has been run, we may miss some nested
967 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
969 void __iomem *isr_reg = NULL;
971 unsigned int gpio_irq;
972 struct gpio_bank *bank;
976 desc->chip->ack(irq);
978 bank = get_irq_data(irq);
979 #ifdef CONFIG_ARCH_OMAP1
980 if (bank->method == METHOD_MPUIO)
981 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
983 #ifdef CONFIG_ARCH_OMAP15XX
984 if (bank->method == METHOD_GPIO_1510)
985 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
987 #if defined(CONFIG_ARCH_OMAP16XX)
988 if (bank->method == METHOD_GPIO_1610)
989 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
991 #ifdef CONFIG_ARCH_OMAP730
992 if (bank->method == METHOD_GPIO_730)
993 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
995 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
996 if (bank->method == METHOD_GPIO_24XX)
997 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1000 u32 isr_saved, level_mask = 0;
1003 enabled = _get_gpio_irqbank_mask(bank);
1004 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1006 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1009 if (cpu_class_is_omap2()) {
1010 level_mask = bank->level_mask & enabled;
1013 /* clear edge sensitive interrupts before handler(s) are
1014 called so that we don't miss any interrupt occurred while
1016 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1017 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1018 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1020 /* if there is only edge sensitive GPIO pin interrupts
1021 configured, we could unmask GPIO bank interrupt immediately */
1022 if (!level_mask && !unmasked) {
1024 desc->chip->unmask(irq);
1032 gpio_irq = bank->virtual_irq_start;
1033 for (; isr != 0; isr >>= 1, gpio_irq++) {
1037 generic_handle_irq(gpio_irq);
1040 /* if bank has any level sensitive GPIO pin interrupt
1041 configured, we must unmask the bank interrupt only after
1042 handler(s) are executed in order to avoid spurious bank
1045 desc->chip->unmask(irq);
1049 static void gpio_irq_shutdown(unsigned int irq)
1051 unsigned int gpio = irq - IH_GPIO_BASE;
1052 struct gpio_bank *bank = get_irq_chip_data(irq);
1054 _reset_gpio(bank, gpio);
1057 static void gpio_ack_irq(unsigned int irq)
1059 unsigned int gpio = irq - IH_GPIO_BASE;
1060 struct gpio_bank *bank = get_irq_chip_data(irq);
1062 _clear_gpio_irqstatus(bank, gpio);
1065 static void gpio_mask_irq(unsigned int irq)
1067 unsigned int gpio = irq - IH_GPIO_BASE;
1068 struct gpio_bank *bank = get_irq_chip_data(irq);
1070 _set_gpio_irqenable(bank, gpio, 0);
1073 static void gpio_unmask_irq(unsigned int irq)
1075 unsigned int gpio = irq - IH_GPIO_BASE;
1076 struct gpio_bank *bank = get_irq_chip_data(irq);
1077 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1079 /* For level-triggered GPIOs, the clearing must be done after
1080 * the HW source is cleared, thus after the handler has run */
1081 if (bank->level_mask & irq_mask) {
1082 _set_gpio_irqenable(bank, gpio, 0);
1083 _clear_gpio_irqstatus(bank, gpio);
1086 _set_gpio_irqenable(bank, gpio, 1);
1089 static struct irq_chip gpio_irq_chip = {
1091 .shutdown = gpio_irq_shutdown,
1092 .ack = gpio_ack_irq,
1093 .mask = gpio_mask_irq,
1094 .unmask = gpio_unmask_irq,
1095 .set_type = gpio_irq_type,
1096 .set_wake = gpio_wake_enable,
1099 /*---------------------------------------------------------------------*/
1101 #ifdef CONFIG_ARCH_OMAP1
1103 /* MPUIO uses the always-on 32k clock */
1105 static void mpuio_ack_irq(unsigned int irq)
1107 /* The ISR is reset automatically, so do nothing here. */
1110 static void mpuio_mask_irq(unsigned int irq)
1112 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1113 struct gpio_bank *bank = get_irq_chip_data(irq);
1115 _set_gpio_irqenable(bank, gpio, 0);
1118 static void mpuio_unmask_irq(unsigned int irq)
1120 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1121 struct gpio_bank *bank = get_irq_chip_data(irq);
1123 _set_gpio_irqenable(bank, gpio, 1);
1126 static struct irq_chip mpuio_irq_chip = {
1128 .ack = mpuio_ack_irq,
1129 .mask = mpuio_mask_irq,
1130 .unmask = mpuio_unmask_irq,
1131 .set_type = gpio_irq_type,
1132 #ifdef CONFIG_ARCH_OMAP16XX
1133 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1134 .set_wake = gpio_wake_enable,
1139 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1142 #ifdef CONFIG_ARCH_OMAP16XX
1144 #include <linux/platform_device.h>
1146 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1148 struct gpio_bank *bank = platform_get_drvdata(pdev);
1149 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1150 unsigned long flags;
1152 spin_lock_irqsave(&bank->lock, flags);
1153 bank->saved_wakeup = __raw_readl(mask_reg);
1154 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1155 spin_unlock_irqrestore(&bank->lock, flags);
1160 static int omap_mpuio_resume_early(struct platform_device *pdev)
1162 struct gpio_bank *bank = platform_get_drvdata(pdev);
1163 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1164 unsigned long flags;
1166 spin_lock_irqsave(&bank->lock, flags);
1167 __raw_writel(bank->saved_wakeup, mask_reg);
1168 spin_unlock_irqrestore(&bank->lock, flags);
1173 /* use platform_driver for this, now that there's no longer any
1174 * point to sys_device (other than not disturbing old code).
1176 static struct platform_driver omap_mpuio_driver = {
1177 .suspend_late = omap_mpuio_suspend_late,
1178 .resume_early = omap_mpuio_resume_early,
1184 static struct platform_device omap_mpuio_device = {
1188 .driver = &omap_mpuio_driver.driver,
1190 /* could list the /proc/iomem resources */
1193 static inline void mpuio_init(void)
1195 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1197 if (platform_driver_register(&omap_mpuio_driver) == 0)
1198 (void) platform_device_register(&omap_mpuio_device);
1202 static inline void mpuio_init(void) {}
1207 extern struct irq_chip mpuio_irq_chip;
1209 #define bank_is_mpuio(bank) 0
1210 static inline void mpuio_init(void) {}
1214 /*---------------------------------------------------------------------*/
1216 /* REVISIT these are stupid implementations! replace by ones that
1217 * don't switch on METHOD_* and which mostly avoid spinlocks
1220 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1222 struct gpio_bank *bank;
1223 unsigned long flags;
1225 bank = container_of(chip, struct gpio_bank, chip);
1226 spin_lock_irqsave(&bank->lock, flags);
1227 _set_gpio_direction(bank, offset, 1);
1228 spin_unlock_irqrestore(&bank->lock, flags);
1232 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1234 return __omap_get_gpio_datain(chip->base + offset);
1237 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1239 struct gpio_bank *bank;
1240 unsigned long flags;
1242 bank = container_of(chip, struct gpio_bank, chip);
1243 spin_lock_irqsave(&bank->lock, flags);
1244 _set_gpio_dataout(bank, offset, value);
1245 _set_gpio_direction(bank, offset, 0);
1246 spin_unlock_irqrestore(&bank->lock, flags);
1250 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1252 struct gpio_bank *bank;
1253 unsigned long flags;
1255 bank = container_of(chip, struct gpio_bank, chip);
1256 spin_lock_irqsave(&bank->lock, flags);
1257 _set_gpio_dataout(bank, offset, value);
1258 spin_unlock_irqrestore(&bank->lock, flags);
1261 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1263 struct gpio_bank *bank;
1265 bank = container_of(chip, struct gpio_bank, chip);
1266 return bank->virtual_irq_start + offset;
1269 /*---------------------------------------------------------------------*/
1271 static int initialized;
1272 #if !defined(CONFIG_ARCH_OMAP3)
1273 static struct clk * gpio_ick;
1276 #if defined(CONFIG_ARCH_OMAP2)
1277 static struct clk * gpio_fck;
1280 #if defined(CONFIG_ARCH_OMAP2430)
1281 static struct clk * gpio5_ick;
1282 static struct clk * gpio5_fck;
1285 #if defined(CONFIG_ARCH_OMAP3)
1286 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1289 /* This lock class tells lockdep that GPIO irqs are in a different
1290 * category than their parents, so it won't report false recursion.
1292 static struct lock_class_key gpio_lock_class;
1294 static int __init _omap_gpio_init(void)
1298 struct gpio_bank *bank;
1303 #if defined(CONFIG_ARCH_OMAP1)
1304 if (cpu_is_omap15xx()) {
1305 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1306 if (IS_ERR(gpio_ick))
1307 printk("Could not get arm_gpio_ck\n");
1309 clk_enable(gpio_ick);
1312 #if defined(CONFIG_ARCH_OMAP2)
1313 if (cpu_class_is_omap2()) {
1314 gpio_ick = clk_get(NULL, "gpios_ick");
1315 if (IS_ERR(gpio_ick))
1316 printk("Could not get gpios_ick\n");
1318 clk_enable(gpio_ick);
1319 gpio_fck = clk_get(NULL, "gpios_fck");
1320 if (IS_ERR(gpio_fck))
1321 printk("Could not get gpios_fck\n");
1323 clk_enable(gpio_fck);
1326 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1328 #if defined(CONFIG_ARCH_OMAP2430)
1329 if (cpu_is_omap2430()) {
1330 gpio5_ick = clk_get(NULL, "gpio5_ick");
1331 if (IS_ERR(gpio5_ick))
1332 printk("Could not get gpio5_ick\n");
1334 clk_enable(gpio5_ick);
1335 gpio5_fck = clk_get(NULL, "gpio5_fck");
1336 if (IS_ERR(gpio5_fck))
1337 printk("Could not get gpio5_fck\n");
1339 clk_enable(gpio5_fck);
1345 #if defined(CONFIG_ARCH_OMAP3)
1346 if (cpu_is_omap34xx()) {
1347 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1348 sprintf(clk_name, "gpio%d_ick", i + 1);
1349 gpio_iclks[i] = clk_get(NULL, clk_name);
1350 if (IS_ERR(gpio_iclks[i]))
1351 printk(KERN_ERR "Could not get %s\n", clk_name);
1353 clk_enable(gpio_iclks[i]);
1359 #ifdef CONFIG_ARCH_OMAP15XX
1360 if (cpu_is_omap15xx()) {
1361 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1362 gpio_bank_count = 2;
1363 gpio_bank = gpio_bank_1510;
1366 #if defined(CONFIG_ARCH_OMAP16XX)
1367 if (cpu_is_omap16xx()) {
1370 gpio_bank_count = 5;
1371 gpio_bank = gpio_bank_1610;
1372 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1373 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1374 (rev >> 4) & 0x0f, rev & 0x0f);
1377 #ifdef CONFIG_ARCH_OMAP730
1378 if (cpu_is_omap730()) {
1379 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1380 gpio_bank_count = 7;
1381 gpio_bank = gpio_bank_730;
1385 #ifdef CONFIG_ARCH_OMAP24XX
1386 if (cpu_is_omap242x()) {
1389 gpio_bank_count = 4;
1390 gpio_bank = gpio_bank_242x;
1391 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1392 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1393 (rev >> 4) & 0x0f, rev & 0x0f);
1395 if (cpu_is_omap243x()) {
1398 gpio_bank_count = 5;
1399 gpio_bank = gpio_bank_243x;
1400 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1401 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1402 (rev >> 4) & 0x0f, rev & 0x0f);
1405 #ifdef CONFIG_ARCH_OMAP34XX
1406 if (cpu_is_omap34xx()) {
1409 gpio_bank_count = OMAP34XX_NR_GPIOS;
1410 gpio_bank = gpio_bank_34xx;
1411 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1412 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1413 (rev >> 4) & 0x0f, rev & 0x0f);
1416 for (i = 0; i < gpio_bank_count; i++) {
1417 int j, gpio_count = 16;
1419 bank = &gpio_bank[i];
1420 spin_lock_init(&bank->lock);
1421 if (bank_is_mpuio(bank))
1422 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1423 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1424 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1425 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1427 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1428 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1429 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1430 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1432 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1433 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1434 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1436 gpio_count = 32; /* 730 has 32-bit GPIOs */
1439 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1440 if (bank->method == METHOD_GPIO_24XX) {
1441 static const u32 non_wakeup_gpios[] = {
1442 0xe203ffc0, 0x08700040
1445 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1446 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1447 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1449 /* Initialize interface clock ungated, module enabled */
1450 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1451 if (i < ARRAY_SIZE(non_wakeup_gpios))
1452 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1457 /* REVISIT eventually switch from OMAP-specific gpio structs
1458 * over to the generic ones
1460 bank->chip.direction_input = gpio_input;
1461 bank->chip.get = gpio_get;
1462 bank->chip.direction_output = gpio_output;
1463 bank->chip.set = gpio_set;
1464 bank->chip.to_irq = gpio_2irq;
1465 if (bank_is_mpuio(bank)) {
1466 bank->chip.label = "mpuio";
1467 #ifdef CONFIG_ARCH_OMAP16XX
1468 bank->chip.dev = &omap_mpuio_device.dev;
1470 bank->chip.base = OMAP_MPUIO(0);
1472 bank->chip.label = "gpio";
1473 bank->chip.base = gpio;
1476 bank->chip.ngpio = gpio_count;
1478 gpiochip_add(&bank->chip);
1480 for (j = bank->virtual_irq_start;
1481 j < bank->virtual_irq_start + gpio_count; j++) {
1482 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1483 set_irq_chip_data(j, bank);
1484 if (bank_is_mpuio(bank))
1485 set_irq_chip(j, &mpuio_irq_chip);
1487 set_irq_chip(j, &gpio_irq_chip);
1488 set_irq_handler(j, handle_simple_irq);
1489 set_irq_flags(j, IRQF_VALID);
1491 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1492 set_irq_data(bank->irq, bank);
1494 if (cpu_is_omap34xx()) {
1495 sprintf(clk_name, "gpio%d_dbck", i + 1);
1496 bank->dbck = clk_get(NULL, clk_name);
1497 if (IS_ERR(bank->dbck))
1498 printk(KERN_ERR "Could not get %s\n", clk_name);
1502 /* Enable system clock for GPIO module.
1503 * The CAM_CLK_CTRL *is* really the right place. */
1504 if (cpu_is_omap16xx())
1505 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1507 /* Enable autoidle for the OCP interface */
1508 if (cpu_is_omap24xx())
1509 omap_writel(1 << 0, 0x48019010);
1510 if (cpu_is_omap34xx())
1511 omap_writel(1 << 0, 0x48306814);
1516 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1517 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1521 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1524 for (i = 0; i < gpio_bank_count; i++) {
1525 struct gpio_bank *bank = &gpio_bank[i];
1526 void __iomem *wake_status;
1527 void __iomem *wake_clear;
1528 void __iomem *wake_set;
1529 unsigned long flags;
1531 switch (bank->method) {
1532 #ifdef CONFIG_ARCH_OMAP16XX
1533 case METHOD_GPIO_1610:
1534 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1535 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1536 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1539 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1540 case METHOD_GPIO_24XX:
1541 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1542 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1543 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1550 spin_lock_irqsave(&bank->lock, flags);
1551 bank->saved_wakeup = __raw_readl(wake_status);
1552 __raw_writel(0xffffffff, wake_clear);
1553 __raw_writel(bank->suspend_wakeup, wake_set);
1554 spin_unlock_irqrestore(&bank->lock, flags);
1560 static int omap_gpio_resume(struct sys_device *dev)
1564 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1567 for (i = 0; i < gpio_bank_count; i++) {
1568 struct gpio_bank *bank = &gpio_bank[i];
1569 void __iomem *wake_clear;
1570 void __iomem *wake_set;
1571 unsigned long flags;
1573 switch (bank->method) {
1574 #ifdef CONFIG_ARCH_OMAP16XX
1575 case METHOD_GPIO_1610:
1576 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1577 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1580 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1581 case METHOD_GPIO_24XX:
1582 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1583 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1590 spin_lock_irqsave(&bank->lock, flags);
1591 __raw_writel(0xffffffff, wake_clear);
1592 __raw_writel(bank->saved_wakeup, wake_set);
1593 spin_unlock_irqrestore(&bank->lock, flags);
1599 static struct sysdev_class omap_gpio_sysclass = {
1601 .suspend = omap_gpio_suspend,
1602 .resume = omap_gpio_resume,
1605 static struct sys_device omap_gpio_device = {
1607 .cls = &omap_gpio_sysclass,
1612 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1614 static int workaround_enabled;
1616 void omap2_gpio_prepare_for_retention(void)
1620 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1621 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1622 for (i = 0; i < gpio_bank_count; i++) {
1623 struct gpio_bank *bank = &gpio_bank[i];
1626 if (!(bank->enabled_non_wakeup_gpios))
1628 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1629 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1630 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1631 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1633 bank->saved_fallingdetect = l1;
1634 bank->saved_risingdetect = l2;
1635 l1 &= ~bank->enabled_non_wakeup_gpios;
1636 l2 &= ~bank->enabled_non_wakeup_gpios;
1637 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1638 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1639 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1644 workaround_enabled = 0;
1647 workaround_enabled = 1;
1650 void omap2_gpio_resume_after_retention(void)
1654 if (!workaround_enabled)
1656 for (i = 0; i < gpio_bank_count; i++) {
1657 struct gpio_bank *bank = &gpio_bank[i];
1660 if (!(bank->enabled_non_wakeup_gpios))
1662 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1663 __raw_writel(bank->saved_fallingdetect,
1664 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1665 __raw_writel(bank->saved_risingdetect,
1666 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1668 /* Check if any of the non-wakeup interrupt GPIOs have changed
1669 * state. If so, generate an IRQ by software. This is
1670 * horribly racy, but it's the best we can do to work around
1671 * this silicon bug. */
1672 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1673 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1675 l ^= bank->saved_datain;
1676 l &= bank->non_wakeup_gpios;
1679 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1680 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1681 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1682 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1683 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1684 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1685 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1695 * This may get called early from board specific init
1696 * for boards that have interrupts routed via FPGA.
1698 int __init omap_gpio_init(void)
1701 return _omap_gpio_init();
1706 static int __init omap_gpio_sysinit(void)
1711 ret = _omap_gpio_init();
1715 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1716 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1718 ret = sysdev_class_register(&omap_gpio_sysclass);
1720 ret = sysdev_register(&omap_gpio_device);
1728 EXPORT_SYMBOL(omap_request_gpio);
1729 EXPORT_SYMBOL(omap_free_gpio);
1731 arch_initcall(omap_gpio_sysinit);
1734 #ifdef CONFIG_DEBUG_FS
1736 #include <linux/debugfs.h>
1737 #include <linux/seq_file.h>
1739 static int gpio_is_input(struct gpio_bank *bank, int mask)
1741 void __iomem *reg = bank->base;
1743 switch (bank->method) {
1745 reg += OMAP_MPUIO_IO_CNTL;
1747 case METHOD_GPIO_1510:
1748 reg += OMAP1510_GPIO_DIR_CONTROL;
1750 case METHOD_GPIO_1610:
1751 reg += OMAP1610_GPIO_DIRECTION;
1753 case METHOD_GPIO_730:
1754 reg += OMAP730_GPIO_DIR_CONTROL;
1756 case METHOD_GPIO_24XX:
1757 reg += OMAP24XX_GPIO_OE;
1760 return __raw_readl(reg) & mask;
1764 static int dbg_gpio_show(struct seq_file *s, void *unused)
1766 unsigned i, j, gpio;
1768 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1769 struct gpio_bank *bank = gpio_bank + i;
1770 unsigned bankwidth = 16;
1773 if (bank_is_mpuio(bank))
1774 gpio = OMAP_MPUIO(0);
1775 else if (cpu_class_is_omap2() || cpu_is_omap730())
1778 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1779 unsigned irq, value, is_in, irqstat;
1782 label = gpiochip_is_requested(&bank->chip, j);
1786 irq = bank->virtual_irq_start + j;
1787 value = gpio_get_value(gpio);
1788 is_in = gpio_is_input(bank, mask);
1790 if (bank_is_mpuio(bank))
1791 seq_printf(s, "MPUIO %2d ", j);
1793 seq_printf(s, "GPIO %3d ", gpio);
1794 seq_printf(s, "(%10s): %s %s",
1796 is_in ? "in " : "out",
1797 value ? "hi" : "lo");
1799 /* FIXME for at least omap2, show pullup/pulldown state */
1801 irqstat = irq_desc[irq].status;
1802 if (is_in && ((bank->suspend_wakeup & mask)
1803 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1804 char *trigger = NULL;
1806 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1807 case IRQ_TYPE_EDGE_FALLING:
1808 trigger = "falling";
1810 case IRQ_TYPE_EDGE_RISING:
1813 case IRQ_TYPE_EDGE_BOTH:
1814 trigger = "bothedge";
1816 case IRQ_TYPE_LEVEL_LOW:
1819 case IRQ_TYPE_LEVEL_HIGH:
1826 seq_printf(s, ", irq-%d %-8s%s",
1828 (bank->suspend_wakeup & mask)
1831 seq_printf(s, "\n");
1834 if (bank_is_mpuio(bank)) {
1835 seq_printf(s, "\n");
1842 static int dbg_gpio_open(struct inode *inode, struct file *file)
1844 return single_open(file, dbg_gpio_show, &inode->i_private);
1847 static const struct file_operations debug_fops = {
1848 .open = dbg_gpio_open,
1850 .llseek = seq_lseek,
1851 .release = single_release,
1854 static int __init omap_gpio_debuginit(void)
1856 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1857 NULL, NULL, &debug_fops);
1860 late_initcall(omap_gpio_debuginit);