2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
46 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
47 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
48 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
71 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
72 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
73 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
74 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
75 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
87 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
88 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
89 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
92 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
93 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
94 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
95 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_CTRL 0x0030
105 #define OMAP24XX_GPIO_OE 0x0034
106 #define OMAP24XX_GPIO_DATAIN 0x0038
107 #define OMAP24XX_GPIO_DATAOUT 0x003c
108 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
109 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
110 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
111 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
112 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
113 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
122 * omap34xx specific GPIO registers
125 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
126 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
127 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
128 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
129 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
130 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
136 u16 virtual_irq_start;
138 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
142 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
143 u32 non_wakeup_gpios;
144 u32 enabled_non_wakeup_gpios;
147 u32 saved_fallingdetect;
148 u32 saved_risingdetect;
152 struct gpio_chip chip;
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
190 #ifdef CONFIG_ARCH_OMAP24XX
192 static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
199 static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
221 static struct gpio_bank *gpio_bank;
222 static int gpio_bank_count;
224 static inline struct gpio_bank *get_gpio_bank(int gpio)
226 if (cpu_is_omap15xx()) {
227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
247 static inline int get_gpio_index(int gpio)
249 if (cpu_is_omap730())
251 if (cpu_is_omap24xx())
253 if (cpu_is_omap34xx())
258 static inline int gpio_valid(int gpio)
262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
267 if (cpu_is_omap15xx() && gpio < 16)
269 if ((cpu_is_omap16xx()) && gpio < 64)
271 if (cpu_is_omap730() && gpio < 192)
273 if (cpu_is_omap24xx() && gpio < 128)
275 if (cpu_is_omap34xx() && gpio < 160)
280 static int check_gpio(int gpio)
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
290 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
292 void __iomem *reg = bank->base;
295 switch (bank->method) {
296 #ifdef CONFIG_ARCH_OMAP1
298 reg += OMAP_MPUIO_IO_CNTL;
301 #ifdef CONFIG_ARCH_OMAP15XX
302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
306 #ifdef CONFIG_ARCH_OMAP16XX
307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
311 #ifdef CONFIG_ARCH_OMAP730
312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
316 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
325 l = __raw_readl(reg);
330 __raw_writel(l, reg);
333 void omap_set_gpio_direction(int gpio, int is_input)
335 struct gpio_bank *bank;
338 if (check_gpio(gpio) < 0)
340 bank = get_gpio_bank(gpio);
341 spin_lock_irqsave(&bank->lock, flags);
342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
343 spin_unlock_irqrestore(&bank->lock, flags);
346 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
348 void __iomem *reg = bank->base;
351 switch (bank->method) {
352 #ifdef CONFIG_ARCH_OMAP1
354 reg += OMAP_MPUIO_OUTPUT;
355 l = __raw_readl(reg);
362 #ifdef CONFIG_ARCH_OMAP15XX
363 case METHOD_GPIO_1510:
364 reg += OMAP1510_GPIO_DATA_OUTPUT;
365 l = __raw_readl(reg);
372 #ifdef CONFIG_ARCH_OMAP16XX
373 case METHOD_GPIO_1610:
375 reg += OMAP1610_GPIO_SET_DATAOUT;
377 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
381 #ifdef CONFIG_ARCH_OMAP730
382 case METHOD_GPIO_730:
383 reg += OMAP730_GPIO_DATA_OUTPUT;
384 l = __raw_readl(reg);
391 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
392 case METHOD_GPIO_24XX:
394 reg += OMAP24XX_GPIO_SETDATAOUT;
396 reg += OMAP24XX_GPIO_CLEARDATAOUT;
404 __raw_writel(l, reg);
407 void omap_set_gpio_dataout(int gpio, int enable)
409 struct gpio_bank *bank;
412 if (check_gpio(gpio) < 0)
414 bank = get_gpio_bank(gpio);
415 spin_lock_irqsave(&bank->lock, flags);
416 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
417 spin_unlock_irqrestore(&bank->lock, flags);
420 int omap_get_gpio_datain(int gpio)
422 struct gpio_bank *bank;
425 if (check_gpio(gpio) < 0)
427 bank = get_gpio_bank(gpio);
429 switch (bank->method) {
430 #ifdef CONFIG_ARCH_OMAP1
432 reg += OMAP_MPUIO_INPUT_LATCH;
435 #ifdef CONFIG_ARCH_OMAP15XX
436 case METHOD_GPIO_1510:
437 reg += OMAP1510_GPIO_DATA_INPUT;
440 #ifdef CONFIG_ARCH_OMAP16XX
441 case METHOD_GPIO_1610:
442 reg += OMAP1610_GPIO_DATAIN;
445 #ifdef CONFIG_ARCH_OMAP730
446 case METHOD_GPIO_730:
447 reg += OMAP730_GPIO_DATA_INPUT;
450 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
451 case METHOD_GPIO_24XX:
452 reg += OMAP24XX_GPIO_DATAIN;
458 return (__raw_readl(reg)
459 & (1 << get_gpio_index(gpio))) != 0;
462 #define MOD_REG_BIT(reg, bit_mask, set) \
464 int l = __raw_readl(base + reg); \
465 if (set) l |= bit_mask; \
466 else l &= ~bit_mask; \
467 __raw_writel(l, base + reg); \
470 void omap_set_gpio_debounce(int gpio, int enable)
472 struct gpio_bank *bank;
474 u32 val, l = 1 << get_gpio_index(gpio);
476 if (cpu_class_is_omap1())
479 bank = get_gpio_bank(gpio);
482 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
483 val = __raw_readl(reg);
490 __raw_writel(val, reg);
492 EXPORT_SYMBOL(omap_set_gpio_debounce);
494 void omap_set_gpio_debounce_time(int gpio, int enc_time)
496 struct gpio_bank *bank;
499 if (cpu_class_is_omap1())
502 bank = get_gpio_bank(gpio);
506 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
507 __raw_writel(enc_time, reg);
509 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
511 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
512 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
515 void __iomem *base = bank->base;
516 u32 gpio_bit = 1 << gpio;
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
519 trigger & IRQ_TYPE_LEVEL_LOW);
520 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
521 trigger & IRQ_TYPE_LEVEL_HIGH);
522 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
523 trigger & IRQ_TYPE_EDGE_RISING);
524 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
525 trigger & IRQ_TYPE_EDGE_FALLING);
527 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
529 __raw_writel(1 << gpio, bank->base
530 + OMAP24XX_GPIO_SETWKUENA);
532 __raw_writel(1 << gpio, bank->base
533 + OMAP24XX_GPIO_CLEARWKUENA);
536 bank->enabled_non_wakeup_gpios |= gpio_bit;
538 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
542 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
543 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
547 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
549 void __iomem *reg = bank->base;
552 switch (bank->method) {
553 #ifdef CONFIG_ARCH_OMAP1
555 reg += OMAP_MPUIO_GPIO_INT_EDGE;
556 l = __raw_readl(reg);
557 if (trigger & IRQ_TYPE_EDGE_RISING)
559 else if (trigger & IRQ_TYPE_EDGE_FALLING)
565 #ifdef CONFIG_ARCH_OMAP15XX
566 case METHOD_GPIO_1510:
567 reg += OMAP1510_GPIO_INT_CONTROL;
568 l = __raw_readl(reg);
569 if (trigger & IRQ_TYPE_EDGE_RISING)
571 else if (trigger & IRQ_TYPE_EDGE_FALLING)
577 #ifdef CONFIG_ARCH_OMAP16XX
578 case METHOD_GPIO_1610:
580 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 l = __raw_readl(reg);
585 l &= ~(3 << (gpio << 1));
586 if (trigger & IRQ_TYPE_EDGE_RISING)
587 l |= 2 << (gpio << 1);
588 if (trigger & IRQ_TYPE_EDGE_FALLING)
589 l |= 1 << (gpio << 1);
591 /* Enable wake-up during idle for dynamic tick */
592 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
597 #ifdef CONFIG_ARCH_OMAP730
598 case METHOD_GPIO_730:
599 reg += OMAP730_GPIO_INT_CONTROL;
600 l = __raw_readl(reg);
601 if (trigger & IRQ_TYPE_EDGE_RISING)
603 else if (trigger & IRQ_TYPE_EDGE_FALLING)
609 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
610 case METHOD_GPIO_24XX:
611 set_24xx_gpio_triggering(bank, gpio, trigger);
617 __raw_writel(l, reg);
623 static int gpio_irq_type(unsigned irq, unsigned type)
625 struct gpio_bank *bank;
630 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
631 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
633 gpio = irq - IH_GPIO_BASE;
635 if (check_gpio(gpio) < 0)
638 if (type & ~IRQ_TYPE_SENSE_MASK)
641 /* OMAP1 allows only only edge triggering */
642 if (!cpu_class_is_omap2()
643 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
646 bank = get_irq_chip_data(irq);
647 spin_lock_irqsave(&bank->lock, flags);
648 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
650 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
651 irq_desc[irq].status |= type;
653 spin_unlock_irqrestore(&bank->lock, flags);
655 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
656 __set_irq_handler_unlocked(irq, handle_level_irq);
657 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
658 __set_irq_handler_unlocked(irq, handle_edge_irq);
663 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
665 void __iomem *reg = bank->base;
667 switch (bank->method) {
668 #ifdef CONFIG_ARCH_OMAP1
670 /* MPUIO irqstatus is reset by reading the status register,
671 * so do nothing here */
674 #ifdef CONFIG_ARCH_OMAP15XX
675 case METHOD_GPIO_1510:
676 reg += OMAP1510_GPIO_INT_STATUS;
679 #ifdef CONFIG_ARCH_OMAP16XX
680 case METHOD_GPIO_1610:
681 reg += OMAP1610_GPIO_IRQSTATUS1;
684 #ifdef CONFIG_ARCH_OMAP730
685 case METHOD_GPIO_730:
686 reg += OMAP730_GPIO_INT_STATUS;
689 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
690 case METHOD_GPIO_24XX:
691 reg += OMAP24XX_GPIO_IRQSTATUS1;
698 __raw_writel(gpio_mask, reg);
700 /* Workaround for clearing DSP GPIO interrupts to allow retention */
701 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
702 if (cpu_is_omap24xx() || cpu_is_omap34xx())
703 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
707 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
709 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
712 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
714 void __iomem *reg = bank->base;
719 switch (bank->method) {
720 #ifdef CONFIG_ARCH_OMAP1
722 reg += OMAP_MPUIO_GPIO_MASKIT;
727 #ifdef CONFIG_ARCH_OMAP15XX
728 case METHOD_GPIO_1510:
729 reg += OMAP1510_GPIO_INT_MASK;
734 #ifdef CONFIG_ARCH_OMAP16XX
735 case METHOD_GPIO_1610:
736 reg += OMAP1610_GPIO_IRQENABLE1;
740 #ifdef CONFIG_ARCH_OMAP730
741 case METHOD_GPIO_730:
742 reg += OMAP730_GPIO_INT_MASK;
747 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
748 case METHOD_GPIO_24XX:
749 reg += OMAP24XX_GPIO_IRQENABLE1;
758 l = __raw_readl(reg);
765 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
767 void __iomem *reg = bank->base;
770 switch (bank->method) {
771 #ifdef CONFIG_ARCH_OMAP1
773 reg += OMAP_MPUIO_GPIO_MASKIT;
774 l = __raw_readl(reg);
781 #ifdef CONFIG_ARCH_OMAP15XX
782 case METHOD_GPIO_1510:
783 reg += OMAP1510_GPIO_INT_MASK;
784 l = __raw_readl(reg);
791 #ifdef CONFIG_ARCH_OMAP16XX
792 case METHOD_GPIO_1610:
794 reg += OMAP1610_GPIO_SET_IRQENABLE1;
796 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
800 #ifdef CONFIG_ARCH_OMAP730
801 case METHOD_GPIO_730:
802 reg += OMAP730_GPIO_INT_MASK;
803 l = __raw_readl(reg);
810 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
811 case METHOD_GPIO_24XX:
813 reg += OMAP24XX_GPIO_SETIRQENABLE1;
815 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
823 __raw_writel(l, reg);
826 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
828 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
832 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
833 * 1510 does not seem to have a wake-up register. If JTAG is connected
834 * to the target, system will wake up always on GPIO events. While
835 * system is running all registered GPIO interrupts need to have wake-up
836 * enabled. When system is suspended, only selected GPIO interrupts need
837 * to have wake-up enabled.
839 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
843 switch (bank->method) {
844 #ifdef CONFIG_ARCH_OMAP16XX
846 case METHOD_GPIO_1610:
847 spin_lock_irqsave(&bank->lock, flags);
849 bank->suspend_wakeup |= (1 << gpio);
850 enable_irq_wake(bank->irq);
852 disable_irq_wake(bank->irq);
853 bank->suspend_wakeup &= ~(1 << gpio);
855 spin_unlock_irqrestore(&bank->lock, flags);
858 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
859 case METHOD_GPIO_24XX:
860 if (bank->non_wakeup_gpios & (1 << gpio)) {
861 printk(KERN_ERR "Unable to modify wakeup on "
862 "non-wakeup GPIO%d\n",
863 (bank - gpio_bank) * 32 + gpio);
866 spin_lock_irqsave(&bank->lock, flags);
868 bank->suspend_wakeup |= (1 << gpio);
869 enable_irq_wake(bank->irq);
871 disable_irq_wake(bank->irq);
872 bank->suspend_wakeup &= ~(1 << gpio);
874 spin_unlock_irqrestore(&bank->lock, flags);
878 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
884 static void _reset_gpio(struct gpio_bank *bank, int gpio)
886 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
887 _set_gpio_irqenable(bank, gpio, 0);
888 _clear_gpio_irqstatus(bank, gpio);
889 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
892 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
893 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
895 unsigned int gpio = irq - IH_GPIO_BASE;
896 struct gpio_bank *bank;
899 if (check_gpio(gpio) < 0)
901 bank = get_irq_chip_data(irq);
902 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
907 int omap_request_gpio(int gpio)
909 struct gpio_bank *bank;
913 if (check_gpio(gpio) < 0)
916 status = gpio_request(gpio, NULL);
920 bank = get_gpio_bank(gpio);
921 spin_lock_irqsave(&bank->lock, flags);
923 /* Set trigger to none. You need to enable the desired trigger with
924 * request_irq() or set_irq_type().
926 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
928 #ifdef CONFIG_ARCH_OMAP15XX
929 if (bank->method == METHOD_GPIO_1510) {
932 /* Claim the pin for MPU */
933 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
934 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
937 spin_unlock_irqrestore(&bank->lock, flags);
942 void omap_free_gpio(int gpio)
944 struct gpio_bank *bank;
947 if (check_gpio(gpio) < 0)
949 bank = get_gpio_bank(gpio);
950 spin_lock_irqsave(&bank->lock, flags);
951 if (unlikely(!gpiochip_is_requested(&bank->chip,
952 get_gpio_index(gpio)))) {
953 spin_unlock_irqrestore(&bank->lock, flags);
954 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
958 #ifdef CONFIG_ARCH_OMAP16XX
959 if (bank->method == METHOD_GPIO_1610) {
960 /* Disable wake-up during idle for dynamic tick */
961 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
962 __raw_writel(1 << get_gpio_index(gpio), reg);
965 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
966 if (bank->method == METHOD_GPIO_24XX) {
967 /* Disable wake-up during idle for dynamic tick */
968 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
969 __raw_writel(1 << get_gpio_index(gpio), reg);
972 _reset_gpio(bank, gpio);
973 spin_unlock_irqrestore(&bank->lock, flags);
978 * We need to unmask the GPIO bank interrupt as soon as possible to
979 * avoid missing GPIO interrupts for other lines in the bank.
980 * Then we need to mask-read-clear-unmask the triggered GPIO lines
981 * in the bank to avoid missing nested interrupts for a GPIO line.
982 * If we wait to unmask individual GPIO lines in the bank after the
983 * line's interrupt handler has been run, we may miss some nested
986 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
988 void __iomem *isr_reg = NULL;
990 unsigned int gpio_irq;
991 struct gpio_bank *bank;
995 desc->chip->ack(irq);
997 bank = get_irq_data(irq);
998 #ifdef CONFIG_ARCH_OMAP1
999 if (bank->method == METHOD_MPUIO)
1000 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1002 #ifdef CONFIG_ARCH_OMAP15XX
1003 if (bank->method == METHOD_GPIO_1510)
1004 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1006 #if defined(CONFIG_ARCH_OMAP16XX)
1007 if (bank->method == METHOD_GPIO_1610)
1008 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1010 #ifdef CONFIG_ARCH_OMAP730
1011 if (bank->method == METHOD_GPIO_730)
1012 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1014 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1015 if (bank->method == METHOD_GPIO_24XX)
1016 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1019 u32 isr_saved, level_mask = 0;
1022 enabled = _get_gpio_irqbank_mask(bank);
1023 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1025 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1028 if (cpu_class_is_omap2()) {
1029 level_mask = bank->level_mask & enabled;
1032 /* clear edge sensitive interrupts before handler(s) are
1033 called so that we don't miss any interrupt occurred while
1035 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1036 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1037 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1039 /* if there is only edge sensitive GPIO pin interrupts
1040 configured, we could unmask GPIO bank interrupt immediately */
1041 if (!level_mask && !unmasked) {
1043 desc->chip->unmask(irq);
1051 gpio_irq = bank->virtual_irq_start;
1052 for (; isr != 0; isr >>= 1, gpio_irq++) {
1057 d = irq_desc + gpio_irq;
1059 desc_handle_irq(gpio_irq, d);
1062 /* if bank has any level sensitive GPIO pin interrupt
1063 configured, we must unmask the bank interrupt only after
1064 handler(s) are executed in order to avoid spurious bank
1067 desc->chip->unmask(irq);
1071 static void gpio_irq_shutdown(unsigned int irq)
1073 unsigned int gpio = irq - IH_GPIO_BASE;
1074 struct gpio_bank *bank = get_irq_chip_data(irq);
1076 _reset_gpio(bank, gpio);
1079 static void gpio_ack_irq(unsigned int irq)
1081 unsigned int gpio = irq - IH_GPIO_BASE;
1082 struct gpio_bank *bank = get_irq_chip_data(irq);
1084 _clear_gpio_irqstatus(bank, gpio);
1087 static void gpio_mask_irq(unsigned int irq)
1089 unsigned int gpio = irq - IH_GPIO_BASE;
1090 struct gpio_bank *bank = get_irq_chip_data(irq);
1092 _set_gpio_irqenable(bank, gpio, 0);
1095 static void gpio_unmask_irq(unsigned int irq)
1097 unsigned int gpio = irq - IH_GPIO_BASE;
1098 struct gpio_bank *bank = get_irq_chip_data(irq);
1099 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1101 /* For level-triggered GPIOs, the clearing must be done after
1102 * the HW source is cleared, thus after the handler has run */
1103 if (bank->level_mask & irq_mask) {
1104 _set_gpio_irqenable(bank, gpio, 0);
1105 _clear_gpio_irqstatus(bank, gpio);
1108 _set_gpio_irqenable(bank, gpio, 1);
1111 static struct irq_chip gpio_irq_chip = {
1113 .shutdown = gpio_irq_shutdown,
1114 .ack = gpio_ack_irq,
1115 .mask = gpio_mask_irq,
1116 .unmask = gpio_unmask_irq,
1117 .set_type = gpio_irq_type,
1118 .set_wake = gpio_wake_enable,
1121 /*---------------------------------------------------------------------*/
1123 #ifdef CONFIG_ARCH_OMAP1
1125 /* MPUIO uses the always-on 32k clock */
1127 static void mpuio_ack_irq(unsigned int irq)
1129 /* The ISR is reset automatically, so do nothing here. */
1132 static void mpuio_mask_irq(unsigned int irq)
1134 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1135 struct gpio_bank *bank = get_irq_chip_data(irq);
1137 _set_gpio_irqenable(bank, gpio, 0);
1140 static void mpuio_unmask_irq(unsigned int irq)
1142 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1143 struct gpio_bank *bank = get_irq_chip_data(irq);
1145 _set_gpio_irqenable(bank, gpio, 1);
1148 static struct irq_chip mpuio_irq_chip = {
1150 .ack = mpuio_ack_irq,
1151 .mask = mpuio_mask_irq,
1152 .unmask = mpuio_unmask_irq,
1153 .set_type = gpio_irq_type,
1154 #ifdef CONFIG_ARCH_OMAP16XX
1155 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1156 .set_wake = gpio_wake_enable,
1161 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1164 #ifdef CONFIG_ARCH_OMAP16XX
1166 #include <linux/platform_device.h>
1168 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1170 struct gpio_bank *bank = platform_get_drvdata(pdev);
1171 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1172 unsigned long flags;
1174 spin_lock_irqsave(&bank->lock, flags);
1175 bank->saved_wakeup = __raw_readl(mask_reg);
1176 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1177 spin_unlock_irqrestore(&bank->lock, flags);
1182 static int omap_mpuio_resume_early(struct platform_device *pdev)
1184 struct gpio_bank *bank = platform_get_drvdata(pdev);
1185 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1186 unsigned long flags;
1188 spin_lock_irqsave(&bank->lock, flags);
1189 __raw_writel(bank->saved_wakeup, mask_reg);
1190 spin_unlock_irqrestore(&bank->lock, flags);
1195 /* use platform_driver for this, now that there's no longer any
1196 * point to sys_device (other than not disturbing old code).
1198 static struct platform_driver omap_mpuio_driver = {
1199 .suspend_late = omap_mpuio_suspend_late,
1200 .resume_early = omap_mpuio_resume_early,
1206 static struct platform_device omap_mpuio_device = {
1210 .driver = &omap_mpuio_driver.driver,
1212 /* could list the /proc/iomem resources */
1215 static inline void mpuio_init(void)
1217 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1219 if (platform_driver_register(&omap_mpuio_driver) == 0)
1220 (void) platform_device_register(&omap_mpuio_device);
1224 static inline void mpuio_init(void) {}
1229 extern struct irq_chip mpuio_irq_chip;
1231 #define bank_is_mpuio(bank) 0
1232 static inline void mpuio_init(void) {}
1236 /*---------------------------------------------------------------------*/
1238 /* REVISIT these are stupid implementations! replace by ones that
1239 * don't switch on METHOD_* and which mostly avoid spinlocks
1242 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1244 struct gpio_bank *bank;
1245 unsigned long flags;
1247 bank = container_of(chip, struct gpio_bank, chip);
1248 spin_lock_irqsave(&bank->lock, flags);
1249 _set_gpio_direction(bank, offset, 1);
1250 spin_unlock_irqrestore(&bank->lock, flags);
1254 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1256 return omap_get_gpio_datain(chip->base + offset);
1259 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1261 struct gpio_bank *bank;
1262 unsigned long flags;
1264 bank = container_of(chip, struct gpio_bank, chip);
1265 spin_lock_irqsave(&bank->lock, flags);
1266 _set_gpio_dataout(bank, offset, value);
1267 _set_gpio_direction(bank, offset, 0);
1268 spin_unlock_irqrestore(&bank->lock, flags);
1272 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1274 struct gpio_bank *bank;
1275 unsigned long flags;
1277 bank = container_of(chip, struct gpio_bank, chip);
1278 spin_lock_irqsave(&bank->lock, flags);
1279 _set_gpio_dataout(bank, offset, value);
1280 spin_unlock_irqrestore(&bank->lock, flags);
1283 /*---------------------------------------------------------------------*/
1285 static int initialized;
1286 #if !defined(CONFIG_ARCH_OMAP3)
1287 static struct clk * gpio_ick;
1290 #if defined(CONFIG_ARCH_OMAP2)
1291 static struct clk * gpio_fck;
1294 #if defined(CONFIG_ARCH_OMAP2430)
1295 static struct clk * gpio5_ick;
1296 static struct clk * gpio5_fck;
1299 #if defined(CONFIG_ARCH_OMAP3)
1300 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1301 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1304 /* This lock class tells lockdep that GPIO irqs are in a different
1305 * category than their parents, so it won't report false recursion.
1307 static struct lock_class_key gpio_lock_class;
1309 static int __init _omap_gpio_init(void)
1313 struct gpio_bank *bank;
1314 #if defined(CONFIG_ARCH_OMAP3)
1320 #if defined(CONFIG_ARCH_OMAP1)
1321 if (cpu_is_omap15xx()) {
1322 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1323 if (IS_ERR(gpio_ick))
1324 printk("Could not get arm_gpio_ck\n");
1326 clk_enable(gpio_ick);
1329 #if defined(CONFIG_ARCH_OMAP2)
1330 if (cpu_class_is_omap2()) {
1331 gpio_ick = clk_get(NULL, "gpios_ick");
1332 if (IS_ERR(gpio_ick))
1333 printk("Could not get gpios_ick\n");
1335 clk_enable(gpio_ick);
1336 gpio_fck = clk_get(NULL, "gpios_fck");
1337 if (IS_ERR(gpio_fck))
1338 printk("Could not get gpios_fck\n");
1340 clk_enable(gpio_fck);
1343 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1345 #if defined(CONFIG_ARCH_OMAP2430)
1346 if (cpu_is_omap2430()) {
1347 gpio5_ick = clk_get(NULL, "gpio5_ick");
1348 if (IS_ERR(gpio5_ick))
1349 printk("Could not get gpio5_ick\n");
1351 clk_enable(gpio5_ick);
1352 gpio5_fck = clk_get(NULL, "gpio5_fck");
1353 if (IS_ERR(gpio5_fck))
1354 printk("Could not get gpio5_fck\n");
1356 clk_enable(gpio5_fck);
1362 #if defined(CONFIG_ARCH_OMAP3)
1363 if (cpu_is_omap34xx()) {
1364 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1365 sprintf(clk_name, "gpio%d_ick", i + 1);
1366 gpio_iclks[i] = clk_get(NULL, clk_name);
1367 if (IS_ERR(gpio_iclks[i]))
1368 printk(KERN_ERR "Could not get %s\n", clk_name);
1370 clk_enable(gpio_iclks[i]);
1371 sprintf(clk_name, "gpio%d_fck", i + 1);
1372 gpio_fclks[i] = clk_get(NULL, clk_name);
1373 if (IS_ERR(gpio_fclks[i]))
1374 printk(KERN_ERR "Could not get %s\n", clk_name);
1376 clk_enable(gpio_fclks[i]);
1382 #ifdef CONFIG_ARCH_OMAP15XX
1383 if (cpu_is_omap15xx()) {
1384 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1385 gpio_bank_count = 2;
1386 gpio_bank = gpio_bank_1510;
1389 #if defined(CONFIG_ARCH_OMAP16XX)
1390 if (cpu_is_omap16xx()) {
1393 gpio_bank_count = 5;
1394 gpio_bank = gpio_bank_1610;
1395 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1396 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1397 (rev >> 4) & 0x0f, rev & 0x0f);
1400 #ifdef CONFIG_ARCH_OMAP730
1401 if (cpu_is_omap730()) {
1402 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1403 gpio_bank_count = 7;
1404 gpio_bank = gpio_bank_730;
1408 #ifdef CONFIG_ARCH_OMAP24XX
1409 if (cpu_is_omap242x()) {
1412 gpio_bank_count = 4;
1413 gpio_bank = gpio_bank_242x;
1414 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1415 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1416 (rev >> 4) & 0x0f, rev & 0x0f);
1418 if (cpu_is_omap243x()) {
1421 gpio_bank_count = 5;
1422 gpio_bank = gpio_bank_243x;
1423 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1424 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1425 (rev >> 4) & 0x0f, rev & 0x0f);
1428 #ifdef CONFIG_ARCH_OMAP34XX
1429 if (cpu_is_omap34xx()) {
1432 gpio_bank_count = OMAP34XX_NR_GPIOS;
1433 gpio_bank = gpio_bank_34xx;
1434 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1435 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1436 (rev >> 4) & 0x0f, rev & 0x0f);
1439 for (i = 0; i < gpio_bank_count; i++) {
1440 int j, gpio_count = 16;
1442 bank = &gpio_bank[i];
1443 bank->base = IO_ADDRESS(bank->base);
1444 spin_lock_init(&bank->lock);
1445 if (bank_is_mpuio(bank))
1446 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1447 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1448 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1449 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1451 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1452 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1453 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1454 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1456 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1457 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1458 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1460 gpio_count = 32; /* 730 has 32-bit GPIOs */
1463 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1464 if (bank->method == METHOD_GPIO_24XX) {
1465 static const u32 non_wakeup_gpios[] = {
1466 0xe203ffc0, 0x08700040
1469 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1470 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1471 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1473 /* Initialize interface clock ungated, module enabled */
1474 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1475 if (i < ARRAY_SIZE(non_wakeup_gpios))
1476 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1481 /* REVISIT eventually switch from OMAP-specific gpio structs
1482 * over to the generic ones
1484 bank->chip.direction_input = gpio_input;
1485 bank->chip.get = gpio_get;
1486 bank->chip.direction_output = gpio_output;
1487 bank->chip.set = gpio_set;
1488 if (bank_is_mpuio(bank)) {
1489 bank->chip.label = "mpuio";
1490 #ifdef CONFIG_ARCH_OMAP1
1491 bank->chip.dev = &omap_mpuio_device.dev;
1493 bank->chip.base = OMAP_MPUIO(0);
1495 bank->chip.label = "gpio";
1496 bank->chip.base = gpio;
1499 bank->chip.ngpio = gpio_count;
1501 gpiochip_add(&bank->chip);
1503 for (j = bank->virtual_irq_start;
1504 j < bank->virtual_irq_start + gpio_count; j++) {
1505 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1506 set_irq_chip_data(j, bank);
1507 if (bank_is_mpuio(bank))
1508 set_irq_chip(j, &mpuio_irq_chip);
1510 set_irq_chip(j, &gpio_irq_chip);
1511 set_irq_handler(j, handle_simple_irq);
1512 set_irq_flags(j, IRQF_VALID);
1514 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1515 set_irq_data(bank->irq, bank);
1518 /* Enable system clock for GPIO module.
1519 * The CAM_CLK_CTRL *is* really the right place. */
1520 if (cpu_is_omap16xx())
1521 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1523 /* Enable autoidle for the OCP interface */
1524 if (cpu_is_omap24xx())
1525 omap_writel(1 << 0, 0x48019010);
1526 if (cpu_is_omap34xx())
1527 omap_writel(1 << 0, 0x48306814);
1532 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1533 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1537 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1540 for (i = 0; i < gpio_bank_count; i++) {
1541 struct gpio_bank *bank = &gpio_bank[i];
1542 void __iomem *wake_status;
1543 void __iomem *wake_clear;
1544 void __iomem *wake_set;
1545 unsigned long flags;
1547 switch (bank->method) {
1548 #ifdef CONFIG_ARCH_OMAP16XX
1549 case METHOD_GPIO_1610:
1550 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1551 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1552 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1555 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1556 case METHOD_GPIO_24XX:
1557 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1558 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1559 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1566 spin_lock_irqsave(&bank->lock, flags);
1567 bank->saved_wakeup = __raw_readl(wake_status);
1568 __raw_writel(0xffffffff, wake_clear);
1569 __raw_writel(bank->suspend_wakeup, wake_set);
1570 spin_unlock_irqrestore(&bank->lock, flags);
1576 static int omap_gpio_resume(struct sys_device *dev)
1580 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1583 for (i = 0; i < gpio_bank_count; i++) {
1584 struct gpio_bank *bank = &gpio_bank[i];
1585 void __iomem *wake_clear;
1586 void __iomem *wake_set;
1587 unsigned long flags;
1589 switch (bank->method) {
1590 #ifdef CONFIG_ARCH_OMAP16XX
1591 case METHOD_GPIO_1610:
1592 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1593 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1596 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1597 case METHOD_GPIO_24XX:
1598 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1599 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1606 spin_lock_irqsave(&bank->lock, flags);
1607 __raw_writel(0xffffffff, wake_clear);
1608 __raw_writel(bank->saved_wakeup, wake_set);
1609 spin_unlock_irqrestore(&bank->lock, flags);
1615 static struct sysdev_class omap_gpio_sysclass = {
1617 .suspend = omap_gpio_suspend,
1618 .resume = omap_gpio_resume,
1621 static struct sys_device omap_gpio_device = {
1623 .cls = &omap_gpio_sysclass,
1628 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1630 static int workaround_enabled;
1632 void omap2_gpio_prepare_for_retention(void)
1636 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1637 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1638 for (i = 0; i < gpio_bank_count; i++) {
1639 struct gpio_bank *bank = &gpio_bank[i];
1642 if (!(bank->enabled_non_wakeup_gpios))
1644 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1645 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1646 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1647 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1649 bank->saved_fallingdetect = l1;
1650 bank->saved_risingdetect = l2;
1651 l1 &= ~bank->enabled_non_wakeup_gpios;
1652 l2 &= ~bank->enabled_non_wakeup_gpios;
1653 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1654 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1655 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1660 workaround_enabled = 0;
1663 workaround_enabled = 1;
1666 void omap2_gpio_resume_after_retention(void)
1670 if (!workaround_enabled)
1672 for (i = 0; i < gpio_bank_count; i++) {
1673 struct gpio_bank *bank = &gpio_bank[i];
1676 if (!(bank->enabled_non_wakeup_gpios))
1678 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1679 __raw_writel(bank->saved_fallingdetect,
1680 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1681 __raw_writel(bank->saved_risingdetect,
1682 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1684 /* Check if any of the non-wakeup interrupt GPIOs have changed
1685 * state. If so, generate an IRQ by software. This is
1686 * horribly racy, but it's the best we can do to work around
1687 * this silicon bug. */
1688 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1689 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1691 l ^= bank->saved_datain;
1692 l &= bank->non_wakeup_gpios;
1695 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1696 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1697 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1698 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1699 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1700 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1701 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1711 * This may get called early from board specific init
1712 * for boards that have interrupts routed via FPGA.
1714 int __init omap_gpio_init(void)
1717 return _omap_gpio_init();
1722 static int __init omap_gpio_sysinit(void)
1727 ret = _omap_gpio_init();
1731 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1732 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1734 ret = sysdev_class_register(&omap_gpio_sysclass);
1736 ret = sysdev_register(&omap_gpio_device);
1744 EXPORT_SYMBOL(omap_request_gpio);
1745 EXPORT_SYMBOL(omap_free_gpio);
1746 EXPORT_SYMBOL(omap_set_gpio_direction);
1747 EXPORT_SYMBOL(omap_set_gpio_dataout);
1748 EXPORT_SYMBOL(omap_get_gpio_datain);
1750 arch_initcall(omap_gpio_sysinit);
1753 #ifdef CONFIG_DEBUG_FS
1755 #include <linux/debugfs.h>
1756 #include <linux/seq_file.h>
1758 static int gpio_is_input(struct gpio_bank *bank, int mask)
1760 void __iomem *reg = bank->base;
1762 switch (bank->method) {
1764 reg += OMAP_MPUIO_IO_CNTL;
1766 case METHOD_GPIO_1510:
1767 reg += OMAP1510_GPIO_DIR_CONTROL;
1769 case METHOD_GPIO_1610:
1770 reg += OMAP1610_GPIO_DIRECTION;
1772 case METHOD_GPIO_730:
1773 reg += OMAP730_GPIO_DIR_CONTROL;
1775 case METHOD_GPIO_24XX:
1776 reg += OMAP24XX_GPIO_OE;
1779 return __raw_readl(reg) & mask;
1783 static int dbg_gpio_show(struct seq_file *s, void *unused)
1785 unsigned i, j, gpio;
1787 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1788 struct gpio_bank *bank = gpio_bank + i;
1789 unsigned bankwidth = 16;
1792 if (bank_is_mpuio(bank))
1793 gpio = OMAP_MPUIO(0);
1794 else if (cpu_class_is_omap2() || cpu_is_omap730())
1797 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1798 unsigned irq, value, is_in, irqstat;
1801 label = gpiochip_is_requested(&bank->chip, j);
1805 irq = bank->virtual_irq_start + j;
1806 value = omap_get_gpio_datain(gpio);
1807 is_in = gpio_is_input(bank, mask);
1809 if (bank_is_mpuio(bank))
1810 seq_printf(s, "MPUIO %2d ", j);
1812 seq_printf(s, "GPIO %3d ", gpio);
1813 seq_printf(s, "(%10s): %s %s",
1815 is_in ? "in " : "out",
1816 value ? "hi" : "lo");
1818 /* FIXME for at least omap2, show pullup/pulldown state */
1820 irqstat = irq_desc[irq].status;
1821 if (is_in && ((bank->suspend_wakeup & mask)
1822 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1823 char *trigger = NULL;
1825 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1826 case IRQ_TYPE_EDGE_FALLING:
1827 trigger = "falling";
1829 case IRQ_TYPE_EDGE_RISING:
1832 case IRQ_TYPE_EDGE_BOTH:
1833 trigger = "bothedge";
1835 case IRQ_TYPE_LEVEL_LOW:
1838 case IRQ_TYPE_LEVEL_HIGH:
1845 seq_printf(s, ", irq-%d %-8s%s",
1847 (bank->suspend_wakeup & mask)
1850 seq_printf(s, "\n");
1853 if (bank_is_mpuio(bank)) {
1854 seq_printf(s, "\n");
1861 static int dbg_gpio_open(struct inode *inode, struct file *file)
1863 return single_open(file, dbg_gpio_show, &inode->i_private);
1866 static const struct file_operations debug_fops = {
1867 .open = dbg_gpio_open,
1869 .llseek = seq_lseek,
1870 .release = single_release,
1873 static int __init omap_gpio_debuginit(void)
1875 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1876 NULL, NULL, &debug_fops);
1879 late_initcall(omap_gpio_debuginit);