2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
30 * OMAP1510 GPIO registers
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41 #define OMAP1510_IH_GPIO_BASE 64
44 * OMAP1610 specific GPIO registers
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 * OMAP730 specific GPIO registers
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
85 * omap24xx specific GPIO registers
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
137 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
190 #ifdef CONFIG_ARCH_OMAP24XX
192 static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
199 static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
221 static struct gpio_bank *gpio_bank;
222 static int gpio_bank_count;
224 static inline struct gpio_bank *get_gpio_bank(int gpio)
226 #ifdef CONFIG_ARCH_OMAP15XX
227 if (cpu_is_omap15xx()) {
228 if (OMAP_GPIO_IS_MPUIO(gpio))
229 return &gpio_bank[0];
230 return &gpio_bank[1];
233 #if defined(CONFIG_ARCH_OMAP16XX)
234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
240 #ifdef CONFIG_ARCH_OMAP730
241 if (cpu_is_omap730()) {
242 if (OMAP_GPIO_IS_MPUIO(gpio))
243 return &gpio_bank[0];
244 return &gpio_bank[1 + (gpio >> 5)];
247 #ifdef CONFIG_ARCH_OMAP24XX
248 if (cpu_is_omap24xx())
249 return &gpio_bank[gpio >> 5];
251 #ifdef CONFIG_ARCH_OMAP34XX
252 if (cpu_is_omap34xx())
253 return &gpio_bank[gpio >> 5];
257 static inline int get_gpio_index(int gpio)
259 #ifdef CONFIG_ARCH_OMAP730
260 if (cpu_is_omap730())
263 #ifdef CONFIG_ARCH_OMAP24XX
264 if (cpu_is_omap24xx())
267 #ifdef CONFIG_ARCH_OMAP34XX
268 if (cpu_is_omap34xx())
274 static inline int gpio_valid(int gpio)
278 #ifndef CONFIG_ARCH_OMAP24XX
279 if (OMAP_GPIO_IS_MPUIO(gpio)) {
280 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
285 #ifdef CONFIG_ARCH_OMAP15XX
286 if (cpu_is_omap15xx() && gpio < 16)
289 #if defined(CONFIG_ARCH_OMAP16XX)
290 if ((cpu_is_omap16xx()) && gpio < 64)
293 #ifdef CONFIG_ARCH_OMAP730
294 if (cpu_is_omap730() && gpio < 192)
297 #ifdef CONFIG_ARCH_OMAP24XX
298 if (cpu_is_omap24xx() && gpio < 128)
301 #ifdef CONFIG_ARCH_OMAP34XX
302 if (cpu_is_omap34xx() && gpio < 160)
308 static int check_gpio(int gpio)
310 if (unlikely(gpio_valid(gpio)) < 0) {
311 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
318 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
320 void __iomem *reg = bank->base;
323 switch (bank->method) {
324 #ifdef CONFIG_ARCH_OMAP1
326 reg += OMAP_MPUIO_IO_CNTL;
329 #ifdef CONFIG_ARCH_OMAP15XX
330 case METHOD_GPIO_1510:
331 reg += OMAP1510_GPIO_DIR_CONTROL;
334 #ifdef CONFIG_ARCH_OMAP16XX
335 case METHOD_GPIO_1610:
336 reg += OMAP1610_GPIO_DIRECTION;
339 #ifdef CONFIG_ARCH_OMAP730
340 case METHOD_GPIO_730:
341 reg += OMAP730_GPIO_DIR_CONTROL;
344 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
345 case METHOD_GPIO_24XX:
346 reg += OMAP24XX_GPIO_OE;
353 l = __raw_readl(reg);
358 __raw_writel(l, reg);
361 void omap_set_gpio_direction(int gpio, int is_input)
363 struct gpio_bank *bank;
365 if (check_gpio(gpio) < 0)
367 bank = get_gpio_bank(gpio);
368 spin_lock(&bank->lock);
369 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
370 spin_unlock(&bank->lock);
373 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
375 void __iomem *reg = bank->base;
378 switch (bank->method) {
379 #ifdef CONFIG_ARCH_OMAP1
381 reg += OMAP_MPUIO_OUTPUT;
382 l = __raw_readl(reg);
389 #ifdef CONFIG_ARCH_OMAP15XX
390 case METHOD_GPIO_1510:
391 reg += OMAP1510_GPIO_DATA_OUTPUT;
392 l = __raw_readl(reg);
399 #ifdef CONFIG_ARCH_OMAP16XX
400 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_SET_DATAOUT;
404 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
408 #ifdef CONFIG_ARCH_OMAP730
409 case METHOD_GPIO_730:
410 reg += OMAP730_GPIO_DATA_OUTPUT;
411 l = __raw_readl(reg);
418 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
419 case METHOD_GPIO_24XX:
421 reg += OMAP24XX_GPIO_SETDATAOUT;
423 reg += OMAP24XX_GPIO_CLEARDATAOUT;
431 __raw_writel(l, reg);
434 void omap_set_gpio_dataout(int gpio, int enable)
436 struct gpio_bank *bank;
438 if (check_gpio(gpio) < 0)
440 bank = get_gpio_bank(gpio);
441 spin_lock(&bank->lock);
442 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
443 spin_unlock(&bank->lock);
446 int omap_get_gpio_datain(int gpio)
448 struct gpio_bank *bank;
451 if (check_gpio(gpio) < 0)
453 bank = get_gpio_bank(gpio);
455 switch (bank->method) {
456 #ifdef CONFIG_ARCH_OMAP1
458 reg += OMAP_MPUIO_INPUT_LATCH;
461 #ifdef CONFIG_ARCH_OMAP15XX
462 case METHOD_GPIO_1510:
463 reg += OMAP1510_GPIO_DATA_INPUT;
466 #ifdef CONFIG_ARCH_OMAP16XX
467 case METHOD_GPIO_1610:
468 reg += OMAP1610_GPIO_DATAIN;
471 #ifdef CONFIG_ARCH_OMAP730
472 case METHOD_GPIO_730:
473 reg += OMAP730_GPIO_DATA_INPUT;
476 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
477 case METHOD_GPIO_24XX:
478 reg += OMAP24XX_GPIO_DATAIN;
484 return (__raw_readl(reg)
485 & (1 << get_gpio_index(gpio))) != 0;
488 #define MOD_REG_BIT(reg, bit_mask, set) \
490 int l = __raw_readl(base + reg); \
491 if (set) l |= bit_mask; \
492 else l &= ~bit_mask; \
493 __raw_writel(l, base + reg); \
496 void omap_set_gpio_debounce(int gpio, int enable)
498 struct gpio_bank *bank;
500 u32 val, l = 1 << get_gpio_index(gpio);
502 if (cpu_class_is_omap1())
505 bank = get_gpio_bank(gpio);
508 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
509 val = __raw_readl(reg);
516 __raw_writel(val, reg);
518 EXPORT_SYMBOL(omap_set_gpio_debounce);
520 void omap_set_gpio_debounce_time(int gpio, int enc_time)
522 struct gpio_bank *bank;
525 if (cpu_class_is_omap1())
528 bank = get_gpio_bank(gpio);
532 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
533 __raw_writel(enc_time, reg);
535 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
537 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
538 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
541 void __iomem *base = bank->base;
542 u32 gpio_bit = 1 << gpio;
544 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
545 trigger & __IRQT_LOWLVL);
546 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
547 trigger & __IRQT_HIGHLVL);
548 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
549 trigger & __IRQT_RISEDGE);
550 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
551 trigger & __IRQT_FALEDGE);
553 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
555 __raw_writel(1 << gpio, bank->base
556 + OMAP24XX_GPIO_SETWKUENA);
558 __raw_writel(1 << gpio, bank->base
559 + OMAP24XX_GPIO_CLEARWKUENA);
562 bank->enabled_non_wakeup_gpios |= gpio_bit;
564 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
568 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
569 *level triggering requested.
574 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
576 void __iomem *reg = bank->base;
579 switch (bank->method) {
580 #ifdef CONFIG_ARCH_OMAP1
582 reg += OMAP_MPUIO_GPIO_INT_EDGE;
583 l = __raw_readl(reg);
584 if (trigger & __IRQT_RISEDGE)
586 else if (trigger & __IRQT_FALEDGE)
592 #ifdef CONFIG_ARCH_OMAP15XX
593 case METHOD_GPIO_1510:
594 reg += OMAP1510_GPIO_INT_CONTROL;
595 l = __raw_readl(reg);
596 if (trigger & __IRQT_RISEDGE)
598 else if (trigger & __IRQT_FALEDGE)
604 #ifdef CONFIG_ARCH_OMAP16XX
605 case METHOD_GPIO_1610:
607 reg += OMAP1610_GPIO_EDGE_CTRL2;
609 reg += OMAP1610_GPIO_EDGE_CTRL1;
611 l = __raw_readl(reg);
612 l &= ~(3 << (gpio << 1));
613 if (trigger & __IRQT_RISEDGE)
614 l |= 2 << (gpio << 1);
615 if (trigger & __IRQT_FALEDGE)
616 l |= 1 << (gpio << 1);
618 /* Enable wake-up during idle for dynamic tick */
619 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
621 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
624 #ifdef CONFIG_ARCH_OMAP730
625 case METHOD_GPIO_730:
626 reg += OMAP730_GPIO_INT_CONTROL;
627 l = __raw_readl(reg);
628 if (trigger & __IRQT_RISEDGE)
630 else if (trigger & __IRQT_FALEDGE)
636 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
637 case METHOD_GPIO_24XX:
638 set_24xx_gpio_triggering(bank, gpio, trigger);
644 __raw_writel(l, reg);
650 static int gpio_irq_type(unsigned irq, unsigned type)
652 struct gpio_bank *bank;
656 if (!(cpu_class_is_omap2()) && irq > IH_MPUIO_BASE)
657 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
659 gpio = irq - IH_GPIO_BASE;
661 if (check_gpio(gpio) < 0)
664 if (type & ~IRQ_TYPE_SENSE_MASK)
667 /* OMAP1 allows only only edge triggering */
668 if (!(cpu_class_is_omap2())
669 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
672 bank = get_irq_chip_data(irq);
673 spin_lock(&bank->lock);
674 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
676 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
677 irq_desc[irq].status |= type;
679 spin_unlock(&bank->lock);
683 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
685 void __iomem *reg = bank->base;
687 switch (bank->method) {
688 #ifdef CONFIG_ARCH_OMAP1
690 /* MPUIO irqstatus is reset by reading the status register,
691 * so do nothing here */
694 #ifdef CONFIG_ARCH_OMAP15XX
695 case METHOD_GPIO_1510:
696 reg += OMAP1510_GPIO_INT_STATUS;
699 #ifdef CONFIG_ARCH_OMAP16XX
700 case METHOD_GPIO_1610:
701 reg += OMAP1610_GPIO_IRQSTATUS1;
704 #ifdef CONFIG_ARCH_OMAP730
705 case METHOD_GPIO_730:
706 reg += OMAP730_GPIO_INT_STATUS;
709 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
710 case METHOD_GPIO_24XX:
711 reg += OMAP24XX_GPIO_IRQSTATUS1;
718 __raw_writel(gpio_mask, reg);
720 /* Workaround for clearing DSP GPIO interrupts to allow retention */
721 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
722 if (cpu_is_omap24xx() || cpu_is_omap34xx())
723 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
727 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
729 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
732 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
734 void __iomem *reg = bank->base;
739 switch (bank->method) {
740 #ifdef CONFIG_ARCH_OMAP1
742 reg += OMAP_MPUIO_GPIO_MASKIT;
747 #ifdef CONFIG_ARCH_OMAP15XX
748 case METHOD_GPIO_1510:
749 reg += OMAP1510_GPIO_INT_MASK;
754 #ifdef CONFIG_ARCH_OMAP16XX
755 case METHOD_GPIO_1610:
756 reg += OMAP1610_GPIO_IRQENABLE1;
760 #ifdef CONFIG_ARCH_OMAP730
761 case METHOD_GPIO_730:
762 reg += OMAP730_GPIO_INT_MASK;
767 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
768 case METHOD_GPIO_24XX:
769 reg += OMAP24XX_GPIO_IRQENABLE1;
778 l = __raw_readl(reg);
785 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
787 void __iomem *reg = bank->base;
790 switch (bank->method) {
791 #ifdef CONFIG_ARCH_OMAP1
793 reg += OMAP_MPUIO_GPIO_MASKIT;
794 l = __raw_readl(reg);
801 #ifdef CONFIG_ARCH_OMAP15XX
802 case METHOD_GPIO_1510:
803 reg += OMAP1510_GPIO_INT_MASK;
804 l = __raw_readl(reg);
811 #ifdef CONFIG_ARCH_OMAP16XX
812 case METHOD_GPIO_1610:
814 reg += OMAP1610_GPIO_SET_IRQENABLE1;
816 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
820 #ifdef CONFIG_ARCH_OMAP730
821 case METHOD_GPIO_730:
822 reg += OMAP730_GPIO_INT_MASK;
823 l = __raw_readl(reg);
830 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
831 case METHOD_GPIO_24XX:
833 reg += OMAP24XX_GPIO_SETIRQENABLE1;
835 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
843 __raw_writel(l, reg);
846 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
848 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
852 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
853 * 1510 does not seem to have a wake-up register. If JTAG is connected
854 * to the target, system will wake up always on GPIO events. While
855 * system is running all registered GPIO interrupts need to have wake-up
856 * enabled. When system is suspended, only selected GPIO interrupts need
857 * to have wake-up enabled.
859 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
861 switch (bank->method) {
862 #ifdef CONFIG_ARCH_OMAP16XX
864 case METHOD_GPIO_1610:
865 spin_lock(&bank->lock);
867 bank->suspend_wakeup |= (1 << gpio);
868 enable_irq_wake(bank->irq);
870 disable_irq_wake(bank->irq);
871 bank->suspend_wakeup &= ~(1 << gpio);
873 spin_unlock(&bank->lock);
876 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
877 case METHOD_GPIO_24XX:
878 if (bank->non_wakeup_gpios & (1 << gpio)) {
879 printk(KERN_ERR "Unable to modify wakeup on "
880 "non-wakeup GPIO%d\n",
881 (bank - gpio_bank) * 32 + gpio);
884 spin_lock(&bank->lock);
886 bank->suspend_wakeup |= (1 << gpio);
887 enable_irq_wake(bank->irq);
889 disable_irq_wake(bank->irq);
890 bank->suspend_wakeup &= ~(1 << gpio);
892 spin_unlock(&bank->lock);
896 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
902 static void _reset_gpio(struct gpio_bank *bank, int gpio)
904 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
905 _set_gpio_irqenable(bank, gpio, 0);
906 _clear_gpio_irqstatus(bank, gpio);
907 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
910 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
911 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
913 unsigned int gpio = irq - IH_GPIO_BASE;
914 struct gpio_bank *bank;
917 if (check_gpio(gpio) < 0)
919 bank = get_irq_chip_data(irq);
920 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
925 int omap_request_gpio(int gpio)
927 struct gpio_bank *bank;
929 if (check_gpio(gpio) < 0)
932 bank = get_gpio_bank(gpio);
933 spin_lock(&bank->lock);
934 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
935 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
937 spin_unlock(&bank->lock);
940 bank->reserved_map |= (1 << get_gpio_index(gpio));
942 /* Set trigger to none. You need to enable the desired trigger with
943 * request_irq() or set_irq_type().
945 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
947 #ifdef CONFIG_ARCH_OMAP15XX
948 if (bank->method == METHOD_GPIO_1510) {
951 /* Claim the pin for MPU */
952 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
953 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
956 spin_unlock(&bank->lock);
961 void omap_free_gpio(int gpio)
963 struct gpio_bank *bank;
965 if (check_gpio(gpio) < 0)
967 bank = get_gpio_bank(gpio);
968 spin_lock(&bank->lock);
969 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
970 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
972 spin_unlock(&bank->lock);
975 #ifdef CONFIG_ARCH_OMAP16XX
976 if (bank->method == METHOD_GPIO_1610) {
977 /* Disable wake-up during idle for dynamic tick */
978 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
979 __raw_writel(1 << get_gpio_index(gpio), reg);
982 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
983 if (bank->method == METHOD_GPIO_24XX) {
984 /* Disable wake-up during idle for dynamic tick */
985 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
986 __raw_writel(1 << get_gpio_index(gpio), reg);
989 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
990 _reset_gpio(bank, gpio);
991 spin_unlock(&bank->lock);
995 * We need to unmask the GPIO bank interrupt as soon as possible to
996 * avoid missing GPIO interrupts for other lines in the bank.
997 * Then we need to mask-read-clear-unmask the triggered GPIO lines
998 * in the bank to avoid missing nested interrupts for a GPIO line.
999 * If we wait to unmask individual GPIO lines in the bank after the
1000 * line's interrupt handler has been run, we may miss some nested
1003 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1005 void __iomem *isr_reg = NULL;
1007 unsigned int gpio_irq;
1008 struct gpio_bank *bank;
1012 desc->chip->ack(irq);
1014 bank = get_irq_data(irq);
1015 #ifdef CONFIG_ARCH_OMAP1
1016 if (bank->method == METHOD_MPUIO)
1017 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1019 #ifdef CONFIG_ARCH_OMAP15XX
1020 if (bank->method == METHOD_GPIO_1510)
1021 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1023 #if defined(CONFIG_ARCH_OMAP16XX)
1024 if (bank->method == METHOD_GPIO_1610)
1025 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1027 #ifdef CONFIG_ARCH_OMAP730
1028 if (bank->method == METHOD_GPIO_730)
1029 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1031 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1032 if (bank->method == METHOD_GPIO_24XX)
1033 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1036 u32 isr_saved, level_mask = 0;
1039 enabled = _get_gpio_irqbank_mask(bank);
1040 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1042 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1045 if (cpu_class_is_omap2()) {
1047 __raw_readl(bank->base +
1048 OMAP24XX_GPIO_LEVELDETECT0) |
1049 __raw_readl(bank->base +
1050 OMAP24XX_GPIO_LEVELDETECT1);
1051 level_mask &= enabled;
1054 /* clear edge sensitive interrupts before handler(s) are
1055 called so that we don't miss any interrupt occurred while
1057 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1058 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1059 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1061 /* if there is only edge sensitive GPIO pin interrupts
1062 configured, we could unmask GPIO bank interrupt immediately */
1063 if (!level_mask && !unmasked) {
1065 desc->chip->unmask(irq);
1073 gpio_irq = bank->virtual_irq_start;
1074 for (; isr != 0; isr >>= 1, gpio_irq++) {
1079 d = irq_desc + gpio_irq;
1080 /* Don't run the handler if it's already running
1081 * or was disabled lazely.
1083 if (unlikely((d->depth ||
1084 (d->status & IRQ_INPROGRESS)))) {
1086 (gpio_irq - bank->virtual_irq_start);
1087 /* The unmasking will be done by
1088 * enable_irq in case it is disabled or
1089 * after returning from the handler if
1090 * it's already running.
1092 _enable_gpio_irqbank(bank, irq_mask, 0);
1094 /* Level triggered interrupts
1095 * won't ever be reentered
1097 BUG_ON(level_mask & irq_mask);
1098 d->status |= IRQ_PENDING;
1103 desc_handle_irq(gpio_irq, d);
1105 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1107 (gpio_irq - bank->virtual_irq_start);
1108 d->status &= ~IRQ_PENDING;
1109 _enable_gpio_irqbank(bank, irq_mask, 1);
1110 retrigger |= irq_mask;
1114 if (cpu_class_is_omap2()) {
1115 /* clear level sensitive interrupts after handler(s) */
1116 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1117 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1118 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1122 /* if bank has any level sensitive GPIO pin interrupt
1123 configured, we must unmask the bank interrupt only after
1124 handler(s) are executed in order to avoid spurious bank
1127 desc->chip->unmask(irq);
1131 static void gpio_irq_shutdown(unsigned int irq)
1133 unsigned int gpio = irq - IH_GPIO_BASE;
1134 struct gpio_bank *bank = get_irq_chip_data(irq);
1136 _reset_gpio(bank, gpio);
1139 static void gpio_ack_irq(unsigned int irq)
1141 unsigned int gpio = irq - IH_GPIO_BASE;
1142 struct gpio_bank *bank = get_irq_chip_data(irq);
1144 _clear_gpio_irqstatus(bank, gpio);
1147 static void gpio_mask_irq(unsigned int irq)
1149 unsigned int gpio = irq - IH_GPIO_BASE;
1150 struct gpio_bank *bank = get_irq_chip_data(irq);
1152 _set_gpio_irqenable(bank, gpio, 0);
1155 static void gpio_unmask_irq(unsigned int irq)
1157 unsigned int gpio = irq - IH_GPIO_BASE;
1158 unsigned int gpio_idx = get_gpio_index(gpio);
1159 struct gpio_bank *bank = get_irq_chip_data(irq);
1161 _set_gpio_irqenable(bank, gpio_idx, 1);
1164 static struct irq_chip gpio_irq_chip = {
1166 .shutdown = gpio_irq_shutdown,
1167 .ack = gpio_ack_irq,
1168 .mask = gpio_mask_irq,
1169 .unmask = gpio_unmask_irq,
1170 .set_type = gpio_irq_type,
1171 .set_wake = gpio_wake_enable,
1174 /*---------------------------------------------------------------------*/
1176 #ifdef CONFIG_ARCH_OMAP1
1178 /* MPUIO uses the always-on 32k clock */
1180 static void mpuio_ack_irq(unsigned int irq)
1182 /* The ISR is reset automatically, so do nothing here. */
1185 static void mpuio_mask_irq(unsigned int irq)
1187 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1188 struct gpio_bank *bank = get_irq_chip_data(irq);
1190 _set_gpio_irqenable(bank, gpio, 0);
1193 static void mpuio_unmask_irq(unsigned int irq)
1195 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1196 struct gpio_bank *bank = get_irq_chip_data(irq);
1198 _set_gpio_irqenable(bank, gpio, 1);
1201 static struct irq_chip mpuio_irq_chip = {
1203 .ack = mpuio_ack_irq,
1204 .mask = mpuio_mask_irq,
1205 .unmask = mpuio_unmask_irq,
1206 .set_type = gpio_irq_type,
1207 #ifdef CONFIG_ARCH_OMAP16XX
1208 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1209 .set_wake = gpio_wake_enable,
1214 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1217 #ifdef CONFIG_ARCH_OMAP16XX
1219 #include <linux/platform_device.h>
1221 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1223 struct gpio_bank *bank = platform_get_drvdata(pdev);
1224 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1226 spin_lock(&bank->lock);
1227 bank->saved_wakeup = __raw_readl(mask_reg);
1228 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1229 spin_unlock(&bank->lock);
1234 static int omap_mpuio_resume_early(struct platform_device *pdev)
1236 struct gpio_bank *bank = platform_get_drvdata(pdev);
1237 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1239 spin_lock(&bank->lock);
1240 __raw_writel(bank->saved_wakeup, mask_reg);
1241 spin_unlock(&bank->lock);
1246 /* use platform_driver for this, now that there's no longer any
1247 * point to sys_device (other than not disturbing old code).
1249 static struct platform_driver omap_mpuio_driver = {
1250 .suspend_late = omap_mpuio_suspend_late,
1251 .resume_early = omap_mpuio_resume_early,
1257 static struct platform_device omap_mpuio_device = {
1261 .driver = &omap_mpuio_driver.driver,
1263 /* could list the /proc/iomem resources */
1266 static inline void mpuio_init(void)
1268 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1270 if (platform_driver_register(&omap_mpuio_driver) == 0)
1271 (void) platform_device_register(&omap_mpuio_device);
1275 static inline void mpuio_init(void) {}
1280 extern struct irq_chip mpuio_irq_chip;
1282 #define bank_is_mpuio(bank) 0
1283 static inline void mpuio_init(void) {}
1287 /*---------------------------------------------------------------------*/
1289 static int initialized;
1290 #if !defined(CONFIG_ARCH_OMAP3)
1291 static struct clk * gpio_ick;
1294 #if defined(CONFIG_ARCH_OMAP2)
1295 static struct clk * gpio_fck;
1298 #if defined(CONFIG_ARCH_OMAP2430)
1299 static struct clk * gpio5_ick;
1300 static struct clk * gpio5_fck;
1303 #if defined(CONFIG_ARCH_OMAP3)
1304 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1305 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1308 static int __init _omap_gpio_init(void)
1311 struct gpio_bank *bank;
1312 #if defined(CONFIG_ARCH_OMAP3)
1318 #if defined(CONFIG_ARCH_OMAP1)
1319 if (cpu_is_omap15xx()) {
1320 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1321 if (IS_ERR(gpio_ick))
1322 printk("Could not get arm_gpio_ck\n");
1324 clk_enable(gpio_ick);
1327 #if defined(CONFIG_ARCH_OMAP2)
1328 if (cpu_class_is_omap2()) {
1329 gpio_ick = clk_get(NULL, "gpios_ick");
1330 if (IS_ERR(gpio_ick))
1331 printk("Could not get gpios_ick\n");
1333 clk_enable(gpio_ick);
1334 gpio_fck = clk_get(NULL, "gpios_fck");
1335 if (IS_ERR(gpio_fck))
1336 printk("Could not get gpios_fck\n");
1338 clk_enable(gpio_fck);
1341 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1343 #if defined(CONFIG_ARCH_OMAP2430)
1344 if (cpu_is_omap2430()) {
1345 gpio5_ick = clk_get(NULL, "gpio5_ick");
1346 if (IS_ERR(gpio5_ick))
1347 printk("Could not get gpio5_ick\n");
1349 clk_enable(gpio5_ick);
1350 gpio5_fck = clk_get(NULL, "gpio5_fck");
1351 if (IS_ERR(gpio5_fck))
1352 printk("Could not get gpio5_fck\n");
1354 clk_enable(gpio5_fck);
1360 #if defined(CONFIG_ARCH_OMAP3)
1361 if (cpu_is_omap34xx()) {
1362 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1363 sprintf(clk_name, "gpio%d_ick", i + 1);
1364 gpio_iclks[i] = clk_get(NULL, clk_name);
1365 if (IS_ERR(gpio_iclks[i]))
1366 printk(KERN_ERR "Could not get %s\n", clk_name);
1368 clk_enable(gpio_iclks[i]);
1369 sprintf(clk_name, "gpio%d_fck", i + 1);
1370 gpio_fclks[i] = clk_get(NULL, clk_name);
1371 if (IS_ERR(gpio_fclks[i]))
1372 printk(KERN_ERR "Could not get %s\n", clk_name);
1374 clk_enable(gpio_fclks[i]);
1380 #ifdef CONFIG_ARCH_OMAP15XX
1381 if (cpu_is_omap15xx()) {
1382 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1383 gpio_bank_count = 2;
1384 gpio_bank = gpio_bank_1510;
1387 #if defined(CONFIG_ARCH_OMAP16XX)
1388 if (cpu_is_omap16xx()) {
1391 gpio_bank_count = 5;
1392 gpio_bank = gpio_bank_1610;
1393 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1394 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1395 (rev >> 4) & 0x0f, rev & 0x0f);
1398 #ifdef CONFIG_ARCH_OMAP730
1399 if (cpu_is_omap730()) {
1400 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1401 gpio_bank_count = 7;
1402 gpio_bank = gpio_bank_730;
1406 #ifdef CONFIG_ARCH_OMAP24XX
1407 if (cpu_is_omap242x()) {
1410 gpio_bank_count = 4;
1411 gpio_bank = gpio_bank_242x;
1412 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1413 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1414 (rev >> 4) & 0x0f, rev & 0x0f);
1416 if (cpu_is_omap243x()) {
1419 gpio_bank_count = 5;
1420 gpio_bank = gpio_bank_243x;
1421 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1422 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1423 (rev >> 4) & 0x0f, rev & 0x0f);
1426 #ifdef CONFIG_ARCH_OMAP34XX
1427 if (cpu_is_omap34xx()) {
1430 gpio_bank_count = OMAP34XX_NR_GPIOS;
1431 gpio_bank = gpio_bank_34xx;
1432 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1433 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1434 (rev >> 4) & 0x0f, rev & 0x0f);
1437 for (i = 0; i < gpio_bank_count; i++) {
1438 int j, gpio_count = 16;
1440 bank = &gpio_bank[i];
1441 bank->reserved_map = 0;
1442 bank->base = IO_ADDRESS(bank->base);
1443 spin_lock_init(&bank->lock);
1444 if (bank_is_mpuio(bank))
1445 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1446 #ifdef CONFIG_ARCH_OMAP15XX
1447 if (bank->method == METHOD_GPIO_1510) {
1448 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1449 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1452 #if defined(CONFIG_ARCH_OMAP16XX)
1453 if (bank->method == METHOD_GPIO_1610) {
1454 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1455 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1456 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1459 #ifdef CONFIG_ARCH_OMAP730
1460 if (bank->method == METHOD_GPIO_730) {
1461 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1462 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1464 gpio_count = 32; /* 730 has 32-bit GPIOs */
1467 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1468 if (bank->method == METHOD_GPIO_24XX) {
1469 static const u32 non_wakeup_gpios[] = {
1470 0xe203ffc0, 0x08700040
1473 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1474 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1475 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1477 /* Initialize interface clock ungated, module enabled */
1478 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1479 if (i < ARRAY_SIZE(non_wakeup_gpios))
1480 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1484 for (j = bank->virtual_irq_start;
1485 j < bank->virtual_irq_start + gpio_count; j++) {
1486 set_irq_chip_data(j, bank);
1487 if (bank_is_mpuio(bank))
1488 set_irq_chip(j, &mpuio_irq_chip);
1490 set_irq_chip(j, &gpio_irq_chip);
1491 set_irq_handler(j, handle_simple_irq);
1492 set_irq_flags(j, IRQF_VALID);
1494 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1495 set_irq_data(bank->irq, bank);
1498 /* Enable system clock for GPIO module.
1499 * The CAM_CLK_CTRL *is* really the right place. */
1500 if (cpu_is_omap16xx())
1501 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1503 #if defined(CONFIG_ARCH_OMAP24XX)
1504 /* Enable autoidle for the OCP interface */
1505 if (cpu_is_omap24xx())
1506 omap_writel(1 << 0, 0x48019010);
1507 #elif defined(CONFIG_ARCH_OMAP34XX)
1508 if (cpu_is_omap34xx())
1509 omap_writel(1 << 0, 0x48306814);
1514 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1515 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1519 if ((!cpu_class_is_omap2()) && (!cpu_is_omap16xx()))
1522 for (i = 0; i < gpio_bank_count; i++) {
1523 struct gpio_bank *bank = &gpio_bank[i];
1524 void __iomem *wake_status;
1525 void __iomem *wake_clear;
1526 void __iomem *wake_set;
1528 switch (bank->method) {
1529 #ifdef CONFIG_ARCH_OMAP16XX
1530 case METHOD_GPIO_1610:
1531 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1532 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1533 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1536 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1537 case METHOD_GPIO_24XX:
1538 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1539 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1540 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1547 spin_lock(&bank->lock);
1548 bank->saved_wakeup = __raw_readl(wake_status);
1549 __raw_writel(0xffffffff, wake_clear);
1550 __raw_writel(bank->suspend_wakeup, wake_set);
1551 spin_unlock(&bank->lock);
1557 static int omap_gpio_resume(struct sys_device *dev)
1561 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1564 for (i = 0; i < gpio_bank_count; i++) {
1565 struct gpio_bank *bank = &gpio_bank[i];
1566 void __iomem *wake_clear;
1567 void __iomem *wake_set;
1569 switch (bank->method) {
1570 #ifdef CONFIG_ARCH_OMAP16XX
1571 case METHOD_GPIO_1610:
1572 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1573 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1576 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1577 case METHOD_GPIO_24XX:
1578 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1579 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1586 spin_lock(&bank->lock);
1587 __raw_writel(0xffffffff, wake_clear);
1588 __raw_writel(bank->saved_wakeup, wake_set);
1589 spin_unlock(&bank->lock);
1595 static struct sysdev_class omap_gpio_sysclass = {
1596 set_kset_name("gpio"),
1597 .suspend = omap_gpio_suspend,
1598 .resume = omap_gpio_resume,
1601 static struct sys_device omap_gpio_device = {
1603 .cls = &omap_gpio_sysclass,
1608 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1610 static int workaround_enabled;
1612 void omap2_gpio_prepare_for_retention(void)
1616 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1617 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1618 for (i = 0; i < gpio_bank_count; i++) {
1619 struct gpio_bank *bank = &gpio_bank[i];
1622 if (!(bank->enabled_non_wakeup_gpios))
1624 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1625 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1626 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1627 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1629 bank->saved_fallingdetect = l1;
1630 bank->saved_risingdetect = l2;
1631 l1 &= ~bank->enabled_non_wakeup_gpios;
1632 l2 &= ~bank->enabled_non_wakeup_gpios;
1633 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1634 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1635 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1640 workaround_enabled = 0;
1643 workaround_enabled = 1;
1646 void omap2_gpio_resume_after_retention(void)
1650 if (!workaround_enabled)
1652 for (i = 0; i < gpio_bank_count; i++) {
1653 struct gpio_bank *bank = &gpio_bank[i];
1656 if (!(bank->enabled_non_wakeup_gpios))
1658 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1659 __raw_writel(bank->saved_fallingdetect,
1660 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1661 __raw_writel(bank->saved_risingdetect,
1662 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1664 /* Check if any of the non-wakeup interrupt GPIOs have changed
1665 * state. If so, generate an IRQ by software. This is
1666 * horribly racy, but it's the best we can do to work around
1667 * this silicon bug. */
1668 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1669 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1671 l ^= bank->saved_datain;
1672 l &= bank->non_wakeup_gpios;
1675 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1676 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1677 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1678 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1679 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1680 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1681 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1691 * This may get called early from board specific init
1692 * for boards that have interrupts routed via FPGA.
1694 int __init omap_gpio_init(void)
1697 return _omap_gpio_init();
1702 static int __init omap_gpio_sysinit(void)
1707 ret = _omap_gpio_init();
1711 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1712 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1714 ret = sysdev_class_register(&omap_gpio_sysclass);
1716 ret = sysdev_register(&omap_gpio_device);
1724 EXPORT_SYMBOL(omap_request_gpio);
1725 EXPORT_SYMBOL(omap_free_gpio);
1726 EXPORT_SYMBOL(omap_set_gpio_direction);
1727 EXPORT_SYMBOL(omap_set_gpio_dataout);
1728 EXPORT_SYMBOL(omap_get_gpio_datain);
1730 arch_initcall(omap_gpio_sysinit);
1733 #ifdef CONFIG_DEBUG_FS
1735 #include <linux/debugfs.h>
1736 #include <linux/seq_file.h>
1738 static int gpio_is_input(struct gpio_bank *bank, int mask)
1740 void __iomem *reg = bank->base;
1742 switch (bank->method) {
1744 reg += OMAP_MPUIO_IO_CNTL;
1746 case METHOD_GPIO_1510:
1747 reg += OMAP1510_GPIO_DIR_CONTROL;
1749 case METHOD_GPIO_1610:
1750 reg += OMAP1610_GPIO_DIRECTION;
1752 case METHOD_GPIO_730:
1753 reg += OMAP730_GPIO_DIR_CONTROL;
1755 case METHOD_GPIO_24XX:
1756 reg += OMAP24XX_GPIO_OE;
1759 return __raw_readl(reg) & mask;
1763 static int dbg_gpio_show(struct seq_file *s, void *unused)
1765 unsigned i, j, gpio;
1767 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1768 struct gpio_bank *bank = gpio_bank + i;
1769 unsigned bankwidth = 16;
1772 if (bank_is_mpuio(bank))
1773 gpio = OMAP_MPUIO(0);
1774 else if (cpu_class_is_omap2() || cpu_is_omap730())
1777 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1778 unsigned irq, value, is_in, irqstat;
1780 if (!(bank->reserved_map & mask))
1783 irq = bank->virtual_irq_start + j;
1784 value = omap_get_gpio_datain(gpio);
1785 is_in = gpio_is_input(bank, mask);
1787 if (bank_is_mpuio(bank))
1788 seq_printf(s, "MPUIO %2d: ", j);
1790 seq_printf(s, "GPIO %3d: ", gpio);
1791 seq_printf(s, "%s %s",
1792 is_in ? "in " : "out",
1793 value ? "hi" : "lo");
1795 irqstat = irq_desc[irq].status;
1796 if (is_in && ((bank->suspend_wakeup & mask)
1797 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1798 char *trigger = NULL;
1800 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1801 case IRQ_TYPE_EDGE_FALLING:
1802 trigger = "falling";
1804 case IRQ_TYPE_EDGE_RISING:
1807 case IRQ_TYPE_EDGE_BOTH:
1808 trigger = "bothedge";
1810 case IRQ_TYPE_LEVEL_LOW:
1813 case IRQ_TYPE_LEVEL_HIGH:
1817 trigger = "(unspecified)";
1820 seq_printf(s, ", irq-%d %s%s",
1822 (bank->suspend_wakeup & mask)
1825 seq_printf(s, "\n");
1828 if (bank_is_mpuio(bank)) {
1829 seq_printf(s, "\n");
1836 static int dbg_gpio_open(struct inode *inode, struct file *file)
1838 return single_open(file, dbg_gpio_show, &inode->i_private);
1841 static const struct file_operations debug_fops = {
1842 .open = dbg_gpio_open,
1844 .llseek = seq_lseek,
1845 .release = single_release,
1848 static int __init omap_gpio_debuginit(void)
1850 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1851 NULL, NULL, &debug_fops);
1854 late_initcall(omap_gpio_debuginit);