2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ptrace.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/delay.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * omap24xx specific GPIO registers
89 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
94 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
95 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
96 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
97 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
98 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
100 #define OMAP24XX_GPIO_REVISION 0x0000
101 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
102 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
103 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
104 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
105 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
106 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
107 #define OMAP24XX_GPIO_CTRL 0x0030
108 #define OMAP24XX_GPIO_OE 0x0034
109 #define OMAP24XX_GPIO_DATAIN 0x0038
110 #define OMAP24XX_GPIO_DATAOUT 0x003c
111 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
112 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
113 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
114 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
125 u16 virtual_irq_start;
128 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
132 #ifdef CONFIG_ARCH_OMAP24XX
133 u32 non_wakeup_gpios;
134 u32 enabled_non_wakeup_gpios;
137 u32 saved_fallingdetect;
138 u32 saved_risingdetect;
143 #define METHOD_MPUIO 0
144 #define METHOD_GPIO_1510 1
145 #define METHOD_GPIO_1610 2
146 #define METHOD_GPIO_730 3
147 #define METHOD_GPIO_24XX 4
149 #ifdef CONFIG_ARCH_OMAP16XX
150 static struct gpio_bank gpio_bank_1610[5] = {
151 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
152 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
153 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
154 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
155 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
159 #ifdef CONFIG_ARCH_OMAP15XX
160 static struct gpio_bank gpio_bank_1510[2] = {
161 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
162 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
166 #ifdef CONFIG_ARCH_OMAP730
167 static struct gpio_bank gpio_bank_730[7] = {
168 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
169 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
170 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
171 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
172 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
173 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
174 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
178 #ifdef CONFIG_ARCH_OMAP24XX
180 static struct gpio_bank gpio_bank_242x[4] = {
181 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
182 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
183 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
184 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
187 static struct gpio_bank gpio_bank_243x[5] = {
188 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
189 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
190 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
191 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
192 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
197 static struct gpio_bank *gpio_bank;
198 static int gpio_bank_count;
200 static inline struct gpio_bank *get_gpio_bank(int gpio)
202 #ifdef CONFIG_ARCH_OMAP15XX
203 if (cpu_is_omap15xx()) {
204 if (OMAP_GPIO_IS_MPUIO(gpio))
205 return &gpio_bank[0];
206 return &gpio_bank[1];
209 #if defined(CONFIG_ARCH_OMAP16XX)
210 if (cpu_is_omap16xx()) {
211 if (OMAP_GPIO_IS_MPUIO(gpio))
212 return &gpio_bank[0];
213 return &gpio_bank[1 + (gpio >> 4)];
216 #ifdef CONFIG_ARCH_OMAP730
217 if (cpu_is_omap730()) {
218 if (OMAP_GPIO_IS_MPUIO(gpio))
219 return &gpio_bank[0];
220 return &gpio_bank[1 + (gpio >> 5)];
223 #ifdef CONFIG_ARCH_OMAP24XX
224 if (cpu_is_omap24xx())
225 return &gpio_bank[gpio >> 5];
229 static inline int get_gpio_index(int gpio)
231 #ifdef CONFIG_ARCH_OMAP730
232 if (cpu_is_omap730())
235 #ifdef CONFIG_ARCH_OMAP24XX
236 if (cpu_is_omap24xx())
242 static inline int gpio_valid(int gpio)
246 #ifndef CONFIG_ARCH_OMAP24XX
247 if (OMAP_GPIO_IS_MPUIO(gpio)) {
248 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
253 #ifdef CONFIG_ARCH_OMAP15XX
254 if (cpu_is_omap15xx() && gpio < 16)
257 #if defined(CONFIG_ARCH_OMAP16XX)
258 if ((cpu_is_omap16xx()) && gpio < 64)
261 #ifdef CONFIG_ARCH_OMAP730
262 if (cpu_is_omap730() && gpio < 192)
265 #ifdef CONFIG_ARCH_OMAP24XX
266 if (cpu_is_omap24xx() && gpio < 128)
272 static int check_gpio(int gpio)
274 if (unlikely(gpio_valid(gpio)) < 0) {
275 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
282 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
284 void __iomem *reg = bank->base;
287 switch (bank->method) {
288 #ifdef CONFIG_ARCH_OMAP1
290 reg += OMAP_MPUIO_IO_CNTL;
293 #ifdef CONFIG_ARCH_OMAP15XX
294 case METHOD_GPIO_1510:
295 reg += OMAP1510_GPIO_DIR_CONTROL;
298 #ifdef CONFIG_ARCH_OMAP16XX
299 case METHOD_GPIO_1610:
300 reg += OMAP1610_GPIO_DIRECTION;
303 #ifdef CONFIG_ARCH_OMAP730
304 case METHOD_GPIO_730:
305 reg += OMAP730_GPIO_DIR_CONTROL;
308 #ifdef CONFIG_ARCH_OMAP24XX
309 case METHOD_GPIO_24XX:
310 reg += OMAP24XX_GPIO_OE;
317 l = __raw_readl(reg);
322 __raw_writel(l, reg);
325 void omap_set_gpio_direction(int gpio, int is_input)
327 struct gpio_bank *bank;
329 if (check_gpio(gpio) < 0)
331 bank = get_gpio_bank(gpio);
332 spin_lock(&bank->lock);
333 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
334 spin_unlock(&bank->lock);
337 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
339 void __iomem *reg = bank->base;
342 switch (bank->method) {
343 #ifdef CONFIG_ARCH_OMAP1
345 reg += OMAP_MPUIO_OUTPUT;
346 l = __raw_readl(reg);
353 #ifdef CONFIG_ARCH_OMAP15XX
354 case METHOD_GPIO_1510:
355 reg += OMAP1510_GPIO_DATA_OUTPUT;
356 l = __raw_readl(reg);
363 #ifdef CONFIG_ARCH_OMAP16XX
364 case METHOD_GPIO_1610:
366 reg += OMAP1610_GPIO_SET_DATAOUT;
368 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
372 #ifdef CONFIG_ARCH_OMAP730
373 case METHOD_GPIO_730:
374 reg += OMAP730_GPIO_DATA_OUTPUT;
375 l = __raw_readl(reg);
382 #ifdef CONFIG_ARCH_OMAP24XX
383 case METHOD_GPIO_24XX:
385 reg += OMAP24XX_GPIO_SETDATAOUT;
387 reg += OMAP24XX_GPIO_CLEARDATAOUT;
395 __raw_writel(l, reg);
398 void omap_set_gpio_dataout(int gpio, int enable)
400 struct gpio_bank *bank;
402 if (check_gpio(gpio) < 0)
404 bank = get_gpio_bank(gpio);
405 spin_lock(&bank->lock);
406 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
407 spin_unlock(&bank->lock);
410 int omap_get_gpio_datain(int gpio)
412 struct gpio_bank *bank;
415 if (check_gpio(gpio) < 0)
417 bank = get_gpio_bank(gpio);
419 switch (bank->method) {
420 #ifdef CONFIG_ARCH_OMAP1
422 reg += OMAP_MPUIO_INPUT_LATCH;
425 #ifdef CONFIG_ARCH_OMAP15XX
426 case METHOD_GPIO_1510:
427 reg += OMAP1510_GPIO_DATA_INPUT;
430 #ifdef CONFIG_ARCH_OMAP16XX
431 case METHOD_GPIO_1610:
432 reg += OMAP1610_GPIO_DATAIN;
435 #ifdef CONFIG_ARCH_OMAP730
436 case METHOD_GPIO_730:
437 reg += OMAP730_GPIO_DATA_INPUT;
440 #ifdef CONFIG_ARCH_OMAP24XX
441 case METHOD_GPIO_24XX:
442 reg += OMAP24XX_GPIO_DATAIN;
448 return (__raw_readl(reg)
449 & (1 << get_gpio_index(gpio))) != 0;
452 #define MOD_REG_BIT(reg, bit_mask, set) \
454 int l = __raw_readl(base + reg); \
455 if (set) l |= bit_mask; \
456 else l &= ~bit_mask; \
457 __raw_writel(l, base + reg); \
460 #ifdef CONFIG_ARCH_OMAP24XX
461 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
463 void __iomem *base = bank->base;
464 u32 gpio_bit = 1 << gpio;
466 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
467 trigger & __IRQT_LOWLVL);
468 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
469 trigger & __IRQT_HIGHLVL);
470 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
471 trigger & __IRQT_RISEDGE);
472 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
473 trigger & __IRQT_FALEDGE);
474 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
476 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
478 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
481 bank->enabled_non_wakeup_gpios |= gpio_bit;
483 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
485 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
486 * triggering requested. */
490 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
492 void __iomem *reg = bank->base;
495 switch (bank->method) {
496 #ifdef CONFIG_ARCH_OMAP1
498 reg += OMAP_MPUIO_GPIO_INT_EDGE;
499 l = __raw_readl(reg);
500 if (trigger & __IRQT_RISEDGE)
502 else if (trigger & __IRQT_FALEDGE)
508 #ifdef CONFIG_ARCH_OMAP15XX
509 case METHOD_GPIO_1510:
510 reg += OMAP1510_GPIO_INT_CONTROL;
511 l = __raw_readl(reg);
512 if (trigger & __IRQT_RISEDGE)
514 else if (trigger & __IRQT_FALEDGE)
520 #ifdef CONFIG_ARCH_OMAP16XX
521 case METHOD_GPIO_1610:
523 reg += OMAP1610_GPIO_EDGE_CTRL2;
525 reg += OMAP1610_GPIO_EDGE_CTRL1;
527 l = __raw_readl(reg);
528 l &= ~(3 << (gpio << 1));
529 if (trigger & __IRQT_RISEDGE)
530 l |= 2 << (gpio << 1);
531 if (trigger & __IRQT_FALEDGE)
532 l |= 1 << (gpio << 1);
534 /* Enable wake-up during idle for dynamic tick */
535 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
537 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
540 #ifdef CONFIG_ARCH_OMAP730
541 case METHOD_GPIO_730:
542 reg += OMAP730_GPIO_INT_CONTROL;
543 l = __raw_readl(reg);
544 if (trigger & __IRQT_RISEDGE)
546 else if (trigger & __IRQT_FALEDGE)
552 #ifdef CONFIG_ARCH_OMAP24XX
553 case METHOD_GPIO_24XX:
554 set_24xx_gpio_triggering(bank, gpio, trigger);
560 __raw_writel(l, reg);
566 static int gpio_irq_type(unsigned irq, unsigned type)
568 struct gpio_bank *bank;
572 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
573 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
575 gpio = irq - IH_GPIO_BASE;
577 if (check_gpio(gpio) < 0)
580 if (type & ~IRQ_TYPE_SENSE_MASK)
583 /* OMAP1 allows only only edge triggering */
584 if (!cpu_is_omap24xx()
585 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
588 bank = get_irq_chip_data(irq);
589 spin_lock(&bank->lock);
590 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
592 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
593 irq_desc[irq].status |= type;
595 spin_unlock(&bank->lock);
599 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
601 void __iomem *reg = bank->base;
603 switch (bank->method) {
604 #ifdef CONFIG_ARCH_OMAP1
606 /* MPUIO irqstatus is reset by reading the status register,
607 * so do nothing here */
610 #ifdef CONFIG_ARCH_OMAP15XX
611 case METHOD_GPIO_1510:
612 reg += OMAP1510_GPIO_INT_STATUS;
615 #ifdef CONFIG_ARCH_OMAP16XX
616 case METHOD_GPIO_1610:
617 reg += OMAP1610_GPIO_IRQSTATUS1;
620 #ifdef CONFIG_ARCH_OMAP730
621 case METHOD_GPIO_730:
622 reg += OMAP730_GPIO_INT_STATUS;
625 #ifdef CONFIG_ARCH_OMAP24XX
626 case METHOD_GPIO_24XX:
627 reg += OMAP24XX_GPIO_IRQSTATUS1;
634 __raw_writel(gpio_mask, reg);
636 /* Workaround for clearing DSP GPIO interrupts to allow retention */
637 if (cpu_is_omap2420())
638 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
641 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
643 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
646 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
648 void __iomem *reg = bank->base;
653 switch (bank->method) {
654 #ifdef CONFIG_ARCH_OMAP1
656 reg += OMAP_MPUIO_GPIO_MASKIT;
661 #ifdef CONFIG_ARCH_OMAP15XX
662 case METHOD_GPIO_1510:
663 reg += OMAP1510_GPIO_INT_MASK;
668 #ifdef CONFIG_ARCH_OMAP16XX
669 case METHOD_GPIO_1610:
670 reg += OMAP1610_GPIO_IRQENABLE1;
674 #ifdef CONFIG_ARCH_OMAP730
675 case METHOD_GPIO_730:
676 reg += OMAP730_GPIO_INT_MASK;
681 #ifdef CONFIG_ARCH_OMAP24XX
682 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQENABLE1;
692 l = __raw_readl(reg);
699 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
701 void __iomem *reg = bank->base;
704 switch (bank->method) {
705 #ifdef CONFIG_ARCH_OMAP1
707 reg += OMAP_MPUIO_GPIO_MASKIT;
708 l = __raw_readl(reg);
715 #ifdef CONFIG_ARCH_OMAP15XX
716 case METHOD_GPIO_1510:
717 reg += OMAP1510_GPIO_INT_MASK;
718 l = __raw_readl(reg);
725 #ifdef CONFIG_ARCH_OMAP16XX
726 case METHOD_GPIO_1610:
728 reg += OMAP1610_GPIO_SET_IRQENABLE1;
730 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
734 #ifdef CONFIG_ARCH_OMAP730
735 case METHOD_GPIO_730:
736 reg += OMAP730_GPIO_INT_MASK;
737 l = __raw_readl(reg);
744 #ifdef CONFIG_ARCH_OMAP24XX
745 case METHOD_GPIO_24XX:
747 reg += OMAP24XX_GPIO_SETIRQENABLE1;
749 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
757 __raw_writel(l, reg);
760 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
762 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
766 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
767 * 1510 does not seem to have a wake-up register. If JTAG is connected
768 * to the target, system will wake up always on GPIO events. While
769 * system is running all registered GPIO interrupts need to have wake-up
770 * enabled. When system is suspended, only selected GPIO interrupts need
771 * to have wake-up enabled.
773 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
775 switch (bank->method) {
776 #ifdef CONFIG_ARCH_OMAP16XX
778 case METHOD_GPIO_1610:
779 spin_lock(&bank->lock);
781 bank->suspend_wakeup |= (1 << gpio);
782 enable_irq_wake(bank->irq);
784 disable_irq_wake(bank->irq);
785 bank->suspend_wakeup &= ~(1 << gpio);
787 spin_unlock(&bank->lock);
790 #ifdef CONFIG_ARCH_OMAP24XX
791 case METHOD_GPIO_24XX:
792 if (bank->non_wakeup_gpios & (1 << gpio)) {
793 printk(KERN_ERR "Unable to modify wakeup on "
794 "non-wakeup GPIO%d\n",
795 (bank - gpio_bank) * 32 + gpio);
798 spin_lock(&bank->lock);
800 bank->suspend_wakeup |= (1 << gpio);
801 enable_irq_wake(bank->irq);
803 disable_irq_wake(bank->irq);
804 bank->suspend_wakeup &= ~(1 << gpio);
806 spin_unlock(&bank->lock);
810 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
816 static void _reset_gpio(struct gpio_bank *bank, int gpio)
818 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
819 _set_gpio_irqenable(bank, gpio, 0);
820 _clear_gpio_irqstatus(bank, gpio);
821 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
824 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
825 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
827 unsigned int gpio = irq - IH_GPIO_BASE;
828 struct gpio_bank *bank;
831 if (check_gpio(gpio) < 0)
833 bank = get_irq_chip_data(irq);
834 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
839 int omap_request_gpio(int gpio)
841 struct gpio_bank *bank;
843 if (check_gpio(gpio) < 0)
846 bank = get_gpio_bank(gpio);
847 spin_lock(&bank->lock);
848 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
849 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
851 spin_unlock(&bank->lock);
854 bank->reserved_map |= (1 << get_gpio_index(gpio));
856 /* Set trigger to none. You need to enable the desired trigger with
857 * request_irq() or set_irq_type().
859 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
861 #ifdef CONFIG_ARCH_OMAP15XX
862 if (bank->method == METHOD_GPIO_1510) {
865 /* Claim the pin for MPU */
866 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
867 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
870 spin_unlock(&bank->lock);
875 void omap_free_gpio(int gpio)
877 struct gpio_bank *bank;
879 if (check_gpio(gpio) < 0)
881 bank = get_gpio_bank(gpio);
882 spin_lock(&bank->lock);
883 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
884 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
886 spin_unlock(&bank->lock);
889 #ifdef CONFIG_ARCH_OMAP16XX
890 if (bank->method == METHOD_GPIO_1610) {
891 /* Disable wake-up during idle for dynamic tick */
892 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
893 __raw_writel(1 << get_gpio_index(gpio), reg);
896 #ifdef CONFIG_ARCH_OMAP24XX
897 if (bank->method == METHOD_GPIO_24XX) {
898 /* Disable wake-up during idle for dynamic tick */
899 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
900 __raw_writel(1 << get_gpio_index(gpio), reg);
903 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
904 _reset_gpio(bank, gpio);
905 spin_unlock(&bank->lock);
909 * We need to unmask the GPIO bank interrupt as soon as possible to
910 * avoid missing GPIO interrupts for other lines in the bank.
911 * Then we need to mask-read-clear-unmask the triggered GPIO lines
912 * in the bank to avoid missing nested interrupts for a GPIO line.
913 * If we wait to unmask individual GPIO lines in the bank after the
914 * line's interrupt handler has been run, we may miss some nested
917 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
919 void __iomem *isr_reg = NULL;
921 unsigned int gpio_irq;
922 struct gpio_bank *bank;
926 desc->chip->ack(irq);
928 bank = get_irq_data(irq);
929 #ifdef CONFIG_ARCH_OMAP1
930 if (bank->method == METHOD_MPUIO)
931 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
933 #ifdef CONFIG_ARCH_OMAP15XX
934 if (bank->method == METHOD_GPIO_1510)
935 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
937 #if defined(CONFIG_ARCH_OMAP16XX)
938 if (bank->method == METHOD_GPIO_1610)
939 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
941 #ifdef CONFIG_ARCH_OMAP730
942 if (bank->method == METHOD_GPIO_730)
943 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
945 #ifdef CONFIG_ARCH_OMAP24XX
946 if (bank->method == METHOD_GPIO_24XX)
947 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
950 u32 isr_saved, level_mask = 0;
953 enabled = _get_gpio_irqbank_mask(bank);
954 isr_saved = isr = __raw_readl(isr_reg) & enabled;
956 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
959 if (cpu_is_omap24xx()) {
961 __raw_readl(bank->base +
962 OMAP24XX_GPIO_LEVELDETECT0) |
963 __raw_readl(bank->base +
964 OMAP24XX_GPIO_LEVELDETECT1);
965 level_mask &= enabled;
968 /* clear edge sensitive interrupts before handler(s) are
969 called so that we don't miss any interrupt occurred while
971 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
972 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
973 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
975 /* if there is only edge sensitive GPIO pin interrupts
976 configured, we could unmask GPIO bank interrupt immediately */
977 if (!level_mask && !unmasked) {
979 desc->chip->unmask(irq);
987 gpio_irq = bank->virtual_irq_start;
988 for (; isr != 0; isr >>= 1, gpio_irq++) {
993 d = irq_desc + gpio_irq;
994 /* Don't run the handler if it's already running
995 * or was disabled lazely.
997 if (unlikely((d->depth ||
998 (d->status & IRQ_INPROGRESS)))) {
1000 (gpio_irq - bank->virtual_irq_start);
1001 /* The unmasking will be done by
1002 * enable_irq in case it is disabled or
1003 * after returning from the handler if
1004 * it's already running.
1006 _enable_gpio_irqbank(bank, irq_mask, 0);
1008 /* Level triggered interrupts
1009 * won't ever be reentered
1011 BUG_ON(level_mask & irq_mask);
1012 d->status |= IRQ_PENDING;
1017 desc_handle_irq(gpio_irq, d);
1019 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1021 (gpio_irq - bank->virtual_irq_start);
1022 d->status &= ~IRQ_PENDING;
1023 _enable_gpio_irqbank(bank, irq_mask, 1);
1024 retrigger |= irq_mask;
1028 if (cpu_is_omap24xx()) {
1029 /* clear level sensitive interrupts after handler(s) */
1030 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1031 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1032 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1036 /* if bank has any level sensitive GPIO pin interrupt
1037 configured, we must unmask the bank interrupt only after
1038 handler(s) are executed in order to avoid spurious bank
1041 desc->chip->unmask(irq);
1045 static void gpio_irq_shutdown(unsigned int irq)
1047 unsigned int gpio = irq - IH_GPIO_BASE;
1048 struct gpio_bank *bank = get_irq_chip_data(irq);
1050 _reset_gpio(bank, gpio);
1053 static void gpio_ack_irq(unsigned int irq)
1055 unsigned int gpio = irq - IH_GPIO_BASE;
1056 struct gpio_bank *bank = get_irq_chip_data(irq);
1058 _clear_gpio_irqstatus(bank, gpio);
1061 static void gpio_mask_irq(unsigned int irq)
1063 unsigned int gpio = irq - IH_GPIO_BASE;
1064 struct gpio_bank *bank = get_irq_chip_data(irq);
1066 _set_gpio_irqenable(bank, gpio, 0);
1069 static void gpio_unmask_irq(unsigned int irq)
1071 unsigned int gpio = irq - IH_GPIO_BASE;
1072 unsigned int gpio_idx = get_gpio_index(gpio);
1073 struct gpio_bank *bank = get_irq_chip_data(irq);
1075 _set_gpio_irqenable(bank, gpio_idx, 1);
1078 static struct irq_chip gpio_irq_chip = {
1080 .shutdown = gpio_irq_shutdown,
1081 .ack = gpio_ack_irq,
1082 .mask = gpio_mask_irq,
1083 .unmask = gpio_unmask_irq,
1084 .set_type = gpio_irq_type,
1085 .set_wake = gpio_wake_enable,
1088 /*---------------------------------------------------------------------*/
1090 #ifdef CONFIG_ARCH_OMAP1
1092 /* MPUIO uses the always-on 32k clock */
1094 static void mpuio_ack_irq(unsigned int irq)
1096 /* The ISR is reset automatically, so do nothing here. */
1099 static void mpuio_mask_irq(unsigned int irq)
1101 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1102 struct gpio_bank *bank = get_irq_chip_data(irq);
1104 _set_gpio_irqenable(bank, gpio, 0);
1107 static void mpuio_unmask_irq(unsigned int irq)
1109 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1110 struct gpio_bank *bank = get_irq_chip_data(irq);
1112 _set_gpio_irqenable(bank, gpio, 1);
1115 static struct irq_chip mpuio_irq_chip = {
1117 .ack = mpuio_ack_irq,
1118 .mask = mpuio_mask_irq,
1119 .unmask = mpuio_unmask_irq,
1120 .set_type = gpio_irq_type,
1121 #ifdef CONFIG_ARCH_OMAP16XX
1122 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1123 .set_wake = gpio_wake_enable,
1128 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1131 #ifdef CONFIG_ARCH_OMAP16XX
1133 #include <linux/platform_device.h>
1135 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1137 struct gpio_bank *bank = platform_get_drvdata(pdev);
1138 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1140 spin_lock(&bank->lock);
1141 bank->saved_wakeup = __raw_readl(mask_reg);
1142 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1143 spin_unlock(&bank->lock);
1148 static int omap_mpuio_resume_early(struct platform_device *pdev)
1150 struct gpio_bank *bank = platform_get_drvdata(pdev);
1151 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1153 spin_lock(&bank->lock);
1154 __raw_writel(bank->saved_wakeup, mask_reg);
1155 spin_unlock(&bank->lock);
1160 /* use platform_driver for this, now that there's no longer any
1161 * point to sys_device (other than not disturbing old code).
1163 static struct platform_driver omap_mpuio_driver = {
1164 .suspend_late = omap_mpuio_suspend_late,
1165 .resume_early = omap_mpuio_resume_early,
1171 static struct platform_device omap_mpuio_device = {
1175 .driver = &omap_mpuio_driver.driver,
1177 /* could list the /proc/iomem resources */
1180 static inline void mpuio_init(void)
1182 if (platform_driver_register(&omap_mpuio_driver) == 0)
1183 (void) platform_device_register(&omap_mpuio_device);
1187 static inline void mpuio_init(void) {}
1192 extern struct irq_chip mpuio_irq_chip;
1194 #define bank_is_mpuio(bank) 0
1195 static inline void mpuio_init(void) {}
1199 /*---------------------------------------------------------------------*/
1201 static int initialized;
1202 static struct clk * gpio_ick;
1203 static struct clk * gpio_fck;
1205 #ifdef CONFIG_ARCH_OMAP2430
1206 static struct clk * gpio5_ick;
1207 static struct clk * gpio5_fck;
1210 static int __init _omap_gpio_init(void)
1213 struct gpio_bank *bank;
1217 if (cpu_is_omap15xx()) {
1218 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1219 if (IS_ERR(gpio_ick))
1220 printk("Could not get arm_gpio_ck\n");
1222 clk_enable(gpio_ick);
1224 if (cpu_is_omap24xx()) {
1225 gpio_ick = clk_get(NULL, "gpios_ick");
1226 if (IS_ERR(gpio_ick))
1227 printk("Could not get gpios_ick\n");
1229 clk_enable(gpio_ick);
1230 gpio_fck = clk_get(NULL, "gpios_fck");
1231 if (IS_ERR(gpio_fck))
1232 printk("Could not get gpios_fck\n");
1234 clk_enable(gpio_fck);
1237 * On 2430 GPIO 5 uses CORE L4 ICLK
1239 #ifdef CONFIG_ARCH_OMAP2430
1240 if (cpu_is_omap2430()) {
1241 gpio5_ick = clk_get(NULL, "gpio5_ick");
1242 if (IS_ERR(gpio5_ick))
1243 printk("Could not get gpio5_ick\n");
1245 clk_enable(gpio5_ick);
1246 gpio5_fck = clk_get(NULL, "gpio5_fck");
1247 if (IS_ERR(gpio5_fck))
1248 printk("Could not get gpio5_fck\n");
1250 clk_enable(gpio5_fck);
1255 #ifdef CONFIG_ARCH_OMAP15XX
1256 if (cpu_is_omap15xx()) {
1257 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1258 gpio_bank_count = 2;
1259 gpio_bank = gpio_bank_1510;
1262 #if defined(CONFIG_ARCH_OMAP16XX)
1263 if (cpu_is_omap16xx()) {
1266 gpio_bank_count = 5;
1267 gpio_bank = gpio_bank_1610;
1268 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1269 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1270 (rev >> 4) & 0x0f, rev & 0x0f);
1273 #ifdef CONFIG_ARCH_OMAP730
1274 if (cpu_is_omap730()) {
1275 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1276 gpio_bank_count = 7;
1277 gpio_bank = gpio_bank_730;
1281 #ifdef CONFIG_ARCH_OMAP24XX
1282 if (cpu_is_omap242x()) {
1285 gpio_bank_count = 4;
1286 gpio_bank = gpio_bank_242x;
1287 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1288 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1289 (rev >> 4) & 0x0f, rev & 0x0f);
1291 if (cpu_is_omap243x()) {
1294 gpio_bank_count = 5;
1295 gpio_bank = gpio_bank_243x;
1296 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1297 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1298 (rev >> 4) & 0x0f, rev & 0x0f);
1301 for (i = 0; i < gpio_bank_count; i++) {
1302 int j, gpio_count = 16;
1304 bank = &gpio_bank[i];
1305 bank->reserved_map = 0;
1306 bank->base = IO_ADDRESS(bank->base);
1307 spin_lock_init(&bank->lock);
1308 if (bank_is_mpuio(bank))
1309 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1310 #ifdef CONFIG_ARCH_OMAP15XX
1311 if (bank->method == METHOD_GPIO_1510) {
1312 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1313 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1316 #if defined(CONFIG_ARCH_OMAP16XX)
1317 if (bank->method == METHOD_GPIO_1610) {
1318 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1319 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1320 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1323 #ifdef CONFIG_ARCH_OMAP730
1324 if (bank->method == METHOD_GPIO_730) {
1325 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1326 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1328 gpio_count = 32; /* 730 has 32-bit GPIOs */
1331 #ifdef CONFIG_ARCH_OMAP24XX
1332 if (bank->method == METHOD_GPIO_24XX) {
1333 static const u32 non_wakeup_gpios[] = {
1334 0xe203ffc0, 0x08700040
1337 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1338 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1339 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1341 /* Initialize interface clock ungated, module enabled */
1342 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1343 if (i < ARRAY_SIZE(non_wakeup_gpios))
1344 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1348 for (j = bank->virtual_irq_start;
1349 j < bank->virtual_irq_start + gpio_count; j++) {
1350 set_irq_chip_data(j, bank);
1351 if (bank_is_mpuio(bank))
1352 set_irq_chip(j, &mpuio_irq_chip);
1354 set_irq_chip(j, &gpio_irq_chip);
1355 set_irq_handler(j, do_simple_IRQ);
1356 set_irq_flags(j, IRQF_VALID);
1358 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1359 set_irq_data(bank->irq, bank);
1362 /* Enable system clock for GPIO module.
1363 * The CAM_CLK_CTRL *is* really the right place. */
1364 if (cpu_is_omap16xx())
1365 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1367 #ifdef CONFIG_ARCH_OMAP24XX
1368 /* Enable autoidle for the OCP interface */
1369 if (cpu_is_omap24xx())
1370 omap_writel(1 << 0, 0x48019010);
1376 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1377 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1381 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1384 for (i = 0; i < gpio_bank_count; i++) {
1385 struct gpio_bank *bank = &gpio_bank[i];
1386 void __iomem *wake_status;
1387 void __iomem *wake_clear;
1388 void __iomem *wake_set;
1390 switch (bank->method) {
1391 #ifdef CONFIG_ARCH_OMAP16XX
1392 case METHOD_GPIO_1610:
1393 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1394 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1395 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1398 #ifdef CONFIG_ARCH_OMAP24XX
1399 case METHOD_GPIO_24XX:
1400 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1401 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1402 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1409 spin_lock(&bank->lock);
1410 bank->saved_wakeup = __raw_readl(wake_status);
1411 __raw_writel(0xffffffff, wake_clear);
1412 __raw_writel(bank->suspend_wakeup, wake_set);
1413 spin_unlock(&bank->lock);
1419 static int omap_gpio_resume(struct sys_device *dev)
1423 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1426 for (i = 0; i < gpio_bank_count; i++) {
1427 struct gpio_bank *bank = &gpio_bank[i];
1428 void __iomem *wake_clear;
1429 void __iomem *wake_set;
1431 switch (bank->method) {
1432 #ifdef CONFIG_ARCH_OMAP16XX
1433 case METHOD_GPIO_1610:
1434 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1435 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1438 #ifdef CONFIG_ARCH_OMAP24XX
1439 case METHOD_GPIO_24XX:
1440 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1441 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1448 spin_lock(&bank->lock);
1449 __raw_writel(0xffffffff, wake_clear);
1450 __raw_writel(bank->saved_wakeup, wake_set);
1451 spin_unlock(&bank->lock);
1457 static struct sysdev_class omap_gpio_sysclass = {
1458 set_kset_name("gpio"),
1459 .suspend = omap_gpio_suspend,
1460 .resume = omap_gpio_resume,
1463 static struct sys_device omap_gpio_device = {
1465 .cls = &omap_gpio_sysclass,
1470 #ifdef CONFIG_ARCH_OMAP24XX
1472 static int workaround_enabled;
1474 void omap2_gpio_prepare_for_retention(void)
1478 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1479 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1480 for (i = 0; i < gpio_bank_count; i++) {
1481 struct gpio_bank *bank = &gpio_bank[i];
1484 if (!(bank->enabled_non_wakeup_gpios))
1486 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1487 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1488 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1489 bank->saved_fallingdetect = l1;
1490 bank->saved_risingdetect = l2;
1491 l1 &= ~bank->enabled_non_wakeup_gpios;
1492 l2 &= ~bank->enabled_non_wakeup_gpios;
1493 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1494 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1498 workaround_enabled = 0;
1501 workaround_enabled = 1;
1504 void omap2_gpio_resume_after_retention(void)
1508 if (!workaround_enabled)
1510 for (i = 0; i < gpio_bank_count; i++) {
1511 struct gpio_bank *bank = &gpio_bank[i];
1514 if (!(bank->enabled_non_wakeup_gpios))
1516 __raw_writel(bank->saved_fallingdetect,
1517 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1518 __raw_writel(bank->saved_risingdetect,
1519 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1520 /* Check if any of the non-wakeup interrupt GPIOs have changed
1521 * state. If so, generate an IRQ by software. This is
1522 * horribly racy, but it's the best we can do to work around
1523 * this silicon bug. */
1524 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1525 l ^= bank->saved_datain;
1526 l &= bank->non_wakeup_gpios;
1530 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1531 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1532 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1533 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1534 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1535 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1544 * This may get called early from board specific init
1545 * for boards that have interrupts routed via FPGA.
1547 int __init omap_gpio_init(void)
1550 return _omap_gpio_init();
1555 static int __init omap_gpio_sysinit(void)
1560 ret = _omap_gpio_init();
1564 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1565 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1567 ret = sysdev_class_register(&omap_gpio_sysclass);
1569 ret = sysdev_register(&omap_gpio_device);
1577 EXPORT_SYMBOL(omap_request_gpio);
1578 EXPORT_SYMBOL(omap_free_gpio);
1579 EXPORT_SYMBOL(omap_set_gpio_direction);
1580 EXPORT_SYMBOL(omap_set_gpio_dataout);
1581 EXPORT_SYMBOL(omap_get_gpio_datain);
1583 arch_initcall(omap_gpio_sysinit);
1586 #ifdef CONFIG_DEBUG_FS
1588 #include <linux/debugfs.h>
1589 #include <linux/seq_file.h>
1591 static int gpio_is_input(struct gpio_bank *bank, int mask)
1593 void __iomem *reg = bank->base;
1595 switch (bank->method) {
1597 reg += OMAP_MPUIO_IO_CNTL;
1599 case METHOD_GPIO_1510:
1600 reg += OMAP1510_GPIO_DIR_CONTROL;
1602 case METHOD_GPIO_1610:
1603 reg += OMAP1610_GPIO_DIRECTION;
1605 case METHOD_GPIO_730:
1606 reg += OMAP730_GPIO_DIR_CONTROL;
1608 case METHOD_GPIO_24XX:
1609 reg += OMAP24XX_GPIO_OE;
1612 return __raw_readl(reg) & mask;
1616 static int dbg_gpio_show(struct seq_file *s, void *unused)
1618 unsigned i, j, gpio;
1620 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1621 struct gpio_bank *bank = gpio_bank + i;
1622 unsigned bankwidth = 16;
1625 if (bank_is_mpuio(bank))
1626 gpio = OMAP_MPUIO(0);
1627 else if (cpu_is_omap24xx() || cpu_is_omap730())
1630 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1631 unsigned irq, value, is_in, irqstat;
1633 if (!(bank->reserved_map & mask))
1636 irq = bank->virtual_irq_start + j;
1637 value = omap_get_gpio_datain(gpio);
1638 is_in = gpio_is_input(bank, mask);
1640 if (bank_is_mpuio(bank))
1641 seq_printf(s, "MPUIO %2d: ", j);
1643 seq_printf(s, "GPIO %3d: ", gpio);
1644 seq_printf(s, "%s %s",
1645 is_in ? "in " : "out",
1646 value ? "hi" : "lo");
1648 irqstat = irq_desc[irq].status;
1649 if (is_in && ((bank->suspend_wakeup & mask)
1650 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1651 char *trigger = NULL;
1653 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1654 case IRQ_TYPE_EDGE_FALLING:
1655 trigger = "falling";
1657 case IRQ_TYPE_EDGE_RISING:
1660 case IRQ_TYPE_EDGE_BOTH:
1661 trigger = "bothedge";
1663 case IRQ_TYPE_LEVEL_LOW:
1666 case IRQ_TYPE_LEVEL_HIGH:
1670 trigger = "(unspecified)";
1673 seq_printf(s, ", irq-%d %s%s",
1675 (bank->suspend_wakeup & mask)
1678 seq_printf(s, "\n");
1681 if (bank_is_mpuio(bank)) {
1682 seq_printf(s, "\n");
1689 static int dbg_gpio_open(struct inode *inode, struct file *file)
1691 return single_open(file, dbg_gpio_show, &inode->i_private);
1694 static const struct file_operations debug_fops = {
1695 .open = dbg_gpio_open,
1697 .llseek = seq_lseek,
1698 .release = single_release,
1701 static int __init omap_gpio_debuginit(void)
1703 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1704 NULL, NULL, &debug_fops);
1707 late_initcall(omap_gpio_debuginit);