2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/ptrace.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
24 #include <asm/hardware.h>
26 #include <asm/arch/irqs.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/mach/irq.h>
33 * OMAP1510 GPIO registers
35 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
50 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
51 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
52 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72 * OMAP730 specific GPIO registers
74 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
75 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
76 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
77 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
78 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
79 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
80 #define OMAP730_GPIO_DATA_INPUT 0x00
81 #define OMAP730_GPIO_DATA_OUTPUT 0x04
82 #define OMAP730_GPIO_DIR_CONTROL 0x08
83 #define OMAP730_GPIO_INT_CONTROL 0x0c
84 #define OMAP730_GPIO_INT_MASK 0x10
85 #define OMAP730_GPIO_INT_STATUS 0x14
88 * omap24xx specific GPIO registers
90 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
91 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
92 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
93 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
94 #define OMAP24XX_GPIO_REVISION 0x0000
95 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
96 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
97 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
114 #define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
119 u16 virtual_irq_start;
127 #define METHOD_MPUIO 0
128 #define METHOD_GPIO_1510 1
129 #define METHOD_GPIO_1610 2
130 #define METHOD_GPIO_730 3
131 #define METHOD_GPIO_24XX 4
133 #ifdef CONFIG_ARCH_OMAP16XX
134 static struct gpio_bank gpio_bank_1610[5] = {
135 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
136 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
137 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
138 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
139 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
143 #ifdef CONFIG_ARCH_OMAP15XX
144 static struct gpio_bank gpio_bank_1510[2] = {
145 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
146 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
150 #ifdef CONFIG_ARCH_OMAP730
151 static struct gpio_bank gpio_bank_730[7] = {
152 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
153 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
154 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
155 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
156 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
157 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
158 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
162 #ifdef CONFIG_ARCH_OMAP24XX
163 static struct gpio_bank gpio_bank_24xx[4] = {
164 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
166 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
167 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
171 static struct gpio_bank *gpio_bank;
172 static int gpio_bank_count;
174 static inline struct gpio_bank *get_gpio_bank(int gpio)
176 #ifdef CONFIG_ARCH_OMAP15XX
177 if (cpu_is_omap15xx()) {
178 if (OMAP_GPIO_IS_MPUIO(gpio))
179 return &gpio_bank[0];
180 return &gpio_bank[1];
183 #if defined(CONFIG_ARCH_OMAP16XX)
184 if (cpu_is_omap16xx()) {
185 if (OMAP_GPIO_IS_MPUIO(gpio))
186 return &gpio_bank[0];
187 return &gpio_bank[1 + (gpio >> 4)];
190 #ifdef CONFIG_ARCH_OMAP730
191 if (cpu_is_omap730()) {
192 if (OMAP_GPIO_IS_MPUIO(gpio))
193 return &gpio_bank[0];
194 return &gpio_bank[1 + (gpio >> 5)];
197 #ifdef CONFIG_ARCH_OMAP24XX
198 if (cpu_is_omap24xx())
199 return &gpio_bank[gpio >> 5];
203 static inline int get_gpio_index(int gpio)
205 #ifdef CONFIG_ARCH_OMAP730
206 if (cpu_is_omap730())
209 #ifdef CONFIG_ARCH_OMAP24XX
210 if (cpu_is_omap24xx())
216 static inline int gpio_valid(int gpio)
220 if (OMAP_GPIO_IS_MPUIO(gpio)) {
221 if ((gpio & OMAP_MPUIO_MASK) > 16)
225 #ifdef CONFIG_ARCH_OMAP15XX
226 if (cpu_is_omap15xx() && gpio < 16)
229 #if defined(CONFIG_ARCH_OMAP16XX)
230 if ((cpu_is_omap16xx()) && gpio < 64)
233 #ifdef CONFIG_ARCH_OMAP730
234 if (cpu_is_omap730() && gpio < 192)
237 #ifdef CONFIG_ARCH_OMAP24XX
238 if (cpu_is_omap24xx() && gpio < 128)
244 static int check_gpio(int gpio)
246 if (unlikely(gpio_valid(gpio)) < 0) {
247 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
254 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
256 void __iomem *reg = bank->base;
259 switch (bank->method) {
261 reg += OMAP_MPUIO_IO_CNTL;
263 case METHOD_GPIO_1510:
264 reg += OMAP1510_GPIO_DIR_CONTROL;
266 case METHOD_GPIO_1610:
267 reg += OMAP1610_GPIO_DIRECTION;
269 case METHOD_GPIO_730:
270 reg += OMAP730_GPIO_DIR_CONTROL;
272 case METHOD_GPIO_24XX:
273 reg += OMAP24XX_GPIO_OE;
276 l = __raw_readl(reg);
281 __raw_writel(l, reg);
284 void omap_set_gpio_direction(int gpio, int is_input)
286 struct gpio_bank *bank;
288 if (check_gpio(gpio) < 0)
290 bank = get_gpio_bank(gpio);
291 spin_lock(&bank->lock);
292 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
293 spin_unlock(&bank->lock);
296 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
298 void __iomem *reg = bank->base;
301 switch (bank->method) {
303 reg += OMAP_MPUIO_OUTPUT;
304 l = __raw_readl(reg);
310 case METHOD_GPIO_1510:
311 reg += OMAP1510_GPIO_DATA_OUTPUT;
312 l = __raw_readl(reg);
318 case METHOD_GPIO_1610:
320 reg += OMAP1610_GPIO_SET_DATAOUT;
322 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
325 case METHOD_GPIO_730:
326 reg += OMAP730_GPIO_DATA_OUTPUT;
327 l = __raw_readl(reg);
333 case METHOD_GPIO_24XX:
335 reg += OMAP24XX_GPIO_SETDATAOUT;
337 reg += OMAP24XX_GPIO_CLEARDATAOUT;
344 __raw_writel(l, reg);
347 void omap_set_gpio_dataout(int gpio, int enable)
349 struct gpio_bank *bank;
351 if (check_gpio(gpio) < 0)
353 bank = get_gpio_bank(gpio);
354 spin_lock(&bank->lock);
355 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
356 spin_unlock(&bank->lock);
359 int omap_get_gpio_datain(int gpio)
361 struct gpio_bank *bank;
364 if (check_gpio(gpio) < 0)
366 bank = get_gpio_bank(gpio);
368 switch (bank->method) {
370 reg += OMAP_MPUIO_INPUT_LATCH;
372 case METHOD_GPIO_1510:
373 reg += OMAP1510_GPIO_DATA_INPUT;
375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DATAIN;
378 case METHOD_GPIO_730:
379 reg += OMAP730_GPIO_DATA_INPUT;
381 case METHOD_GPIO_24XX:
382 reg += OMAP24XX_GPIO_DATAIN;
388 return (__raw_readl(reg)
389 & (1 << get_gpio_index(gpio))) != 0;
392 #define MOD_REG_BIT(reg, bit_mask, set) \
394 int l = __raw_readl(base + reg); \
395 if (set) l |= bit_mask; \
396 else l &= ~bit_mask; \
397 __raw_writel(l, base + reg); \
400 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
402 u32 gpio_bit = 1 << gpio;
404 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
405 trigger & __IRQT_LOWLVL);
406 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
407 trigger & __IRQT_HIGHLVL);
408 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
409 trigger & __IRQT_RISEDGE);
410 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
411 trigger & __IRQT_FALEDGE);
412 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
413 * triggering requested. */
416 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
418 void __iomem *reg = bank->base;
421 switch (bank->method) {
423 reg += OMAP_MPUIO_GPIO_INT_EDGE;
424 l = __raw_readl(reg);
425 if (trigger & __IRQT_RISEDGE)
427 else if (trigger & __IRQT_FALEDGE)
432 case METHOD_GPIO_1510:
433 reg += OMAP1510_GPIO_INT_CONTROL;
434 l = __raw_readl(reg);
435 if (trigger & __IRQT_RISEDGE)
437 else if (trigger & __IRQT_FALEDGE)
442 case METHOD_GPIO_1610:
444 reg += OMAP1610_GPIO_EDGE_CTRL2;
446 reg += OMAP1610_GPIO_EDGE_CTRL1;
448 /* We allow only edge triggering, i.e. two lowest bits */
449 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
451 l = __raw_readl(reg);
452 l &= ~(3 << (gpio << 1));
453 if (trigger & __IRQT_RISEDGE)
454 l |= 2 << (gpio << 1);
455 else if (trigger & __IRQT_FALEDGE)
456 l |= 1 << (gpio << 1);
460 case METHOD_GPIO_730:
461 reg += OMAP730_GPIO_INT_CONTROL;
462 l = __raw_readl(reg);
463 if (trigger & __IRQT_RISEDGE)
465 else if (trigger & __IRQT_FALEDGE)
470 case METHOD_GPIO_24XX:
471 set_24xx_gpio_triggering(reg, gpio, trigger);
477 __raw_writel(l, reg);
483 static int gpio_irq_type(unsigned irq, unsigned type)
485 struct gpio_bank *bank;
489 if (irq > IH_MPUIO_BASE)
490 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
492 gpio = irq - IH_GPIO_BASE;
494 if (check_gpio(gpio) < 0)
497 if (type & IRQT_PROBE)
499 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
502 bank = get_gpio_bank(gpio);
503 spin_lock(&bank->lock);
504 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
505 spin_unlock(&bank->lock);
509 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
511 void __iomem *reg = bank->base;
513 switch (bank->method) {
515 /* MPUIO irqstatus is reset by reading the status register,
516 * so do nothing here */
518 case METHOD_GPIO_1510:
519 reg += OMAP1510_GPIO_INT_STATUS;
521 case METHOD_GPIO_1610:
522 reg += OMAP1610_GPIO_IRQSTATUS1;
524 case METHOD_GPIO_730:
525 reg += OMAP730_GPIO_INT_STATUS;
527 case METHOD_GPIO_24XX:
528 reg += OMAP24XX_GPIO_IRQSTATUS1;
534 __raw_writel(gpio_mask, reg);
537 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
539 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
542 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
544 void __iomem *reg = bank->base;
547 switch (bank->method) {
549 reg += OMAP_MPUIO_GPIO_MASKIT;
550 l = __raw_readl(reg);
556 case METHOD_GPIO_1510:
557 reg += OMAP1510_GPIO_INT_MASK;
558 l = __raw_readl(reg);
564 case METHOD_GPIO_1610:
566 reg += OMAP1610_GPIO_SET_IRQENABLE1;
568 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
571 case METHOD_GPIO_730:
572 reg += OMAP730_GPIO_INT_MASK;
573 l = __raw_readl(reg);
579 case METHOD_GPIO_24XX:
581 reg += OMAP24XX_GPIO_SETIRQENABLE1;
583 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
590 __raw_writel(l, reg);
593 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
595 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
599 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
600 * 1510 does not seem to have a wake-up register. If JTAG is connected
601 * to the target, system will wake up always on GPIO events. While
602 * system is running all registered GPIO interrupts need to have wake-up
603 * enabled. When system is suspended, only selected GPIO interrupts need
604 * to have wake-up enabled.
606 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
608 switch (bank->method) {
609 case METHOD_GPIO_1610:
610 case METHOD_GPIO_24XX:
611 spin_lock(&bank->lock);
613 bank->suspend_wakeup |= (1 << gpio);
615 bank->suspend_wakeup &= ~(1 << gpio);
616 spin_unlock(&bank->lock);
619 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
625 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
626 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
628 unsigned int gpio = irq - IH_GPIO_BASE;
629 struct gpio_bank *bank;
632 if (check_gpio(gpio) < 0)
634 bank = get_gpio_bank(gpio);
635 spin_lock(&bank->lock);
636 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
637 spin_unlock(&bank->lock);
642 int omap_request_gpio(int gpio)
644 struct gpio_bank *bank;
646 if (check_gpio(gpio) < 0)
649 bank = get_gpio_bank(gpio);
650 spin_lock(&bank->lock);
651 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
652 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
654 spin_unlock(&bank->lock);
657 bank->reserved_map |= (1 << get_gpio_index(gpio));
659 /* Set trigger to none. You need to enable the trigger after request_irq */
660 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
662 #ifdef CONFIG_ARCH_OMAP15XX
663 if (bank->method == METHOD_GPIO_1510) {
666 /* Claim the pin for MPU */
667 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
668 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
671 #ifdef CONFIG_ARCH_OMAP16XX
672 if (bank->method == METHOD_GPIO_1610) {
673 /* Enable wake-up during idle for dynamic tick */
674 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
675 __raw_writel(1 << get_gpio_index(gpio), reg);
678 #ifdef CONFIG_ARCH_OMAP24XX
679 if (bank->method == METHOD_GPIO_24XX) {
680 /* Enable wake-up during idle for dynamic tick */
681 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
682 __raw_writel(1 << get_gpio_index(gpio), reg);
685 spin_unlock(&bank->lock);
690 void omap_free_gpio(int gpio)
692 struct gpio_bank *bank;
694 if (check_gpio(gpio) < 0)
696 bank = get_gpio_bank(gpio);
697 spin_lock(&bank->lock);
698 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
699 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
701 spin_unlock(&bank->lock);
704 #ifdef CONFIG_ARCH_OMAP16XX
705 if (bank->method == METHOD_GPIO_1610) {
706 /* Disable wake-up during idle for dynamic tick */
707 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
708 __raw_writel(1 << get_gpio_index(gpio), reg);
711 #ifdef CONFIG_ARCH_OMAP24XX
712 if (bank->method == METHOD_GPIO_24XX) {
713 /* Disable wake-up during idle for dynamic tick */
714 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
715 __raw_writel(1 << get_gpio_index(gpio), reg);
718 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
719 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
720 _set_gpio_irqenable(bank, gpio, 0);
721 _clear_gpio_irqstatus(bank, gpio);
722 spin_unlock(&bank->lock);
726 * We need to unmask the GPIO bank interrupt as soon as possible to
727 * avoid missing GPIO interrupts for other lines in the bank.
728 * Then we need to mask-read-clear-unmask the triggered GPIO lines
729 * in the bank to avoid missing nested interrupts for a GPIO line.
730 * If we wait to unmask individual GPIO lines in the bank after the
731 * line's interrupt handler has been run, we may miss some nested
734 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
735 struct pt_regs *regs)
737 void __iomem *isr_reg = NULL;
739 unsigned int gpio_irq;
740 struct gpio_bank *bank;
742 desc->chip->ack(irq);
744 bank = (struct gpio_bank *) desc->data;
745 if (bank->method == METHOD_MPUIO)
746 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
747 #ifdef CONFIG_ARCH_OMAP15XX
748 if (bank->method == METHOD_GPIO_1510)
749 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
751 #if defined(CONFIG_ARCH_OMAP16XX)
752 if (bank->method == METHOD_GPIO_1610)
753 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
755 #ifdef CONFIG_ARCH_OMAP730
756 if (bank->method == METHOD_GPIO_730)
757 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
759 #ifdef CONFIG_ARCH_OMAP24XX
760 if (bank->method == METHOD_GPIO_24XX)
761 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
764 u32 isr_saved, level_mask = 0;
766 isr_saved = isr = __raw_readl(isr_reg);
768 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
771 if (cpu_is_omap24xx())
773 __raw_readl(bank->base +
774 OMAP24XX_GPIO_LEVELDETECT0) |
775 __raw_readl(bank->base +
776 OMAP24XX_GPIO_LEVELDETECT1);
778 /* clear edge sensitive interrupts before handler(s) are
779 called so that we don't miss any interrupt occurred while
781 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
782 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
783 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
785 /* if there is only edge sensitive GPIO pin interrupts
786 configured, we could unmask GPIO bank interrupt immediately */
788 desc->chip->unmask(irq);
793 gpio_irq = bank->virtual_irq_start;
794 for (; isr != 0; isr >>= 1, gpio_irq++) {
798 d = irq_desc + gpio_irq;
799 desc_handle_irq(gpio_irq, d, regs);
802 if (cpu_is_omap24xx()) {
803 /* clear level sensitive interrupts after handler(s) */
804 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
805 _clear_gpio_irqbank(bank, isr_saved & level_mask);
806 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
809 /* if bank has any level sensitive GPIO pin interrupt
810 configured, we must unmask the bank interrupt only after
811 handler(s) are executed in order to avoid spurious bank
814 desc->chip->unmask(irq);
818 static void gpio_ack_irq(unsigned int irq)
820 unsigned int gpio = irq - IH_GPIO_BASE;
821 struct gpio_bank *bank = get_gpio_bank(gpio);
823 _clear_gpio_irqstatus(bank, gpio);
826 static void gpio_mask_irq(unsigned int irq)
828 unsigned int gpio = irq - IH_GPIO_BASE;
829 struct gpio_bank *bank = get_gpio_bank(gpio);
831 _set_gpio_irqenable(bank, gpio, 0);
834 static void gpio_unmask_irq(unsigned int irq)
836 unsigned int gpio = irq - IH_GPIO_BASE;
837 unsigned int gpio_idx = get_gpio_index(gpio);
838 struct gpio_bank *bank = get_gpio_bank(gpio);
840 _set_gpio_irqenable(bank, gpio_idx, 1);
843 static void mpuio_ack_irq(unsigned int irq)
845 /* The ISR is reset automatically, so do nothing here. */
848 static void mpuio_mask_irq(unsigned int irq)
850 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
851 struct gpio_bank *bank = get_gpio_bank(gpio);
853 _set_gpio_irqenable(bank, gpio, 0);
856 static void mpuio_unmask_irq(unsigned int irq)
858 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
859 struct gpio_bank *bank = get_gpio_bank(gpio);
861 _set_gpio_irqenable(bank, gpio, 1);
864 static struct irqchip gpio_irq_chip = {
866 .mask = gpio_mask_irq,
867 .unmask = gpio_unmask_irq,
868 .set_type = gpio_irq_type,
869 .set_wake = gpio_wake_enable,
872 static struct irqchip mpuio_irq_chip = {
873 .ack = mpuio_ack_irq,
874 .mask = mpuio_mask_irq,
875 .unmask = mpuio_unmask_irq
878 static int initialized;
879 static struct clk * gpio_ick;
880 static struct clk * gpio_fck;
882 static int __init _omap_gpio_init(void)
885 struct gpio_bank *bank;
889 if (cpu_is_omap15xx()) {
890 gpio_ick = clk_get(NULL, "arm_gpio_ck");
891 if (IS_ERR(gpio_ick))
892 printk("Could not get arm_gpio_ck\n");
894 clk_enable(gpio_ick);
896 if (cpu_is_omap24xx()) {
897 gpio_ick = clk_get(NULL, "gpios_ick");
898 if (IS_ERR(gpio_ick))
899 printk("Could not get gpios_ick\n");
901 clk_enable(gpio_ick);
902 gpio_fck = clk_get(NULL, "gpios_fck");
903 if (IS_ERR(gpio_ick))
904 printk("Could not get gpios_fck\n");
906 clk_enable(gpio_fck);
909 #ifdef CONFIG_ARCH_OMAP15XX
910 if (cpu_is_omap15xx()) {
911 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
913 gpio_bank = gpio_bank_1510;
916 #if defined(CONFIG_ARCH_OMAP16XX)
917 if (cpu_is_omap16xx()) {
921 gpio_bank = gpio_bank_1610;
922 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
923 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
924 (rev >> 4) & 0x0f, rev & 0x0f);
927 #ifdef CONFIG_ARCH_OMAP730
928 if (cpu_is_omap730()) {
929 printk(KERN_INFO "OMAP730 GPIO hardware\n");
931 gpio_bank = gpio_bank_730;
934 #ifdef CONFIG_ARCH_OMAP24XX
935 if (cpu_is_omap24xx()) {
939 gpio_bank = gpio_bank_24xx;
940 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
941 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
942 (rev >> 4) & 0x0f, rev & 0x0f);
945 for (i = 0; i < gpio_bank_count; i++) {
946 int j, gpio_count = 16;
948 bank = &gpio_bank[i];
949 bank->reserved_map = 0;
950 bank->base = IO_ADDRESS(bank->base);
951 spin_lock_init(&bank->lock);
952 if (bank->method == METHOD_MPUIO) {
953 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
955 #ifdef CONFIG_ARCH_OMAP15XX
956 if (bank->method == METHOD_GPIO_1510) {
957 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
958 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
961 #if defined(CONFIG_ARCH_OMAP16XX)
962 if (bank->method == METHOD_GPIO_1610) {
963 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
964 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
965 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
968 #ifdef CONFIG_ARCH_OMAP730
969 if (bank->method == METHOD_GPIO_730) {
970 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
971 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
973 gpio_count = 32; /* 730 has 32-bit GPIOs */
976 #ifdef CONFIG_ARCH_OMAP24XX
977 if (bank->method == METHOD_GPIO_24XX) {
978 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
979 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
984 for (j = bank->virtual_irq_start;
985 j < bank->virtual_irq_start + gpio_count; j++) {
986 if (bank->method == METHOD_MPUIO)
987 set_irq_chip(j, &mpuio_irq_chip);
989 set_irq_chip(j, &gpio_irq_chip);
990 set_irq_handler(j, do_simple_IRQ);
991 set_irq_flags(j, IRQF_VALID);
993 set_irq_chained_handler(bank->irq, gpio_irq_handler);
994 set_irq_data(bank->irq, bank);
997 /* Enable system clock for GPIO module.
998 * The CAM_CLK_CTRL *is* really the right place. */
999 if (cpu_is_omap16xx())
1000 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1005 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1006 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1010 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1013 for (i = 0; i < gpio_bank_count; i++) {
1014 struct gpio_bank *bank = &gpio_bank[i];
1015 void __iomem *wake_status;
1016 void __iomem *wake_clear;
1017 void __iomem *wake_set;
1019 switch (bank->method) {
1020 case METHOD_GPIO_1610:
1021 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1022 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1023 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1025 case METHOD_GPIO_24XX:
1026 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1027 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1028 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1034 spin_lock(&bank->lock);
1035 bank->saved_wakeup = __raw_readl(wake_status);
1036 __raw_writel(0xffffffff, wake_clear);
1037 __raw_writel(bank->suspend_wakeup, wake_set);
1038 spin_unlock(&bank->lock);
1044 static int omap_gpio_resume(struct sys_device *dev)
1048 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1051 for (i = 0; i < gpio_bank_count; i++) {
1052 struct gpio_bank *bank = &gpio_bank[i];
1053 void __iomem *wake_clear;
1054 void __iomem *wake_set;
1056 switch (bank->method) {
1057 case METHOD_GPIO_1610:
1058 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1059 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1061 case METHOD_GPIO_24XX:
1062 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1063 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1069 spin_lock(&bank->lock);
1070 __raw_writel(0xffffffff, wake_clear);
1071 __raw_writel(bank->saved_wakeup, wake_set);
1072 spin_unlock(&bank->lock);
1078 static struct sysdev_class omap_gpio_sysclass = {
1079 set_kset_name("gpio"),
1080 .suspend = omap_gpio_suspend,
1081 .resume = omap_gpio_resume,
1084 static struct sys_device omap_gpio_device = {
1086 .cls = &omap_gpio_sysclass,
1091 * This may get called early from board specific init
1092 * for boards that have interrupts routed via FPGA.
1094 int omap_gpio_init(void)
1097 return _omap_gpio_init();
1102 static int __init omap_gpio_sysinit(void)
1107 ret = _omap_gpio_init();
1109 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1110 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1112 ret = sysdev_class_register(&omap_gpio_sysclass);
1114 ret = sysdev_register(&omap_gpio_device);
1122 EXPORT_SYMBOL(omap_request_gpio);
1123 EXPORT_SYMBOL(omap_free_gpio);
1124 EXPORT_SYMBOL(omap_set_gpio_direction);
1125 EXPORT_SYMBOL(omap_set_gpio_dataout);
1126 EXPORT_SYMBOL(omap_get_gpio_datain);
1128 arch_initcall(omap_gpio_sysinit);