2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_CTRL 0x0030
105 #define OMAP24XX_GPIO_OE 0x0034
106 #define OMAP24XX_GPIO_DATAIN 0x0038
107 #define OMAP24XX_GPIO_DATAOUT 0x003c
108 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
109 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
110 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
111 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
112 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
113 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
122 * omap34xx specific GPIO registers
125 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
126 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
127 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
128 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
129 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
130 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
132 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
137 u16 virtual_irq_start;
139 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
143 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 u32 non_wakeup_gpios;
145 u32 enabled_non_wakeup_gpios;
148 u32 saved_fallingdetect;
149 u32 saved_risingdetect;
153 struct gpio_chip chip;
157 #define METHOD_MPUIO 0
158 #define METHOD_GPIO_1510 1
159 #define METHOD_GPIO_1610 2
160 #define METHOD_GPIO_730 3
161 #define METHOD_GPIO_24XX 4
163 #ifdef CONFIG_ARCH_OMAP16XX
164 static struct gpio_bank gpio_bank_1610[5] = {
165 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
166 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
173 #ifdef CONFIG_ARCH_OMAP15XX
174 static struct gpio_bank gpio_bank_1510[2] = {
175 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
176 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
180 #ifdef CONFIG_ARCH_OMAP730
181 static struct gpio_bank gpio_bank_730[7] = {
182 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
183 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
184 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
185 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
186 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
187 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
188 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
192 #ifdef CONFIG_ARCH_OMAP24XX
194 static struct gpio_bank gpio_bank_242x[4] = {
195 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
201 static struct gpio_bank gpio_bank_243x[5] = {
202 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
211 #ifdef CONFIG_ARCH_OMAP34XX
212 static struct gpio_bank gpio_bank_34xx[6] = {
213 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
223 static struct gpio_bank *gpio_bank;
224 static int gpio_bank_count;
226 static inline struct gpio_bank *get_gpio_bank(int gpio)
228 if (cpu_is_omap15xx()) {
229 if (OMAP_GPIO_IS_MPUIO(gpio))
230 return &gpio_bank[0];
231 return &gpio_bank[1];
233 if (cpu_is_omap16xx()) {
234 if (OMAP_GPIO_IS_MPUIO(gpio))
235 return &gpio_bank[0];
236 return &gpio_bank[1 + (gpio >> 4)];
238 if (cpu_is_omap730()) {
239 if (OMAP_GPIO_IS_MPUIO(gpio))
240 return &gpio_bank[0];
241 return &gpio_bank[1 + (gpio >> 5)];
243 if (cpu_is_omap24xx())
244 return &gpio_bank[gpio >> 5];
245 if (cpu_is_omap34xx())
246 return &gpio_bank[gpio >> 5];
249 static inline int get_gpio_index(int gpio)
251 if (cpu_is_omap730())
253 if (cpu_is_omap24xx())
255 if (cpu_is_omap34xx())
260 static inline int gpio_valid(int gpio)
264 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
265 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
269 if (cpu_is_omap15xx() && gpio < 16)
271 if ((cpu_is_omap16xx()) && gpio < 64)
273 if (cpu_is_omap730() && gpio < 192)
275 if (cpu_is_omap24xx() && gpio < 128)
277 if (cpu_is_omap34xx() && gpio < 160)
282 static int check_gpio(int gpio)
284 if (unlikely(gpio_valid(gpio)) < 0) {
285 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
292 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
294 void __iomem *reg = bank->base;
297 switch (bank->method) {
298 #ifdef CONFIG_ARCH_OMAP1
300 reg += OMAP_MPUIO_IO_CNTL;
303 #ifdef CONFIG_ARCH_OMAP15XX
304 case METHOD_GPIO_1510:
305 reg += OMAP1510_GPIO_DIR_CONTROL;
308 #ifdef CONFIG_ARCH_OMAP16XX
309 case METHOD_GPIO_1610:
310 reg += OMAP1610_GPIO_DIRECTION;
313 #ifdef CONFIG_ARCH_OMAP730
314 case METHOD_GPIO_730:
315 reg += OMAP730_GPIO_DIR_CONTROL;
318 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
319 case METHOD_GPIO_24XX:
320 reg += OMAP24XX_GPIO_OE;
327 l = __raw_readl(reg);
332 __raw_writel(l, reg);
335 void omap_set_gpio_direction(int gpio, int is_input)
337 struct gpio_bank *bank;
340 if (check_gpio(gpio) < 0)
342 bank = get_gpio_bank(gpio);
343 spin_lock_irqsave(&bank->lock, flags);
344 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
345 spin_unlock_irqrestore(&bank->lock, flags);
348 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
350 void __iomem *reg = bank->base;
353 switch (bank->method) {
354 #ifdef CONFIG_ARCH_OMAP1
356 reg += OMAP_MPUIO_OUTPUT;
357 l = __raw_readl(reg);
364 #ifdef CONFIG_ARCH_OMAP15XX
365 case METHOD_GPIO_1510:
366 reg += OMAP1510_GPIO_DATA_OUTPUT;
367 l = __raw_readl(reg);
374 #ifdef CONFIG_ARCH_OMAP16XX
375 case METHOD_GPIO_1610:
377 reg += OMAP1610_GPIO_SET_DATAOUT;
379 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
383 #ifdef CONFIG_ARCH_OMAP730
384 case METHOD_GPIO_730:
385 reg += OMAP730_GPIO_DATA_OUTPUT;
386 l = __raw_readl(reg);
393 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
394 case METHOD_GPIO_24XX:
396 reg += OMAP24XX_GPIO_SETDATAOUT;
398 reg += OMAP24XX_GPIO_CLEARDATAOUT;
406 __raw_writel(l, reg);
409 void omap_set_gpio_dataout(int gpio, int enable)
411 struct gpio_bank *bank;
414 if (check_gpio(gpio) < 0)
416 bank = get_gpio_bank(gpio);
417 spin_lock_irqsave(&bank->lock, flags);
418 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
419 spin_unlock_irqrestore(&bank->lock, flags);
422 int omap_get_gpio_datain(int gpio)
424 struct gpio_bank *bank;
427 if (check_gpio(gpio) < 0)
429 bank = get_gpio_bank(gpio);
431 switch (bank->method) {
432 #ifdef CONFIG_ARCH_OMAP1
434 reg += OMAP_MPUIO_INPUT_LATCH;
437 #ifdef CONFIG_ARCH_OMAP15XX
438 case METHOD_GPIO_1510:
439 reg += OMAP1510_GPIO_DATA_INPUT;
442 #ifdef CONFIG_ARCH_OMAP16XX
443 case METHOD_GPIO_1610:
444 reg += OMAP1610_GPIO_DATAIN;
447 #ifdef CONFIG_ARCH_OMAP730
448 case METHOD_GPIO_730:
449 reg += OMAP730_GPIO_DATA_INPUT;
452 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
453 case METHOD_GPIO_24XX:
454 reg += OMAP24XX_GPIO_DATAIN;
460 return (__raw_readl(reg)
461 & (1 << get_gpio_index(gpio))) != 0;
464 #define MOD_REG_BIT(reg, bit_mask, set) \
466 int l = __raw_readl(base + reg); \
467 if (set) l |= bit_mask; \
468 else l &= ~bit_mask; \
469 __raw_writel(l, base + reg); \
472 void omap_set_gpio_debounce(int gpio, int enable)
474 struct gpio_bank *bank;
476 u32 val, l = 1 << get_gpio_index(gpio);
478 if (cpu_class_is_omap1())
481 bank = get_gpio_bank(gpio);
484 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
485 val = __raw_readl(reg);
487 if (enable && !(val & l))
489 else if (!enable && val & l)
494 if (cpu_is_omap34xx())
495 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
497 __raw_writel(val, reg);
499 EXPORT_SYMBOL(omap_set_gpio_debounce);
501 void omap_set_gpio_debounce_time(int gpio, int enc_time)
503 struct gpio_bank *bank;
506 if (cpu_class_is_omap1())
509 bank = get_gpio_bank(gpio);
513 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
514 __raw_writel(enc_time, reg);
516 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
518 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
519 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
522 void __iomem *base = bank->base;
523 u32 gpio_bit = 1 << gpio;
525 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
526 trigger & IRQ_TYPE_LEVEL_LOW);
527 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
528 trigger & IRQ_TYPE_LEVEL_HIGH);
529 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
530 trigger & IRQ_TYPE_EDGE_RISING);
531 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
532 trigger & IRQ_TYPE_EDGE_FALLING);
534 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
536 __raw_writel(1 << gpio, bank->base
537 + OMAP24XX_GPIO_SETWKUENA);
539 __raw_writel(1 << gpio, bank->base
540 + OMAP24XX_GPIO_CLEARWKUENA);
543 bank->enabled_non_wakeup_gpios |= gpio_bit;
545 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
549 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
550 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
554 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
556 void __iomem *reg = bank->base;
559 switch (bank->method) {
560 #ifdef CONFIG_ARCH_OMAP1
562 reg += OMAP_MPUIO_GPIO_INT_EDGE;
563 l = __raw_readl(reg);
564 if (trigger & IRQ_TYPE_EDGE_RISING)
566 else if (trigger & IRQ_TYPE_EDGE_FALLING)
572 #ifdef CONFIG_ARCH_OMAP15XX
573 case METHOD_GPIO_1510:
574 reg += OMAP1510_GPIO_INT_CONTROL;
575 l = __raw_readl(reg);
576 if (trigger & IRQ_TYPE_EDGE_RISING)
578 else if (trigger & IRQ_TYPE_EDGE_FALLING)
584 #ifdef CONFIG_ARCH_OMAP16XX
585 case METHOD_GPIO_1610:
587 reg += OMAP1610_GPIO_EDGE_CTRL2;
589 reg += OMAP1610_GPIO_EDGE_CTRL1;
591 l = __raw_readl(reg);
592 l &= ~(3 << (gpio << 1));
593 if (trigger & IRQ_TYPE_EDGE_RISING)
594 l |= 2 << (gpio << 1);
595 if (trigger & IRQ_TYPE_EDGE_FALLING)
596 l |= 1 << (gpio << 1);
598 /* Enable wake-up during idle for dynamic tick */
599 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
601 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
604 #ifdef CONFIG_ARCH_OMAP730
605 case METHOD_GPIO_730:
606 reg += OMAP730_GPIO_INT_CONTROL;
607 l = __raw_readl(reg);
608 if (trigger & IRQ_TYPE_EDGE_RISING)
610 else if (trigger & IRQ_TYPE_EDGE_FALLING)
616 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
617 case METHOD_GPIO_24XX:
618 set_24xx_gpio_triggering(bank, gpio, trigger);
624 __raw_writel(l, reg);
630 static int gpio_irq_type(unsigned irq, unsigned type)
632 struct gpio_bank *bank;
637 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
638 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
640 gpio = irq - IH_GPIO_BASE;
642 if (check_gpio(gpio) < 0)
645 if (type & ~IRQ_TYPE_SENSE_MASK)
648 /* OMAP1 allows only only edge triggering */
649 if (!cpu_class_is_omap2()
650 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
653 bank = get_irq_chip_data(irq);
654 spin_lock_irqsave(&bank->lock, flags);
655 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
657 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
658 irq_desc[irq].status |= type;
660 spin_unlock_irqrestore(&bank->lock, flags);
662 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
663 __set_irq_handler_unlocked(irq, handle_level_irq);
664 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
665 __set_irq_handler_unlocked(irq, handle_edge_irq);
670 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
672 void __iomem *reg = bank->base;
674 switch (bank->method) {
675 #ifdef CONFIG_ARCH_OMAP1
677 /* MPUIO irqstatus is reset by reading the status register,
678 * so do nothing here */
681 #ifdef CONFIG_ARCH_OMAP15XX
682 case METHOD_GPIO_1510:
683 reg += OMAP1510_GPIO_INT_STATUS;
686 #ifdef CONFIG_ARCH_OMAP16XX
687 case METHOD_GPIO_1610:
688 reg += OMAP1610_GPIO_IRQSTATUS1;
691 #ifdef CONFIG_ARCH_OMAP730
692 case METHOD_GPIO_730:
693 reg += OMAP730_GPIO_INT_STATUS;
696 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
697 case METHOD_GPIO_24XX:
698 reg += OMAP24XX_GPIO_IRQSTATUS1;
705 __raw_writel(gpio_mask, reg);
707 /* Workaround for clearing DSP GPIO interrupts to allow retention */
708 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
709 if (cpu_is_omap24xx() || cpu_is_omap34xx())
710 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
714 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
716 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
719 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
721 void __iomem *reg = bank->base;
726 switch (bank->method) {
727 #ifdef CONFIG_ARCH_OMAP1
729 reg += OMAP_MPUIO_GPIO_MASKIT;
734 #ifdef CONFIG_ARCH_OMAP15XX
735 case METHOD_GPIO_1510:
736 reg += OMAP1510_GPIO_INT_MASK;
741 #ifdef CONFIG_ARCH_OMAP16XX
742 case METHOD_GPIO_1610:
743 reg += OMAP1610_GPIO_IRQENABLE1;
747 #ifdef CONFIG_ARCH_OMAP730
748 case METHOD_GPIO_730:
749 reg += OMAP730_GPIO_INT_MASK;
754 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
755 case METHOD_GPIO_24XX:
756 reg += OMAP24XX_GPIO_IRQENABLE1;
765 l = __raw_readl(reg);
772 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
774 void __iomem *reg = bank->base;
777 switch (bank->method) {
778 #ifdef CONFIG_ARCH_OMAP1
780 reg += OMAP_MPUIO_GPIO_MASKIT;
781 l = __raw_readl(reg);
788 #ifdef CONFIG_ARCH_OMAP15XX
789 case METHOD_GPIO_1510:
790 reg += OMAP1510_GPIO_INT_MASK;
791 l = __raw_readl(reg);
798 #ifdef CONFIG_ARCH_OMAP16XX
799 case METHOD_GPIO_1610:
801 reg += OMAP1610_GPIO_SET_IRQENABLE1;
803 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
807 #ifdef CONFIG_ARCH_OMAP730
808 case METHOD_GPIO_730:
809 reg += OMAP730_GPIO_INT_MASK;
810 l = __raw_readl(reg);
817 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
818 case METHOD_GPIO_24XX:
820 reg += OMAP24XX_GPIO_SETIRQENABLE1;
822 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
830 __raw_writel(l, reg);
833 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
835 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
839 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
840 * 1510 does not seem to have a wake-up register. If JTAG is connected
841 * to the target, system will wake up always on GPIO events. While
842 * system is running all registered GPIO interrupts need to have wake-up
843 * enabled. When system is suspended, only selected GPIO interrupts need
844 * to have wake-up enabled.
846 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
850 switch (bank->method) {
851 #ifdef CONFIG_ARCH_OMAP16XX
853 case METHOD_GPIO_1610:
854 spin_lock_irqsave(&bank->lock, flags);
856 bank->suspend_wakeup |= (1 << gpio);
857 enable_irq_wake(bank->irq);
859 disable_irq_wake(bank->irq);
860 bank->suspend_wakeup &= ~(1 << gpio);
862 spin_unlock_irqrestore(&bank->lock, flags);
865 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
866 case METHOD_GPIO_24XX:
867 if (bank->non_wakeup_gpios & (1 << gpio)) {
868 printk(KERN_ERR "Unable to modify wakeup on "
869 "non-wakeup GPIO%d\n",
870 (bank - gpio_bank) * 32 + gpio);
873 spin_lock_irqsave(&bank->lock, flags);
875 bank->suspend_wakeup |= (1 << gpio);
876 enable_irq_wake(bank->irq);
878 disable_irq_wake(bank->irq);
879 bank->suspend_wakeup &= ~(1 << gpio);
881 spin_unlock_irqrestore(&bank->lock, flags);
885 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
891 static void _reset_gpio(struct gpio_bank *bank, int gpio)
893 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
894 _set_gpio_irqenable(bank, gpio, 0);
895 _clear_gpio_irqstatus(bank, gpio);
896 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
899 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
900 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
902 unsigned int gpio = irq - IH_GPIO_BASE;
903 struct gpio_bank *bank;
906 if (check_gpio(gpio) < 0)
908 bank = get_irq_chip_data(irq);
909 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
914 int omap_request_gpio(int gpio)
916 struct gpio_bank *bank;
920 if (check_gpio(gpio) < 0)
923 status = gpio_request(gpio, NULL);
927 bank = get_gpio_bank(gpio);
928 spin_lock_irqsave(&bank->lock, flags);
930 /* Set trigger to none. You need to enable the desired trigger with
931 * request_irq() or set_irq_type().
933 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
935 #ifdef CONFIG_ARCH_OMAP15XX
936 if (bank->method == METHOD_GPIO_1510) {
939 /* Claim the pin for MPU */
940 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
941 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
944 spin_unlock_irqrestore(&bank->lock, flags);
949 void omap_free_gpio(int gpio)
951 struct gpio_bank *bank;
954 if (check_gpio(gpio) < 0)
956 bank = get_gpio_bank(gpio);
957 spin_lock_irqsave(&bank->lock, flags);
958 if (unlikely(!gpiochip_is_requested(&bank->chip,
959 get_gpio_index(gpio)))) {
960 spin_unlock_irqrestore(&bank->lock, flags);
961 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
965 #ifdef CONFIG_ARCH_OMAP16XX
966 if (bank->method == METHOD_GPIO_1610) {
967 /* Disable wake-up during idle for dynamic tick */
968 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
969 __raw_writel(1 << get_gpio_index(gpio), reg);
972 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
973 if (bank->method == METHOD_GPIO_24XX) {
974 /* Disable wake-up during idle for dynamic tick */
975 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
976 __raw_writel(1 << get_gpio_index(gpio), reg);
979 _reset_gpio(bank, gpio);
980 spin_unlock_irqrestore(&bank->lock, flags);
985 * We need to unmask the GPIO bank interrupt as soon as possible to
986 * avoid missing GPIO interrupts for other lines in the bank.
987 * Then we need to mask-read-clear-unmask the triggered GPIO lines
988 * in the bank to avoid missing nested interrupts for a GPIO line.
989 * If we wait to unmask individual GPIO lines in the bank after the
990 * line's interrupt handler has been run, we may miss some nested
993 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
995 void __iomem *isr_reg = NULL;
997 unsigned int gpio_irq;
998 struct gpio_bank *bank;
1002 desc->chip->ack(irq);
1004 bank = get_irq_data(irq);
1005 #ifdef CONFIG_ARCH_OMAP1
1006 if (bank->method == METHOD_MPUIO)
1007 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1009 #ifdef CONFIG_ARCH_OMAP15XX
1010 if (bank->method == METHOD_GPIO_1510)
1011 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1013 #if defined(CONFIG_ARCH_OMAP16XX)
1014 if (bank->method == METHOD_GPIO_1610)
1015 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1017 #ifdef CONFIG_ARCH_OMAP730
1018 if (bank->method == METHOD_GPIO_730)
1019 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1021 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1022 if (bank->method == METHOD_GPIO_24XX)
1023 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1026 u32 isr_saved, level_mask = 0;
1029 enabled = _get_gpio_irqbank_mask(bank);
1030 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1032 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1035 if (cpu_class_is_omap2()) {
1036 level_mask = bank->level_mask & enabled;
1039 /* clear edge sensitive interrupts before handler(s) are
1040 called so that we don't miss any interrupt occurred while
1042 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1043 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1044 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1046 /* if there is only edge sensitive GPIO pin interrupts
1047 configured, we could unmask GPIO bank interrupt immediately */
1048 if (!level_mask && !unmasked) {
1050 desc->chip->unmask(irq);
1058 gpio_irq = bank->virtual_irq_start;
1059 for (; isr != 0; isr >>= 1, gpio_irq++) {
1063 generic_handle_irq(gpio_irq);
1066 /* if bank has any level sensitive GPIO pin interrupt
1067 configured, we must unmask the bank interrupt only after
1068 handler(s) are executed in order to avoid spurious bank
1071 desc->chip->unmask(irq);
1075 static void gpio_irq_shutdown(unsigned int irq)
1077 unsigned int gpio = irq - IH_GPIO_BASE;
1078 struct gpio_bank *bank = get_irq_chip_data(irq);
1080 _reset_gpio(bank, gpio);
1083 static void gpio_ack_irq(unsigned int irq)
1085 unsigned int gpio = irq - IH_GPIO_BASE;
1086 struct gpio_bank *bank = get_irq_chip_data(irq);
1088 _clear_gpio_irqstatus(bank, gpio);
1091 static void gpio_mask_irq(unsigned int irq)
1093 unsigned int gpio = irq - IH_GPIO_BASE;
1094 struct gpio_bank *bank = get_irq_chip_data(irq);
1096 _set_gpio_irqenable(bank, gpio, 0);
1099 static void gpio_unmask_irq(unsigned int irq)
1101 unsigned int gpio = irq - IH_GPIO_BASE;
1102 struct gpio_bank *bank = get_irq_chip_data(irq);
1103 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1105 /* For level-triggered GPIOs, the clearing must be done after
1106 * the HW source is cleared, thus after the handler has run */
1107 if (bank->level_mask & irq_mask) {
1108 _set_gpio_irqenable(bank, gpio, 0);
1109 _clear_gpio_irqstatus(bank, gpio);
1112 _set_gpio_irqenable(bank, gpio, 1);
1115 static struct irq_chip gpio_irq_chip = {
1117 .shutdown = gpio_irq_shutdown,
1118 .ack = gpio_ack_irq,
1119 .mask = gpio_mask_irq,
1120 .unmask = gpio_unmask_irq,
1121 .set_type = gpio_irq_type,
1122 .set_wake = gpio_wake_enable,
1125 /*---------------------------------------------------------------------*/
1127 #ifdef CONFIG_ARCH_OMAP1
1129 /* MPUIO uses the always-on 32k clock */
1131 static void mpuio_ack_irq(unsigned int irq)
1133 /* The ISR is reset automatically, so do nothing here. */
1136 static void mpuio_mask_irq(unsigned int irq)
1138 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1139 struct gpio_bank *bank = get_irq_chip_data(irq);
1141 _set_gpio_irqenable(bank, gpio, 0);
1144 static void mpuio_unmask_irq(unsigned int irq)
1146 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1147 struct gpio_bank *bank = get_irq_chip_data(irq);
1149 _set_gpio_irqenable(bank, gpio, 1);
1152 static struct irq_chip mpuio_irq_chip = {
1154 .ack = mpuio_ack_irq,
1155 .mask = mpuio_mask_irq,
1156 .unmask = mpuio_unmask_irq,
1157 .set_type = gpio_irq_type,
1158 #ifdef CONFIG_ARCH_OMAP16XX
1159 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1160 .set_wake = gpio_wake_enable,
1165 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1168 #ifdef CONFIG_ARCH_OMAP16XX
1170 #include <linux/platform_device.h>
1172 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1174 struct gpio_bank *bank = platform_get_drvdata(pdev);
1175 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1176 unsigned long flags;
1178 spin_lock_irqsave(&bank->lock, flags);
1179 bank->saved_wakeup = __raw_readl(mask_reg);
1180 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1181 spin_unlock_irqrestore(&bank->lock, flags);
1186 static int omap_mpuio_resume_early(struct platform_device *pdev)
1188 struct gpio_bank *bank = platform_get_drvdata(pdev);
1189 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1190 unsigned long flags;
1192 spin_lock_irqsave(&bank->lock, flags);
1193 __raw_writel(bank->saved_wakeup, mask_reg);
1194 spin_unlock_irqrestore(&bank->lock, flags);
1199 /* use platform_driver for this, now that there's no longer any
1200 * point to sys_device (other than not disturbing old code).
1202 static struct platform_driver omap_mpuio_driver = {
1203 .suspend_late = omap_mpuio_suspend_late,
1204 .resume_early = omap_mpuio_resume_early,
1210 static struct platform_device omap_mpuio_device = {
1214 .driver = &omap_mpuio_driver.driver,
1216 /* could list the /proc/iomem resources */
1219 static inline void mpuio_init(void)
1221 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1223 if (platform_driver_register(&omap_mpuio_driver) == 0)
1224 (void) platform_device_register(&omap_mpuio_device);
1228 static inline void mpuio_init(void) {}
1233 extern struct irq_chip mpuio_irq_chip;
1235 #define bank_is_mpuio(bank) 0
1236 static inline void mpuio_init(void) {}
1240 /*---------------------------------------------------------------------*/
1242 /* REVISIT these are stupid implementations! replace by ones that
1243 * don't switch on METHOD_* and which mostly avoid spinlocks
1246 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1248 struct gpio_bank *bank;
1249 unsigned long flags;
1251 bank = container_of(chip, struct gpio_bank, chip);
1252 spin_lock_irqsave(&bank->lock, flags);
1253 _set_gpio_direction(bank, offset, 1);
1254 spin_unlock_irqrestore(&bank->lock, flags);
1258 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1260 return omap_get_gpio_datain(chip->base + offset);
1263 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1265 struct gpio_bank *bank;
1266 unsigned long flags;
1268 bank = container_of(chip, struct gpio_bank, chip);
1269 spin_lock_irqsave(&bank->lock, flags);
1270 _set_gpio_dataout(bank, offset, value);
1271 _set_gpio_direction(bank, offset, 0);
1272 spin_unlock_irqrestore(&bank->lock, flags);
1276 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1278 struct gpio_bank *bank;
1279 unsigned long flags;
1281 bank = container_of(chip, struct gpio_bank, chip);
1282 spin_lock_irqsave(&bank->lock, flags);
1283 _set_gpio_dataout(bank, offset, value);
1284 spin_unlock_irqrestore(&bank->lock, flags);
1287 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1289 struct gpio_bank *bank;
1291 bank = container_of(chip, struct gpio_bank, chip);
1292 return bank->virtual_irq_start + offset;
1295 /*---------------------------------------------------------------------*/
1297 static int initialized;
1298 #if !defined(CONFIG_ARCH_OMAP3)
1299 static struct clk * gpio_ick;
1302 #if defined(CONFIG_ARCH_OMAP2)
1303 static struct clk * gpio_fck;
1306 #if defined(CONFIG_ARCH_OMAP2430)
1307 static struct clk * gpio5_ick;
1308 static struct clk * gpio5_fck;
1311 #if defined(CONFIG_ARCH_OMAP3)
1312 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1315 /* This lock class tells lockdep that GPIO irqs are in a different
1316 * category than their parents, so it won't report false recursion.
1318 static struct lock_class_key gpio_lock_class;
1320 static int __init _omap_gpio_init(void)
1324 struct gpio_bank *bank;
1329 #if defined(CONFIG_ARCH_OMAP1)
1330 if (cpu_is_omap15xx()) {
1331 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1332 if (IS_ERR(gpio_ick))
1333 printk("Could not get arm_gpio_ck\n");
1335 clk_enable(gpio_ick);
1338 #if defined(CONFIG_ARCH_OMAP2)
1339 if (cpu_class_is_omap2()) {
1340 gpio_ick = clk_get(NULL, "gpios_ick");
1341 if (IS_ERR(gpio_ick))
1342 printk("Could not get gpios_ick\n");
1344 clk_enable(gpio_ick);
1345 gpio_fck = clk_get(NULL, "gpios_fck");
1346 if (IS_ERR(gpio_fck))
1347 printk("Could not get gpios_fck\n");
1349 clk_enable(gpio_fck);
1352 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1354 #if defined(CONFIG_ARCH_OMAP2430)
1355 if (cpu_is_omap2430()) {
1356 gpio5_ick = clk_get(NULL, "gpio5_ick");
1357 if (IS_ERR(gpio5_ick))
1358 printk("Could not get gpio5_ick\n");
1360 clk_enable(gpio5_ick);
1361 gpio5_fck = clk_get(NULL, "gpio5_fck");
1362 if (IS_ERR(gpio5_fck))
1363 printk("Could not get gpio5_fck\n");
1365 clk_enable(gpio5_fck);
1371 #if defined(CONFIG_ARCH_OMAP3)
1372 if (cpu_is_omap34xx()) {
1373 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1374 sprintf(clk_name, "gpio%d_ick", i + 1);
1375 gpio_iclks[i] = clk_get(NULL, clk_name);
1376 if (IS_ERR(gpio_iclks[i]))
1377 printk(KERN_ERR "Could not get %s\n", clk_name);
1379 clk_enable(gpio_iclks[i]);
1385 #ifdef CONFIG_ARCH_OMAP15XX
1386 if (cpu_is_omap15xx()) {
1387 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1388 gpio_bank_count = 2;
1389 gpio_bank = gpio_bank_1510;
1392 #if defined(CONFIG_ARCH_OMAP16XX)
1393 if (cpu_is_omap16xx()) {
1396 gpio_bank_count = 5;
1397 gpio_bank = gpio_bank_1610;
1398 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1399 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1400 (rev >> 4) & 0x0f, rev & 0x0f);
1403 #ifdef CONFIG_ARCH_OMAP730
1404 if (cpu_is_omap730()) {
1405 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1406 gpio_bank_count = 7;
1407 gpio_bank = gpio_bank_730;
1411 #ifdef CONFIG_ARCH_OMAP24XX
1412 if (cpu_is_omap242x()) {
1415 gpio_bank_count = 4;
1416 gpio_bank = gpio_bank_242x;
1417 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1418 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1419 (rev >> 4) & 0x0f, rev & 0x0f);
1421 if (cpu_is_omap243x()) {
1424 gpio_bank_count = 5;
1425 gpio_bank = gpio_bank_243x;
1426 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1427 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1428 (rev >> 4) & 0x0f, rev & 0x0f);
1431 #ifdef CONFIG_ARCH_OMAP34XX
1432 if (cpu_is_omap34xx()) {
1435 gpio_bank_count = OMAP34XX_NR_GPIOS;
1436 gpio_bank = gpio_bank_34xx;
1437 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1438 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1439 (rev >> 4) & 0x0f, rev & 0x0f);
1442 for (i = 0; i < gpio_bank_count; i++) {
1443 int j, gpio_count = 16;
1445 bank = &gpio_bank[i];
1446 spin_lock_init(&bank->lock);
1447 if (bank_is_mpuio(bank))
1448 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1449 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1450 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1451 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1453 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1454 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1455 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1456 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1458 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1459 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1460 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1462 gpio_count = 32; /* 730 has 32-bit GPIOs */
1465 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1466 if (bank->method == METHOD_GPIO_24XX) {
1467 static const u32 non_wakeup_gpios[] = {
1468 0xe203ffc0, 0x08700040
1471 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1472 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1473 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1475 /* Initialize interface clock ungated, module enabled */
1476 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1477 if (i < ARRAY_SIZE(non_wakeup_gpios))
1478 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1483 /* REVISIT eventually switch from OMAP-specific gpio structs
1484 * over to the generic ones
1486 bank->chip.direction_input = gpio_input;
1487 bank->chip.get = gpio_get;
1488 bank->chip.direction_output = gpio_output;
1489 bank->chip.set = gpio_set;
1490 bank->chip.to_irq = gpio_2irq;
1491 if (bank_is_mpuio(bank)) {
1492 bank->chip.label = "mpuio";
1493 #ifdef CONFIG_ARCH_OMAP16XX
1494 bank->chip.dev = &omap_mpuio_device.dev;
1496 bank->chip.base = OMAP_MPUIO(0);
1498 bank->chip.label = "gpio";
1499 bank->chip.base = gpio;
1502 bank->chip.ngpio = gpio_count;
1504 gpiochip_add(&bank->chip);
1506 for (j = bank->virtual_irq_start;
1507 j < bank->virtual_irq_start + gpio_count; j++) {
1508 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1509 set_irq_chip_data(j, bank);
1510 if (bank_is_mpuio(bank))
1511 set_irq_chip(j, &mpuio_irq_chip);
1513 set_irq_chip(j, &gpio_irq_chip);
1514 set_irq_handler(j, handle_simple_irq);
1515 set_irq_flags(j, IRQF_VALID);
1517 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1518 set_irq_data(bank->irq, bank);
1520 if (cpu_is_omap34xx()) {
1521 sprintf(clk_name, "gpio%d_dbck", i + 1);
1522 bank->dbck = clk_get(NULL, clk_name);
1523 if (IS_ERR(bank->dbck))
1524 printk(KERN_ERR "Could not get %s\n", clk_name);
1528 /* Enable system clock for GPIO module.
1529 * The CAM_CLK_CTRL *is* really the right place. */
1530 if (cpu_is_omap16xx())
1531 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1533 /* Enable autoidle for the OCP interface */
1534 if (cpu_is_omap24xx())
1535 omap_writel(1 << 0, 0x48019010);
1536 if (cpu_is_omap34xx())
1537 omap_writel(1 << 0, 0x48306814);
1542 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1543 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1547 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1550 for (i = 0; i < gpio_bank_count; i++) {
1551 struct gpio_bank *bank = &gpio_bank[i];
1552 void __iomem *wake_status;
1553 void __iomem *wake_clear;
1554 void __iomem *wake_set;
1555 unsigned long flags;
1557 switch (bank->method) {
1558 #ifdef CONFIG_ARCH_OMAP16XX
1559 case METHOD_GPIO_1610:
1560 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1561 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1562 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1565 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1566 case METHOD_GPIO_24XX:
1567 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1568 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1569 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1576 spin_lock_irqsave(&bank->lock, flags);
1577 bank->saved_wakeup = __raw_readl(wake_status);
1578 __raw_writel(0xffffffff, wake_clear);
1579 __raw_writel(bank->suspend_wakeup, wake_set);
1580 spin_unlock_irqrestore(&bank->lock, flags);
1586 static int omap_gpio_resume(struct sys_device *dev)
1590 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1593 for (i = 0; i < gpio_bank_count; i++) {
1594 struct gpio_bank *bank = &gpio_bank[i];
1595 void __iomem *wake_clear;
1596 void __iomem *wake_set;
1597 unsigned long flags;
1599 switch (bank->method) {
1600 #ifdef CONFIG_ARCH_OMAP16XX
1601 case METHOD_GPIO_1610:
1602 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1603 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1606 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1607 case METHOD_GPIO_24XX:
1608 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1609 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1616 spin_lock_irqsave(&bank->lock, flags);
1617 __raw_writel(0xffffffff, wake_clear);
1618 __raw_writel(bank->saved_wakeup, wake_set);
1619 spin_unlock_irqrestore(&bank->lock, flags);
1625 static struct sysdev_class omap_gpio_sysclass = {
1627 .suspend = omap_gpio_suspend,
1628 .resume = omap_gpio_resume,
1631 static struct sys_device omap_gpio_device = {
1633 .cls = &omap_gpio_sysclass,
1638 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1640 static int workaround_enabled;
1642 void omap2_gpio_prepare_for_retention(void)
1646 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1647 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1648 for (i = 0; i < gpio_bank_count; i++) {
1649 struct gpio_bank *bank = &gpio_bank[i];
1652 if (!(bank->enabled_non_wakeup_gpios))
1654 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1655 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1656 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1657 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1659 bank->saved_fallingdetect = l1;
1660 bank->saved_risingdetect = l2;
1661 l1 &= ~bank->enabled_non_wakeup_gpios;
1662 l2 &= ~bank->enabled_non_wakeup_gpios;
1663 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1664 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1665 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1670 workaround_enabled = 0;
1673 workaround_enabled = 1;
1676 void omap2_gpio_resume_after_retention(void)
1680 if (!workaround_enabled)
1682 for (i = 0; i < gpio_bank_count; i++) {
1683 struct gpio_bank *bank = &gpio_bank[i];
1686 if (!(bank->enabled_non_wakeup_gpios))
1688 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1689 __raw_writel(bank->saved_fallingdetect,
1690 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1691 __raw_writel(bank->saved_risingdetect,
1692 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1694 /* Check if any of the non-wakeup interrupt GPIOs have changed
1695 * state. If so, generate an IRQ by software. This is
1696 * horribly racy, but it's the best we can do to work around
1697 * this silicon bug. */
1698 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1699 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1701 l ^= bank->saved_datain;
1702 l &= bank->non_wakeup_gpios;
1705 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1706 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1707 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1708 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1709 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1710 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1711 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1721 * This may get called early from board specific init
1722 * for boards that have interrupts routed via FPGA.
1724 int __init omap_gpio_init(void)
1727 return _omap_gpio_init();
1732 static int __init omap_gpio_sysinit(void)
1737 ret = _omap_gpio_init();
1741 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1742 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1744 ret = sysdev_class_register(&omap_gpio_sysclass);
1746 ret = sysdev_register(&omap_gpio_device);
1754 EXPORT_SYMBOL(omap_request_gpio);
1755 EXPORT_SYMBOL(omap_free_gpio);
1756 EXPORT_SYMBOL(omap_set_gpio_direction);
1757 EXPORT_SYMBOL(omap_set_gpio_dataout);
1758 EXPORT_SYMBOL(omap_get_gpio_datain);
1760 arch_initcall(omap_gpio_sysinit);
1763 #ifdef CONFIG_DEBUG_FS
1765 #include <linux/debugfs.h>
1766 #include <linux/seq_file.h>
1768 static int gpio_is_input(struct gpio_bank *bank, int mask)
1770 void __iomem *reg = bank->base;
1772 switch (bank->method) {
1774 reg += OMAP_MPUIO_IO_CNTL;
1776 case METHOD_GPIO_1510:
1777 reg += OMAP1510_GPIO_DIR_CONTROL;
1779 case METHOD_GPIO_1610:
1780 reg += OMAP1610_GPIO_DIRECTION;
1782 case METHOD_GPIO_730:
1783 reg += OMAP730_GPIO_DIR_CONTROL;
1785 case METHOD_GPIO_24XX:
1786 reg += OMAP24XX_GPIO_OE;
1789 return __raw_readl(reg) & mask;
1793 static int dbg_gpio_show(struct seq_file *s, void *unused)
1795 unsigned i, j, gpio;
1797 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1798 struct gpio_bank *bank = gpio_bank + i;
1799 unsigned bankwidth = 16;
1802 if (bank_is_mpuio(bank))
1803 gpio = OMAP_MPUIO(0);
1804 else if (cpu_class_is_omap2() || cpu_is_omap730())
1807 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1808 unsigned irq, value, is_in, irqstat;
1811 label = gpiochip_is_requested(&bank->chip, j);
1815 irq = bank->virtual_irq_start + j;
1816 value = omap_get_gpio_datain(gpio);
1817 is_in = gpio_is_input(bank, mask);
1819 if (bank_is_mpuio(bank))
1820 seq_printf(s, "MPUIO %2d ", j);
1822 seq_printf(s, "GPIO %3d ", gpio);
1823 seq_printf(s, "(%10s): %s %s",
1825 is_in ? "in " : "out",
1826 value ? "hi" : "lo");
1828 /* FIXME for at least omap2, show pullup/pulldown state */
1830 irqstat = irq_desc[irq].status;
1831 if (is_in && ((bank->suspend_wakeup & mask)
1832 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1833 char *trigger = NULL;
1835 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1836 case IRQ_TYPE_EDGE_FALLING:
1837 trigger = "falling";
1839 case IRQ_TYPE_EDGE_RISING:
1842 case IRQ_TYPE_EDGE_BOTH:
1843 trigger = "bothedge";
1845 case IRQ_TYPE_LEVEL_LOW:
1848 case IRQ_TYPE_LEVEL_HIGH:
1855 seq_printf(s, ", irq-%d %-8s%s",
1857 (bank->suspend_wakeup & mask)
1860 seq_printf(s, "\n");
1863 if (bank_is_mpuio(bank)) {
1864 seq_printf(s, "\n");
1871 static int dbg_gpio_open(struct inode *inode, struct file *file)
1873 return single_open(file, dbg_gpio_show, &inode->i_private);
1876 static const struct file_operations debug_fops = {
1877 .open = dbg_gpio_open,
1879 .llseek = seq_lseek,
1880 .release = single_release,
1883 static int __init omap_gpio_debuginit(void)
1885 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1886 NULL, NULL, &debug_fops);
1889 late_initcall(omap_gpio_debuginit);