2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_CTRL 0x0030
105 #define OMAP24XX_GPIO_OE 0x0034
106 #define OMAP24XX_GPIO_DATAIN 0x0038
107 #define OMAP24XX_GPIO_DATAOUT 0x003c
108 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
109 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
110 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
111 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
112 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
113 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
122 * omap34xx specific GPIO registers
125 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
126 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
127 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
128 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
129 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
130 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
132 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
137 u16 virtual_irq_start;
139 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
143 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 u32 non_wakeup_gpios;
145 u32 enabled_non_wakeup_gpios;
148 u32 saved_fallingdetect;
149 u32 saved_risingdetect;
153 struct gpio_chip chip;
157 #define METHOD_MPUIO 0
158 #define METHOD_GPIO_1510 1
159 #define METHOD_GPIO_1610 2
160 #define METHOD_GPIO_730 3
161 #define METHOD_GPIO_24XX 4
163 #ifdef CONFIG_ARCH_OMAP16XX
164 static struct gpio_bank gpio_bank_1610[5] = {
165 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
166 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
173 #ifdef CONFIG_ARCH_OMAP15XX
174 static struct gpio_bank gpio_bank_1510[2] = {
175 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
176 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
180 #ifdef CONFIG_ARCH_OMAP730
181 static struct gpio_bank gpio_bank_730[7] = {
182 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
183 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
184 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
185 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
186 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
187 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
188 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
192 #ifdef CONFIG_ARCH_OMAP24XX
194 static struct gpio_bank gpio_bank_242x[4] = {
195 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
201 static struct gpio_bank gpio_bank_243x[5] = {
202 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
211 #ifdef CONFIG_ARCH_OMAP34XX
212 static struct gpio_bank gpio_bank_34xx[6] = {
213 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
223 static struct gpio_bank *gpio_bank;
224 static int gpio_bank_count;
226 static inline struct gpio_bank *get_gpio_bank(int gpio)
228 if (cpu_is_omap15xx()) {
229 if (OMAP_GPIO_IS_MPUIO(gpio))
230 return &gpio_bank[0];
231 return &gpio_bank[1];
233 if (cpu_is_omap16xx()) {
234 if (OMAP_GPIO_IS_MPUIO(gpio))
235 return &gpio_bank[0];
236 return &gpio_bank[1 + (gpio >> 4)];
238 if (cpu_is_omap730()) {
239 if (OMAP_GPIO_IS_MPUIO(gpio))
240 return &gpio_bank[0];
241 return &gpio_bank[1 + (gpio >> 5)];
243 if (cpu_is_omap24xx())
244 return &gpio_bank[gpio >> 5];
245 if (cpu_is_omap34xx())
246 return &gpio_bank[gpio >> 5];
251 static inline int get_gpio_index(int gpio)
253 if (cpu_is_omap730())
255 if (cpu_is_omap24xx())
257 if (cpu_is_omap34xx())
262 static inline int gpio_valid(int gpio)
266 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
267 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
271 if (cpu_is_omap15xx() && gpio < 16)
273 if ((cpu_is_omap16xx()) && gpio < 64)
275 if (cpu_is_omap730() && gpio < 192)
277 if (cpu_is_omap24xx() && gpio < 128)
279 if (cpu_is_omap34xx() && gpio < 160)
284 static int check_gpio(int gpio)
286 if (unlikely(gpio_valid(gpio)) < 0) {
287 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
294 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
296 void __iomem *reg = bank->base;
299 switch (bank->method) {
300 #ifdef CONFIG_ARCH_OMAP1
302 reg += OMAP_MPUIO_IO_CNTL;
305 #ifdef CONFIG_ARCH_OMAP15XX
306 case METHOD_GPIO_1510:
307 reg += OMAP1510_GPIO_DIR_CONTROL;
310 #ifdef CONFIG_ARCH_OMAP16XX
311 case METHOD_GPIO_1610:
312 reg += OMAP1610_GPIO_DIRECTION;
315 #ifdef CONFIG_ARCH_OMAP730
316 case METHOD_GPIO_730:
317 reg += OMAP730_GPIO_DIR_CONTROL;
320 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
321 case METHOD_GPIO_24XX:
322 reg += OMAP24XX_GPIO_OE;
329 l = __raw_readl(reg);
334 __raw_writel(l, reg);
337 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
339 void __iomem *reg = bank->base;
342 switch (bank->method) {
343 #ifdef CONFIG_ARCH_OMAP1
345 reg += OMAP_MPUIO_OUTPUT;
346 l = __raw_readl(reg);
353 #ifdef CONFIG_ARCH_OMAP15XX
354 case METHOD_GPIO_1510:
355 reg += OMAP1510_GPIO_DATA_OUTPUT;
356 l = __raw_readl(reg);
363 #ifdef CONFIG_ARCH_OMAP16XX
364 case METHOD_GPIO_1610:
366 reg += OMAP1610_GPIO_SET_DATAOUT;
368 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
372 #ifdef CONFIG_ARCH_OMAP730
373 case METHOD_GPIO_730:
374 reg += OMAP730_GPIO_DATA_OUTPUT;
375 l = __raw_readl(reg);
382 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
383 case METHOD_GPIO_24XX:
385 reg += OMAP24XX_GPIO_SETDATAOUT;
387 reg += OMAP24XX_GPIO_CLEARDATAOUT;
395 __raw_writel(l, reg);
398 static int __omap_get_gpio_datain(int gpio)
400 struct gpio_bank *bank;
403 if (check_gpio(gpio) < 0)
405 bank = get_gpio_bank(gpio);
407 switch (bank->method) {
408 #ifdef CONFIG_ARCH_OMAP1
410 reg += OMAP_MPUIO_INPUT_LATCH;
413 #ifdef CONFIG_ARCH_OMAP15XX
414 case METHOD_GPIO_1510:
415 reg += OMAP1510_GPIO_DATA_INPUT;
418 #ifdef CONFIG_ARCH_OMAP16XX
419 case METHOD_GPIO_1610:
420 reg += OMAP1610_GPIO_DATAIN;
423 #ifdef CONFIG_ARCH_OMAP730
424 case METHOD_GPIO_730:
425 reg += OMAP730_GPIO_DATA_INPUT;
428 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
429 case METHOD_GPIO_24XX:
430 reg += OMAP24XX_GPIO_DATAIN;
436 return (__raw_readl(reg)
437 & (1 << get_gpio_index(gpio))) != 0;
440 #define MOD_REG_BIT(reg, bit_mask, set) \
442 int l = __raw_readl(base + reg); \
443 if (set) l |= bit_mask; \
444 else l &= ~bit_mask; \
445 __raw_writel(l, base + reg); \
448 void omap_set_gpio_debounce(int gpio, int enable)
450 struct gpio_bank *bank;
453 u32 val, l = 1 << get_gpio_index(gpio);
455 if (cpu_class_is_omap1())
458 bank = get_gpio_bank(gpio);
460 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
462 spin_lock_irqsave(&bank->lock, flags);
463 val = __raw_readl(reg);
465 if (enable && !(val & l))
467 else if (!enable && (val & l))
472 if (cpu_is_omap34xx()) {
474 clk_enable(bank->dbck);
476 clk_disable(bank->dbck);
479 __raw_writel(val, reg);
481 spin_unlock_irqrestore(&bank->lock, flags);
483 EXPORT_SYMBOL(omap_set_gpio_debounce);
485 void omap_set_gpio_debounce_time(int gpio, int enc_time)
487 struct gpio_bank *bank;
490 if (cpu_class_is_omap1())
493 bank = get_gpio_bank(gpio);
497 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
498 __raw_writel(enc_time, reg);
500 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
502 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
503 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
506 void __iomem *base = bank->base;
507 u32 gpio_bit = 1 << gpio;
509 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
510 trigger & IRQ_TYPE_LEVEL_LOW);
511 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
512 trigger & IRQ_TYPE_LEVEL_HIGH);
513 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
514 trigger & IRQ_TYPE_EDGE_RISING);
515 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
516 trigger & IRQ_TYPE_EDGE_FALLING);
518 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
520 __raw_writel(1 << gpio, bank->base
521 + OMAP24XX_GPIO_SETWKUENA);
523 __raw_writel(1 << gpio, bank->base
524 + OMAP24XX_GPIO_CLEARWKUENA);
527 bank->enabled_non_wakeup_gpios |= gpio_bit;
529 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
533 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
534 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
538 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
540 void __iomem *reg = bank->base;
543 switch (bank->method) {
544 #ifdef CONFIG_ARCH_OMAP1
546 reg += OMAP_MPUIO_GPIO_INT_EDGE;
547 l = __raw_readl(reg);
548 if (trigger & IRQ_TYPE_EDGE_RISING)
550 else if (trigger & IRQ_TYPE_EDGE_FALLING)
556 #ifdef CONFIG_ARCH_OMAP15XX
557 case METHOD_GPIO_1510:
558 reg += OMAP1510_GPIO_INT_CONTROL;
559 l = __raw_readl(reg);
560 if (trigger & IRQ_TYPE_EDGE_RISING)
562 else if (trigger & IRQ_TYPE_EDGE_FALLING)
568 #ifdef CONFIG_ARCH_OMAP16XX
569 case METHOD_GPIO_1610:
571 reg += OMAP1610_GPIO_EDGE_CTRL2;
573 reg += OMAP1610_GPIO_EDGE_CTRL1;
575 l = __raw_readl(reg);
576 l &= ~(3 << (gpio << 1));
577 if (trigger & IRQ_TYPE_EDGE_RISING)
578 l |= 2 << (gpio << 1);
579 if (trigger & IRQ_TYPE_EDGE_FALLING)
580 l |= 1 << (gpio << 1);
582 /* Enable wake-up during idle for dynamic tick */
583 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
585 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
588 #ifdef CONFIG_ARCH_OMAP730
589 case METHOD_GPIO_730:
590 reg += OMAP730_GPIO_INT_CONTROL;
591 l = __raw_readl(reg);
592 if (trigger & IRQ_TYPE_EDGE_RISING)
594 else if (trigger & IRQ_TYPE_EDGE_FALLING)
600 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
601 case METHOD_GPIO_24XX:
602 set_24xx_gpio_triggering(bank, gpio, trigger);
608 __raw_writel(l, reg);
614 static int gpio_irq_type(unsigned irq, unsigned type)
616 struct gpio_bank *bank;
621 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
622 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
624 gpio = irq - IH_GPIO_BASE;
626 if (check_gpio(gpio) < 0)
629 if (type & ~IRQ_TYPE_SENSE_MASK)
632 /* OMAP1 allows only only edge triggering */
633 if (!cpu_class_is_omap2()
634 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
637 bank = get_irq_chip_data(irq);
638 spin_lock_irqsave(&bank->lock, flags);
639 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
641 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
642 irq_desc[irq].status |= type;
644 spin_unlock_irqrestore(&bank->lock, flags);
646 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
647 __set_irq_handler_unlocked(irq, handle_level_irq);
648 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
649 __set_irq_handler_unlocked(irq, handle_edge_irq);
654 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656 void __iomem *reg = bank->base;
658 switch (bank->method) {
659 #ifdef CONFIG_ARCH_OMAP1
661 /* MPUIO irqstatus is reset by reading the status register,
662 * so do nothing here */
665 #ifdef CONFIG_ARCH_OMAP15XX
666 case METHOD_GPIO_1510:
667 reg += OMAP1510_GPIO_INT_STATUS;
670 #ifdef CONFIG_ARCH_OMAP16XX
671 case METHOD_GPIO_1610:
672 reg += OMAP1610_GPIO_IRQSTATUS1;
675 #ifdef CONFIG_ARCH_OMAP730
676 case METHOD_GPIO_730:
677 reg += OMAP730_GPIO_INT_STATUS;
680 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
681 case METHOD_GPIO_24XX:
682 reg += OMAP24XX_GPIO_IRQSTATUS1;
689 __raw_writel(gpio_mask, reg);
691 /* Workaround for clearing DSP GPIO interrupts to allow retention */
692 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
693 if (cpu_is_omap24xx() || cpu_is_omap34xx())
694 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
698 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
700 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
703 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
705 void __iomem *reg = bank->base;
710 switch (bank->method) {
711 #ifdef CONFIG_ARCH_OMAP1
713 reg += OMAP_MPUIO_GPIO_MASKIT;
718 #ifdef CONFIG_ARCH_OMAP15XX
719 case METHOD_GPIO_1510:
720 reg += OMAP1510_GPIO_INT_MASK;
725 #ifdef CONFIG_ARCH_OMAP16XX
726 case METHOD_GPIO_1610:
727 reg += OMAP1610_GPIO_IRQENABLE1;
731 #ifdef CONFIG_ARCH_OMAP730
732 case METHOD_GPIO_730:
733 reg += OMAP730_GPIO_INT_MASK;
738 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
739 case METHOD_GPIO_24XX:
740 reg += OMAP24XX_GPIO_IRQENABLE1;
749 l = __raw_readl(reg);
756 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
758 void __iomem *reg = bank->base;
761 switch (bank->method) {
762 #ifdef CONFIG_ARCH_OMAP1
764 reg += OMAP_MPUIO_GPIO_MASKIT;
765 l = __raw_readl(reg);
772 #ifdef CONFIG_ARCH_OMAP15XX
773 case METHOD_GPIO_1510:
774 reg += OMAP1510_GPIO_INT_MASK;
775 l = __raw_readl(reg);
782 #ifdef CONFIG_ARCH_OMAP16XX
783 case METHOD_GPIO_1610:
785 reg += OMAP1610_GPIO_SET_IRQENABLE1;
787 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
791 #ifdef CONFIG_ARCH_OMAP730
792 case METHOD_GPIO_730:
793 reg += OMAP730_GPIO_INT_MASK;
794 l = __raw_readl(reg);
801 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
802 case METHOD_GPIO_24XX:
804 reg += OMAP24XX_GPIO_SETIRQENABLE1;
806 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
814 __raw_writel(l, reg);
817 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
819 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
823 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
824 * 1510 does not seem to have a wake-up register. If JTAG is connected
825 * to the target, system will wake up always on GPIO events. While
826 * system is running all registered GPIO interrupts need to have wake-up
827 * enabled. When system is suspended, only selected GPIO interrupts need
828 * to have wake-up enabled.
830 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
834 switch (bank->method) {
835 #ifdef CONFIG_ARCH_OMAP16XX
837 case METHOD_GPIO_1610:
838 spin_lock_irqsave(&bank->lock, flags);
840 bank->suspend_wakeup |= (1 << gpio);
841 enable_irq_wake(bank->irq);
843 disable_irq_wake(bank->irq);
844 bank->suspend_wakeup &= ~(1 << gpio);
846 spin_unlock_irqrestore(&bank->lock, flags);
849 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
850 case METHOD_GPIO_24XX:
851 if (bank->non_wakeup_gpios & (1 << gpio)) {
852 printk(KERN_ERR "Unable to modify wakeup on "
853 "non-wakeup GPIO%d\n",
854 (bank - gpio_bank) * 32 + gpio);
857 spin_lock_irqsave(&bank->lock, flags);
859 bank->suspend_wakeup |= (1 << gpio);
860 enable_irq_wake(bank->irq);
862 disable_irq_wake(bank->irq);
863 bank->suspend_wakeup &= ~(1 << gpio);
865 spin_unlock_irqrestore(&bank->lock, flags);
869 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
875 static void _reset_gpio(struct gpio_bank *bank, int gpio)
877 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
878 _set_gpio_irqenable(bank, gpio, 0);
879 _clear_gpio_irqstatus(bank, gpio);
880 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
883 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
884 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
886 unsigned int gpio = irq - IH_GPIO_BASE;
887 struct gpio_bank *bank;
890 if (check_gpio(gpio) < 0)
892 bank = get_irq_chip_data(irq);
893 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
898 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
900 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
903 spin_lock_irqsave(&bank->lock, flags);
905 /* Set trigger to none. You need to enable the desired trigger with
906 * request_irq() or set_irq_type().
908 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
910 #ifdef CONFIG_ARCH_OMAP15XX
911 if (bank->method == METHOD_GPIO_1510) {
914 /* Claim the pin for MPU */
915 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
916 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
919 spin_unlock_irqrestore(&bank->lock, flags);
924 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
926 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
929 spin_lock_irqsave(&bank->lock, flags);
930 #ifdef CONFIG_ARCH_OMAP16XX
931 if (bank->method == METHOD_GPIO_1610) {
932 /* Disable wake-up during idle for dynamic tick */
933 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
934 __raw_writel(1 << offset, reg);
937 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
938 if (bank->method == METHOD_GPIO_24XX) {
939 /* Disable wake-up during idle for dynamic tick */
940 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
941 __raw_writel(1 << offset, reg);
944 _reset_gpio(bank, bank->chip.base + offset);
945 spin_unlock_irqrestore(&bank->lock, flags);
949 * We need to unmask the GPIO bank interrupt as soon as possible to
950 * avoid missing GPIO interrupts for other lines in the bank.
951 * Then we need to mask-read-clear-unmask the triggered GPIO lines
952 * in the bank to avoid missing nested interrupts for a GPIO line.
953 * If we wait to unmask individual GPIO lines in the bank after the
954 * line's interrupt handler has been run, we may miss some nested
957 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
959 void __iomem *isr_reg = NULL;
961 unsigned int gpio_irq;
962 struct gpio_bank *bank;
966 desc->chip->ack(irq);
968 bank = get_irq_data(irq);
969 #ifdef CONFIG_ARCH_OMAP1
970 if (bank->method == METHOD_MPUIO)
971 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
973 #ifdef CONFIG_ARCH_OMAP15XX
974 if (bank->method == METHOD_GPIO_1510)
975 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
977 #if defined(CONFIG_ARCH_OMAP16XX)
978 if (bank->method == METHOD_GPIO_1610)
979 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
981 #ifdef CONFIG_ARCH_OMAP730
982 if (bank->method == METHOD_GPIO_730)
983 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
985 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
986 if (bank->method == METHOD_GPIO_24XX)
987 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
990 u32 isr_saved, level_mask = 0;
993 enabled = _get_gpio_irqbank_mask(bank);
994 isr_saved = isr = __raw_readl(isr_reg) & enabled;
996 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
999 if (cpu_class_is_omap2()) {
1000 level_mask = bank->level_mask & enabled;
1003 /* clear edge sensitive interrupts before handler(s) are
1004 called so that we don't miss any interrupt occurred while
1006 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1007 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1008 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1010 /* if there is only edge sensitive GPIO pin interrupts
1011 configured, we could unmask GPIO bank interrupt immediately */
1012 if (!level_mask && !unmasked) {
1014 desc->chip->unmask(irq);
1022 gpio_irq = bank->virtual_irq_start;
1023 for (; isr != 0; isr >>= 1, gpio_irq++) {
1027 generic_handle_irq(gpio_irq);
1030 /* if bank has any level sensitive GPIO pin interrupt
1031 configured, we must unmask the bank interrupt only after
1032 handler(s) are executed in order to avoid spurious bank
1035 desc->chip->unmask(irq);
1039 static void gpio_irq_shutdown(unsigned int irq)
1041 unsigned int gpio = irq - IH_GPIO_BASE;
1042 struct gpio_bank *bank = get_irq_chip_data(irq);
1044 _reset_gpio(bank, gpio);
1047 static void gpio_ack_irq(unsigned int irq)
1049 unsigned int gpio = irq - IH_GPIO_BASE;
1050 struct gpio_bank *bank = get_irq_chip_data(irq);
1052 _clear_gpio_irqstatus(bank, gpio);
1055 static void gpio_mask_irq(unsigned int irq)
1057 unsigned int gpio = irq - IH_GPIO_BASE;
1058 struct gpio_bank *bank = get_irq_chip_data(irq);
1060 _set_gpio_irqenable(bank, gpio, 0);
1063 static void gpio_unmask_irq(unsigned int irq)
1065 unsigned int gpio = irq - IH_GPIO_BASE;
1066 struct gpio_bank *bank = get_irq_chip_data(irq);
1067 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1069 /* For level-triggered GPIOs, the clearing must be done after
1070 * the HW source is cleared, thus after the handler has run */
1071 if (bank->level_mask & irq_mask) {
1072 _set_gpio_irqenable(bank, gpio, 0);
1073 _clear_gpio_irqstatus(bank, gpio);
1076 _set_gpio_irqenable(bank, gpio, 1);
1079 static struct irq_chip gpio_irq_chip = {
1081 .shutdown = gpio_irq_shutdown,
1082 .ack = gpio_ack_irq,
1083 .mask = gpio_mask_irq,
1084 .unmask = gpio_unmask_irq,
1085 .set_type = gpio_irq_type,
1086 .set_wake = gpio_wake_enable,
1089 /*---------------------------------------------------------------------*/
1091 #ifdef CONFIG_ARCH_OMAP1
1093 /* MPUIO uses the always-on 32k clock */
1095 static void mpuio_ack_irq(unsigned int irq)
1097 /* The ISR is reset automatically, so do nothing here. */
1100 static void mpuio_mask_irq(unsigned int irq)
1102 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1103 struct gpio_bank *bank = get_irq_chip_data(irq);
1105 _set_gpio_irqenable(bank, gpio, 0);
1108 static void mpuio_unmask_irq(unsigned int irq)
1110 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1111 struct gpio_bank *bank = get_irq_chip_data(irq);
1113 _set_gpio_irqenable(bank, gpio, 1);
1116 static struct irq_chip mpuio_irq_chip = {
1118 .ack = mpuio_ack_irq,
1119 .mask = mpuio_mask_irq,
1120 .unmask = mpuio_unmask_irq,
1121 .set_type = gpio_irq_type,
1122 #ifdef CONFIG_ARCH_OMAP16XX
1123 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1124 .set_wake = gpio_wake_enable,
1129 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1132 #ifdef CONFIG_ARCH_OMAP16XX
1134 #include <linux/platform_device.h>
1136 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1138 struct gpio_bank *bank = platform_get_drvdata(pdev);
1139 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1140 unsigned long flags;
1142 spin_lock_irqsave(&bank->lock, flags);
1143 bank->saved_wakeup = __raw_readl(mask_reg);
1144 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1145 spin_unlock_irqrestore(&bank->lock, flags);
1150 static int omap_mpuio_resume_early(struct platform_device *pdev)
1152 struct gpio_bank *bank = platform_get_drvdata(pdev);
1153 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1154 unsigned long flags;
1156 spin_lock_irqsave(&bank->lock, flags);
1157 __raw_writel(bank->saved_wakeup, mask_reg);
1158 spin_unlock_irqrestore(&bank->lock, flags);
1163 /* use platform_driver for this, now that there's no longer any
1164 * point to sys_device (other than not disturbing old code).
1166 static struct platform_driver omap_mpuio_driver = {
1167 .suspend_late = omap_mpuio_suspend_late,
1168 .resume_early = omap_mpuio_resume_early,
1174 static struct platform_device omap_mpuio_device = {
1178 .driver = &omap_mpuio_driver.driver,
1180 /* could list the /proc/iomem resources */
1183 static inline void mpuio_init(void)
1185 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1187 if (platform_driver_register(&omap_mpuio_driver) == 0)
1188 (void) platform_device_register(&omap_mpuio_device);
1192 static inline void mpuio_init(void) {}
1197 extern struct irq_chip mpuio_irq_chip;
1199 #define bank_is_mpuio(bank) 0
1200 static inline void mpuio_init(void) {}
1204 /*---------------------------------------------------------------------*/
1206 /* REVISIT these are stupid implementations! replace by ones that
1207 * don't switch on METHOD_* and which mostly avoid spinlocks
1210 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1212 struct gpio_bank *bank;
1213 unsigned long flags;
1215 bank = container_of(chip, struct gpio_bank, chip);
1216 spin_lock_irqsave(&bank->lock, flags);
1217 _set_gpio_direction(bank, offset, 1);
1218 spin_unlock_irqrestore(&bank->lock, flags);
1222 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1224 return __omap_get_gpio_datain(chip->base + offset);
1227 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1229 struct gpio_bank *bank;
1230 unsigned long flags;
1232 bank = container_of(chip, struct gpio_bank, chip);
1233 spin_lock_irqsave(&bank->lock, flags);
1234 _set_gpio_dataout(bank, offset, value);
1235 _set_gpio_direction(bank, offset, 0);
1236 spin_unlock_irqrestore(&bank->lock, flags);
1240 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1242 struct gpio_bank *bank;
1243 unsigned long flags;
1245 bank = container_of(chip, struct gpio_bank, chip);
1246 spin_lock_irqsave(&bank->lock, flags);
1247 _set_gpio_dataout(bank, offset, value);
1248 spin_unlock_irqrestore(&bank->lock, flags);
1251 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1253 struct gpio_bank *bank;
1255 bank = container_of(chip, struct gpio_bank, chip);
1256 return bank->virtual_irq_start + offset;
1259 /*---------------------------------------------------------------------*/
1261 static int initialized;
1262 #if !defined(CONFIG_ARCH_OMAP3)
1263 static struct clk * gpio_ick;
1266 #if defined(CONFIG_ARCH_OMAP2)
1267 static struct clk * gpio_fck;
1270 #if defined(CONFIG_ARCH_OMAP2430)
1271 static struct clk * gpio5_ick;
1272 static struct clk * gpio5_fck;
1275 #if defined(CONFIG_ARCH_OMAP3)
1276 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1279 /* This lock class tells lockdep that GPIO irqs are in a different
1280 * category than their parents, so it won't report false recursion.
1282 static struct lock_class_key gpio_lock_class;
1284 static int __init _omap_gpio_init(void)
1288 struct gpio_bank *bank;
1293 #if defined(CONFIG_ARCH_OMAP1)
1294 if (cpu_is_omap15xx()) {
1295 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1296 if (IS_ERR(gpio_ick))
1297 printk("Could not get arm_gpio_ck\n");
1299 clk_enable(gpio_ick);
1302 #if defined(CONFIG_ARCH_OMAP2)
1303 if (cpu_class_is_omap2()) {
1304 gpio_ick = clk_get(NULL, "gpios_ick");
1305 if (IS_ERR(gpio_ick))
1306 printk("Could not get gpios_ick\n");
1308 clk_enable(gpio_ick);
1309 gpio_fck = clk_get(NULL, "gpios_fck");
1310 if (IS_ERR(gpio_fck))
1311 printk("Could not get gpios_fck\n");
1313 clk_enable(gpio_fck);
1316 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1318 #if defined(CONFIG_ARCH_OMAP2430)
1319 if (cpu_is_omap2430()) {
1320 gpio5_ick = clk_get(NULL, "gpio5_ick");
1321 if (IS_ERR(gpio5_ick))
1322 printk("Could not get gpio5_ick\n");
1324 clk_enable(gpio5_ick);
1325 gpio5_fck = clk_get(NULL, "gpio5_fck");
1326 if (IS_ERR(gpio5_fck))
1327 printk("Could not get gpio5_fck\n");
1329 clk_enable(gpio5_fck);
1335 #if defined(CONFIG_ARCH_OMAP3)
1336 if (cpu_is_omap34xx()) {
1337 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1338 sprintf(clk_name, "gpio%d_ick", i + 1);
1339 gpio_iclks[i] = clk_get(NULL, clk_name);
1340 if (IS_ERR(gpio_iclks[i]))
1341 printk(KERN_ERR "Could not get %s\n", clk_name);
1343 clk_enable(gpio_iclks[i]);
1349 #ifdef CONFIG_ARCH_OMAP15XX
1350 if (cpu_is_omap15xx()) {
1351 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1352 gpio_bank_count = 2;
1353 gpio_bank = gpio_bank_1510;
1356 #if defined(CONFIG_ARCH_OMAP16XX)
1357 if (cpu_is_omap16xx()) {
1360 gpio_bank_count = 5;
1361 gpio_bank = gpio_bank_1610;
1362 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1363 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1364 (rev >> 4) & 0x0f, rev & 0x0f);
1367 #ifdef CONFIG_ARCH_OMAP730
1368 if (cpu_is_omap730()) {
1369 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1370 gpio_bank_count = 7;
1371 gpio_bank = gpio_bank_730;
1375 #ifdef CONFIG_ARCH_OMAP24XX
1376 if (cpu_is_omap242x()) {
1379 gpio_bank_count = 4;
1380 gpio_bank = gpio_bank_242x;
1381 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1382 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1383 (rev >> 4) & 0x0f, rev & 0x0f);
1385 if (cpu_is_omap243x()) {
1388 gpio_bank_count = 5;
1389 gpio_bank = gpio_bank_243x;
1390 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1391 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1392 (rev >> 4) & 0x0f, rev & 0x0f);
1395 #ifdef CONFIG_ARCH_OMAP34XX
1396 if (cpu_is_omap34xx()) {
1399 gpio_bank_count = OMAP34XX_NR_GPIOS;
1400 gpio_bank = gpio_bank_34xx;
1401 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1402 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1403 (rev >> 4) & 0x0f, rev & 0x0f);
1406 for (i = 0; i < gpio_bank_count; i++) {
1407 int j, gpio_count = 16;
1409 bank = &gpio_bank[i];
1410 spin_lock_init(&bank->lock);
1411 if (bank_is_mpuio(bank))
1412 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1413 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1414 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1415 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1417 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1418 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1419 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1420 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1422 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1423 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1424 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1426 gpio_count = 32; /* 730 has 32-bit GPIOs */
1429 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1430 if (bank->method == METHOD_GPIO_24XX) {
1431 static const u32 non_wakeup_gpios[] = {
1432 0xe203ffc0, 0x08700040
1435 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1436 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1437 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1439 /* Initialize interface clock ungated, module enabled */
1440 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1441 if (i < ARRAY_SIZE(non_wakeup_gpios))
1442 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1447 /* REVISIT eventually switch from OMAP-specific gpio structs
1448 * over to the generic ones
1450 bank->chip.request = omap_gpio_request;
1451 bank->chip.free = omap_gpio_free;
1452 bank->chip.direction_input = gpio_input;
1453 bank->chip.get = gpio_get;
1454 bank->chip.direction_output = gpio_output;
1455 bank->chip.set = gpio_set;
1456 bank->chip.to_irq = gpio_2irq;
1457 if (bank_is_mpuio(bank)) {
1458 bank->chip.label = "mpuio";
1459 #ifdef CONFIG_ARCH_OMAP16XX
1460 bank->chip.dev = &omap_mpuio_device.dev;
1462 bank->chip.base = OMAP_MPUIO(0);
1464 bank->chip.label = "gpio";
1465 bank->chip.base = gpio;
1468 bank->chip.ngpio = gpio_count;
1470 gpiochip_add(&bank->chip);
1472 for (j = bank->virtual_irq_start;
1473 j < bank->virtual_irq_start + gpio_count; j++) {
1474 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1475 set_irq_chip_data(j, bank);
1476 if (bank_is_mpuio(bank))
1477 set_irq_chip(j, &mpuio_irq_chip);
1479 set_irq_chip(j, &gpio_irq_chip);
1480 set_irq_handler(j, handle_simple_irq);
1481 set_irq_flags(j, IRQF_VALID);
1483 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1484 set_irq_data(bank->irq, bank);
1486 if (cpu_is_omap34xx()) {
1487 sprintf(clk_name, "gpio%d_dbck", i + 1);
1488 bank->dbck = clk_get(NULL, clk_name);
1489 if (IS_ERR(bank->dbck))
1490 printk(KERN_ERR "Could not get %s\n", clk_name);
1494 /* Enable system clock for GPIO module.
1495 * The CAM_CLK_CTRL *is* really the right place. */
1496 if (cpu_is_omap16xx())
1497 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1499 /* Enable autoidle for the OCP interface */
1500 if (cpu_is_omap24xx())
1501 omap_writel(1 << 0, 0x48019010);
1502 if (cpu_is_omap34xx())
1503 omap_writel(1 << 0, 0x48306814);
1508 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1509 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1513 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1516 for (i = 0; i < gpio_bank_count; i++) {
1517 struct gpio_bank *bank = &gpio_bank[i];
1518 void __iomem *wake_status;
1519 void __iomem *wake_clear;
1520 void __iomem *wake_set;
1521 unsigned long flags;
1523 switch (bank->method) {
1524 #ifdef CONFIG_ARCH_OMAP16XX
1525 case METHOD_GPIO_1610:
1526 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1527 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1528 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1531 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1532 case METHOD_GPIO_24XX:
1533 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1534 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1535 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1542 spin_lock_irqsave(&bank->lock, flags);
1543 bank->saved_wakeup = __raw_readl(wake_status);
1544 __raw_writel(0xffffffff, wake_clear);
1545 __raw_writel(bank->suspend_wakeup, wake_set);
1546 spin_unlock_irqrestore(&bank->lock, flags);
1552 static int omap_gpio_resume(struct sys_device *dev)
1556 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1559 for (i = 0; i < gpio_bank_count; i++) {
1560 struct gpio_bank *bank = &gpio_bank[i];
1561 void __iomem *wake_clear;
1562 void __iomem *wake_set;
1563 unsigned long flags;
1565 switch (bank->method) {
1566 #ifdef CONFIG_ARCH_OMAP16XX
1567 case METHOD_GPIO_1610:
1568 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1569 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1572 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1573 case METHOD_GPIO_24XX:
1574 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1575 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1582 spin_lock_irqsave(&bank->lock, flags);
1583 __raw_writel(0xffffffff, wake_clear);
1584 __raw_writel(bank->saved_wakeup, wake_set);
1585 spin_unlock_irqrestore(&bank->lock, flags);
1591 static struct sysdev_class omap_gpio_sysclass = {
1593 .suspend = omap_gpio_suspend,
1594 .resume = omap_gpio_resume,
1597 static struct sys_device omap_gpio_device = {
1599 .cls = &omap_gpio_sysclass,
1604 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1606 static int workaround_enabled;
1608 void omap2_gpio_prepare_for_retention(void)
1612 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1613 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1614 for (i = 0; i < gpio_bank_count; i++) {
1615 struct gpio_bank *bank = &gpio_bank[i];
1618 if (!(bank->enabled_non_wakeup_gpios))
1620 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1621 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1622 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1623 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1625 bank->saved_fallingdetect = l1;
1626 bank->saved_risingdetect = l2;
1627 l1 &= ~bank->enabled_non_wakeup_gpios;
1628 l2 &= ~bank->enabled_non_wakeup_gpios;
1629 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1630 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1631 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1636 workaround_enabled = 0;
1639 workaround_enabled = 1;
1642 void omap2_gpio_resume_after_retention(void)
1646 if (!workaround_enabled)
1648 for (i = 0; i < gpio_bank_count; i++) {
1649 struct gpio_bank *bank = &gpio_bank[i];
1652 if (!(bank->enabled_non_wakeup_gpios))
1654 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1655 __raw_writel(bank->saved_fallingdetect,
1656 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1657 __raw_writel(bank->saved_risingdetect,
1658 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1660 /* Check if any of the non-wakeup interrupt GPIOs have changed
1661 * state. If so, generate an IRQ by software. This is
1662 * horribly racy, but it's the best we can do to work around
1663 * this silicon bug. */
1664 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1665 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1667 l ^= bank->saved_datain;
1668 l &= bank->non_wakeup_gpios;
1671 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1672 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1673 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1674 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1675 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1676 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1677 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1687 * This may get called early from board specific init
1688 * for boards that have interrupts routed via FPGA.
1690 int __init omap_gpio_init(void)
1693 return _omap_gpio_init();
1698 static int __init omap_gpio_sysinit(void)
1703 ret = _omap_gpio_init();
1707 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1708 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1710 ret = sysdev_class_register(&omap_gpio_sysclass);
1712 ret = sysdev_register(&omap_gpio_device);
1720 arch_initcall(omap_gpio_sysinit);
1723 #ifdef CONFIG_DEBUG_FS
1725 #include <linux/debugfs.h>
1726 #include <linux/seq_file.h>
1728 static int gpio_is_input(struct gpio_bank *bank, int mask)
1730 void __iomem *reg = bank->base;
1732 switch (bank->method) {
1734 reg += OMAP_MPUIO_IO_CNTL;
1736 case METHOD_GPIO_1510:
1737 reg += OMAP1510_GPIO_DIR_CONTROL;
1739 case METHOD_GPIO_1610:
1740 reg += OMAP1610_GPIO_DIRECTION;
1742 case METHOD_GPIO_730:
1743 reg += OMAP730_GPIO_DIR_CONTROL;
1745 case METHOD_GPIO_24XX:
1746 reg += OMAP24XX_GPIO_OE;
1749 return __raw_readl(reg) & mask;
1753 static int dbg_gpio_show(struct seq_file *s, void *unused)
1755 unsigned i, j, gpio;
1757 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1758 struct gpio_bank *bank = gpio_bank + i;
1759 unsigned bankwidth = 16;
1762 if (bank_is_mpuio(bank))
1763 gpio = OMAP_MPUIO(0);
1764 else if (cpu_class_is_omap2() || cpu_is_omap730())
1767 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1768 unsigned irq, value, is_in, irqstat;
1771 label = gpiochip_is_requested(&bank->chip, j);
1775 irq = bank->virtual_irq_start + j;
1776 value = gpio_get_value(gpio);
1777 is_in = gpio_is_input(bank, mask);
1779 if (bank_is_mpuio(bank))
1780 seq_printf(s, "MPUIO %2d ", j);
1782 seq_printf(s, "GPIO %3d ", gpio);
1783 seq_printf(s, "(%-20.20s): %s %s",
1785 is_in ? "in " : "out",
1786 value ? "hi" : "lo");
1788 /* FIXME for at least omap2, show pullup/pulldown state */
1790 irqstat = irq_desc[irq].status;
1791 if (is_in && ((bank->suspend_wakeup & mask)
1792 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1793 char *trigger = NULL;
1795 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1796 case IRQ_TYPE_EDGE_FALLING:
1797 trigger = "falling";
1799 case IRQ_TYPE_EDGE_RISING:
1802 case IRQ_TYPE_EDGE_BOTH:
1803 trigger = "bothedge";
1805 case IRQ_TYPE_LEVEL_LOW:
1808 case IRQ_TYPE_LEVEL_HIGH:
1815 seq_printf(s, ", irq-%d %-8s%s",
1817 (bank->suspend_wakeup & mask)
1820 seq_printf(s, "\n");
1823 if (bank_is_mpuio(bank)) {
1824 seq_printf(s, "\n");
1831 static int dbg_gpio_open(struct inode *inode, struct file *file)
1833 return single_open(file, dbg_gpio_show, &inode->i_private);
1836 static const struct file_operations debug_fops = {
1837 .open = dbg_gpio_open,
1839 .llseek = seq_lseek,
1840 .release = single_release,
1843 static int __init omap_gpio_debuginit(void)
1845 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1846 NULL, NULL, &debug_fops);
1849 late_initcall(omap_gpio_debuginit);