2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <mach/hardware.h>
23 #include <mach/irqs.h>
24 #include <mach/gpio.h>
25 #include <asm/mach/irq.h>
30 * OMAP1510 GPIO registers
32 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41 #define OMAP1510_IH_GPIO_BASE 64
44 * OMAP1610 specific GPIO registers
46 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
47 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
48 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
49 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 * OMAP730 specific GPIO registers
71 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
72 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
73 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
74 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
75 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
76 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
85 * omap24xx specific GPIO registers
87 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
88 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
89 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
90 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
92 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
93 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
94 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
95 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
96 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
133 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
138 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
154 struct gpio_chip chip;
157 #define METHOD_MPUIO 0
158 #define METHOD_GPIO_1510 1
159 #define METHOD_GPIO_1610 2
160 #define METHOD_GPIO_730 3
161 #define METHOD_GPIO_24XX 4
163 #ifdef CONFIG_ARCH_OMAP16XX
164 static struct gpio_bank gpio_bank_1610[5] = {
165 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
166 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
173 #ifdef CONFIG_ARCH_OMAP15XX
174 static struct gpio_bank gpio_bank_1510[2] = {
175 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
176 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
180 #ifdef CONFIG_ARCH_OMAP730
181 static struct gpio_bank gpio_bank_730[7] = {
182 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
183 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
184 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
185 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
186 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
187 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
188 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
192 #ifdef CONFIG_ARCH_OMAP24XX
194 static struct gpio_bank gpio_bank_242x[4] = {
195 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
201 static struct gpio_bank gpio_bank_243x[5] = {
202 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
211 #ifdef CONFIG_ARCH_OMAP34XX
212 static struct gpio_bank gpio_bank_34xx[6] = {
213 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
223 static struct gpio_bank *gpio_bank;
224 static int gpio_bank_count;
226 static inline struct gpio_bank *get_gpio_bank(int gpio)
228 if (cpu_is_omap15xx()) {
229 if (OMAP_GPIO_IS_MPUIO(gpio))
230 return &gpio_bank[0];
231 return &gpio_bank[1];
233 if (cpu_is_omap16xx()) {
234 if (OMAP_GPIO_IS_MPUIO(gpio))
235 return &gpio_bank[0];
236 return &gpio_bank[1 + (gpio >> 4)];
238 if (cpu_is_omap730()) {
239 if (OMAP_GPIO_IS_MPUIO(gpio))
240 return &gpio_bank[0];
241 return &gpio_bank[1 + (gpio >> 5)];
243 if (cpu_is_omap24xx())
244 return &gpio_bank[gpio >> 5];
245 if (cpu_is_omap34xx())
246 return &gpio_bank[gpio >> 5];
249 static inline int get_gpio_index(int gpio)
251 if (cpu_is_omap730())
253 if (cpu_is_omap24xx())
255 if (cpu_is_omap34xx())
260 static inline int gpio_valid(int gpio)
264 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
265 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
269 if (cpu_is_omap15xx() && gpio < 16)
271 if ((cpu_is_omap16xx()) && gpio < 64)
273 if (cpu_is_omap730() && gpio < 192)
275 if (cpu_is_omap24xx() && gpio < 128)
277 if (cpu_is_omap34xx() && gpio < 160)
282 static int check_gpio(int gpio)
284 if (unlikely(gpio_valid(gpio)) < 0) {
285 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
292 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
294 void __iomem *reg = bank->base;
297 switch (bank->method) {
298 #ifdef CONFIG_ARCH_OMAP1
300 reg += OMAP_MPUIO_IO_CNTL;
303 #ifdef CONFIG_ARCH_OMAP15XX
304 case METHOD_GPIO_1510:
305 reg += OMAP1510_GPIO_DIR_CONTROL;
308 #ifdef CONFIG_ARCH_OMAP16XX
309 case METHOD_GPIO_1610:
310 reg += OMAP1610_GPIO_DIRECTION;
313 #ifdef CONFIG_ARCH_OMAP730
314 case METHOD_GPIO_730:
315 reg += OMAP730_GPIO_DIR_CONTROL;
318 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
319 case METHOD_GPIO_24XX:
320 reg += OMAP24XX_GPIO_OE;
327 l = __raw_readl(reg);
332 __raw_writel(l, reg);
335 void omap_set_gpio_direction(int gpio, int is_input)
337 struct gpio_bank *bank;
340 if (check_gpio(gpio) < 0)
342 bank = get_gpio_bank(gpio);
343 spin_lock_irqsave(&bank->lock, flags);
344 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
345 spin_unlock_irqrestore(&bank->lock, flags);
348 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
350 void __iomem *reg = bank->base;
353 switch (bank->method) {
354 #ifdef CONFIG_ARCH_OMAP1
356 reg += OMAP_MPUIO_OUTPUT;
357 l = __raw_readl(reg);
364 #ifdef CONFIG_ARCH_OMAP15XX
365 case METHOD_GPIO_1510:
366 reg += OMAP1510_GPIO_DATA_OUTPUT;
367 l = __raw_readl(reg);
374 #ifdef CONFIG_ARCH_OMAP16XX
375 case METHOD_GPIO_1610:
377 reg += OMAP1610_GPIO_SET_DATAOUT;
379 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
383 #ifdef CONFIG_ARCH_OMAP730
384 case METHOD_GPIO_730:
385 reg += OMAP730_GPIO_DATA_OUTPUT;
386 l = __raw_readl(reg);
393 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
394 case METHOD_GPIO_24XX:
396 reg += OMAP24XX_GPIO_SETDATAOUT;
398 reg += OMAP24XX_GPIO_CLEARDATAOUT;
406 __raw_writel(l, reg);
409 void omap_set_gpio_dataout(int gpio, int enable)
411 struct gpio_bank *bank;
414 if (check_gpio(gpio) < 0)
416 bank = get_gpio_bank(gpio);
417 spin_lock_irqsave(&bank->lock, flags);
418 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
419 spin_unlock_irqrestore(&bank->lock, flags);
422 int omap_get_gpio_datain(int gpio)
424 struct gpio_bank *bank;
427 if (check_gpio(gpio) < 0)
429 bank = get_gpio_bank(gpio);
431 switch (bank->method) {
432 #ifdef CONFIG_ARCH_OMAP1
434 reg += OMAP_MPUIO_INPUT_LATCH;
437 #ifdef CONFIG_ARCH_OMAP15XX
438 case METHOD_GPIO_1510:
439 reg += OMAP1510_GPIO_DATA_INPUT;
442 #ifdef CONFIG_ARCH_OMAP16XX
443 case METHOD_GPIO_1610:
444 reg += OMAP1610_GPIO_DATAIN;
447 #ifdef CONFIG_ARCH_OMAP730
448 case METHOD_GPIO_730:
449 reg += OMAP730_GPIO_DATA_INPUT;
452 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
453 case METHOD_GPIO_24XX:
454 reg += OMAP24XX_GPIO_DATAIN;
460 return (__raw_readl(reg)
461 & (1 << get_gpio_index(gpio))) != 0;
464 #define MOD_REG_BIT(reg, bit_mask, set) \
466 int l = __raw_readl(base + reg); \
467 if (set) l |= bit_mask; \
468 else l &= ~bit_mask; \
469 __raw_writel(l, base + reg); \
472 void omap_set_gpio_debounce(int gpio, int enable)
474 struct gpio_bank *bank;
476 u32 val, l = 1 << get_gpio_index(gpio);
478 if (cpu_class_is_omap1())
481 bank = get_gpio_bank(gpio);
484 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
485 val = __raw_readl(reg);
492 __raw_writel(val, reg);
494 EXPORT_SYMBOL(omap_set_gpio_debounce);
496 void omap_set_gpio_debounce_time(int gpio, int enc_time)
498 struct gpio_bank *bank;
501 if (cpu_class_is_omap1())
504 bank = get_gpio_bank(gpio);
508 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
509 __raw_writel(enc_time, reg);
511 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
513 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
514 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
517 void __iomem *base = bank->base;
518 u32 gpio_bit = 1 << gpio;
520 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
521 trigger & IRQ_TYPE_LEVEL_LOW);
522 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
523 trigger & IRQ_TYPE_LEVEL_HIGH);
524 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
525 trigger & IRQ_TYPE_EDGE_RISING);
526 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
527 trigger & IRQ_TYPE_EDGE_FALLING);
529 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
531 __raw_writel(1 << gpio, bank->base
532 + OMAP24XX_GPIO_SETWKUENA);
534 __raw_writel(1 << gpio, bank->base
535 + OMAP24XX_GPIO_CLEARWKUENA);
538 bank->enabled_non_wakeup_gpios |= gpio_bit;
540 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
544 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
545 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
549 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
551 void __iomem *reg = bank->base;
554 switch (bank->method) {
555 #ifdef CONFIG_ARCH_OMAP1
557 reg += OMAP_MPUIO_GPIO_INT_EDGE;
558 l = __raw_readl(reg);
559 if (trigger & IRQ_TYPE_EDGE_RISING)
561 else if (trigger & IRQ_TYPE_EDGE_FALLING)
567 #ifdef CONFIG_ARCH_OMAP15XX
568 case METHOD_GPIO_1510:
569 reg += OMAP1510_GPIO_INT_CONTROL;
570 l = __raw_readl(reg);
571 if (trigger & IRQ_TYPE_EDGE_RISING)
573 else if (trigger & IRQ_TYPE_EDGE_FALLING)
579 #ifdef CONFIG_ARCH_OMAP16XX
580 case METHOD_GPIO_1610:
582 reg += OMAP1610_GPIO_EDGE_CTRL2;
584 reg += OMAP1610_GPIO_EDGE_CTRL1;
586 l = __raw_readl(reg);
587 l &= ~(3 << (gpio << 1));
588 if (trigger & IRQ_TYPE_EDGE_RISING)
589 l |= 2 << (gpio << 1);
590 if (trigger & IRQ_TYPE_EDGE_FALLING)
591 l |= 1 << (gpio << 1);
593 /* Enable wake-up during idle for dynamic tick */
594 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
596 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
599 #ifdef CONFIG_ARCH_OMAP730
600 case METHOD_GPIO_730:
601 reg += OMAP730_GPIO_INT_CONTROL;
602 l = __raw_readl(reg);
603 if (trigger & IRQ_TYPE_EDGE_RISING)
605 else if (trigger & IRQ_TYPE_EDGE_FALLING)
611 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
612 case METHOD_GPIO_24XX:
613 set_24xx_gpio_triggering(bank, gpio, trigger);
619 __raw_writel(l, reg);
625 static int gpio_irq_type(unsigned irq, unsigned type)
627 struct gpio_bank *bank;
632 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
633 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
635 gpio = irq - IH_GPIO_BASE;
637 if (check_gpio(gpio) < 0)
640 if (type & ~IRQ_TYPE_SENSE_MASK)
643 /* OMAP1 allows only only edge triggering */
644 if (!cpu_class_is_omap2()
645 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
648 bank = get_irq_chip_data(irq);
649 spin_lock_irqsave(&bank->lock, flags);
650 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
652 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
653 irq_desc[irq].status |= type;
655 spin_unlock_irqrestore(&bank->lock, flags);
657 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
658 __set_irq_handler_unlocked(irq, handle_level_irq);
659 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
660 __set_irq_handler_unlocked(irq, handle_edge_irq);
665 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
667 void __iomem *reg = bank->base;
669 switch (bank->method) {
670 #ifdef CONFIG_ARCH_OMAP1
672 /* MPUIO irqstatus is reset by reading the status register,
673 * so do nothing here */
676 #ifdef CONFIG_ARCH_OMAP15XX
677 case METHOD_GPIO_1510:
678 reg += OMAP1510_GPIO_INT_STATUS;
681 #ifdef CONFIG_ARCH_OMAP16XX
682 case METHOD_GPIO_1610:
683 reg += OMAP1610_GPIO_IRQSTATUS1;
686 #ifdef CONFIG_ARCH_OMAP730
687 case METHOD_GPIO_730:
688 reg += OMAP730_GPIO_INT_STATUS;
691 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
692 case METHOD_GPIO_24XX:
693 reg += OMAP24XX_GPIO_IRQSTATUS1;
700 __raw_writel(gpio_mask, reg);
702 /* Workaround for clearing DSP GPIO interrupts to allow retention */
703 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
704 if (cpu_is_omap24xx() || cpu_is_omap34xx())
705 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
709 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
711 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
714 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
716 void __iomem *reg = bank->base;
721 switch (bank->method) {
722 #ifdef CONFIG_ARCH_OMAP1
724 reg += OMAP_MPUIO_GPIO_MASKIT;
729 #ifdef CONFIG_ARCH_OMAP15XX
730 case METHOD_GPIO_1510:
731 reg += OMAP1510_GPIO_INT_MASK;
736 #ifdef CONFIG_ARCH_OMAP16XX
737 case METHOD_GPIO_1610:
738 reg += OMAP1610_GPIO_IRQENABLE1;
742 #ifdef CONFIG_ARCH_OMAP730
743 case METHOD_GPIO_730:
744 reg += OMAP730_GPIO_INT_MASK;
749 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
750 case METHOD_GPIO_24XX:
751 reg += OMAP24XX_GPIO_IRQENABLE1;
760 l = __raw_readl(reg);
767 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
769 void __iomem *reg = bank->base;
772 switch (bank->method) {
773 #ifdef CONFIG_ARCH_OMAP1
775 reg += OMAP_MPUIO_GPIO_MASKIT;
776 l = __raw_readl(reg);
783 #ifdef CONFIG_ARCH_OMAP15XX
784 case METHOD_GPIO_1510:
785 reg += OMAP1510_GPIO_INT_MASK;
786 l = __raw_readl(reg);
793 #ifdef CONFIG_ARCH_OMAP16XX
794 case METHOD_GPIO_1610:
796 reg += OMAP1610_GPIO_SET_IRQENABLE1;
798 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
802 #ifdef CONFIG_ARCH_OMAP730
803 case METHOD_GPIO_730:
804 reg += OMAP730_GPIO_INT_MASK;
805 l = __raw_readl(reg);
812 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
813 case METHOD_GPIO_24XX:
815 reg += OMAP24XX_GPIO_SETIRQENABLE1;
817 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
825 __raw_writel(l, reg);
828 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
830 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
834 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
835 * 1510 does not seem to have a wake-up register. If JTAG is connected
836 * to the target, system will wake up always on GPIO events. While
837 * system is running all registered GPIO interrupts need to have wake-up
838 * enabled. When system is suspended, only selected GPIO interrupts need
839 * to have wake-up enabled.
841 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
845 switch (bank->method) {
846 #ifdef CONFIG_ARCH_OMAP16XX
848 case METHOD_GPIO_1610:
849 spin_lock_irqsave(&bank->lock, flags);
851 bank->suspend_wakeup |= (1 << gpio);
852 enable_irq_wake(bank->irq);
854 disable_irq_wake(bank->irq);
855 bank->suspend_wakeup &= ~(1 << gpio);
857 spin_unlock_irqrestore(&bank->lock, flags);
860 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
861 case METHOD_GPIO_24XX:
862 if (bank->non_wakeup_gpios & (1 << gpio)) {
863 printk(KERN_ERR "Unable to modify wakeup on "
864 "non-wakeup GPIO%d\n",
865 (bank - gpio_bank) * 32 + gpio);
868 spin_lock_irqsave(&bank->lock, flags);
870 bank->suspend_wakeup |= (1 << gpio);
871 enable_irq_wake(bank->irq);
873 disable_irq_wake(bank->irq);
874 bank->suspend_wakeup &= ~(1 << gpio);
876 spin_unlock_irqrestore(&bank->lock, flags);
880 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
886 static void _reset_gpio(struct gpio_bank *bank, int gpio)
888 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
889 _set_gpio_irqenable(bank, gpio, 0);
890 _clear_gpio_irqstatus(bank, gpio);
891 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
894 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
895 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
897 unsigned int gpio = irq - IH_GPIO_BASE;
898 struct gpio_bank *bank;
901 if (check_gpio(gpio) < 0)
903 bank = get_irq_chip_data(irq);
904 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
909 int omap_request_gpio(int gpio)
911 struct gpio_bank *bank;
915 if (check_gpio(gpio) < 0)
918 status = gpio_request(gpio, NULL);
922 bank = get_gpio_bank(gpio);
923 spin_lock_irqsave(&bank->lock, flags);
925 /* Set trigger to none. You need to enable the desired trigger with
926 * request_irq() or set_irq_type().
928 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
930 #ifdef CONFIG_ARCH_OMAP15XX
931 if (bank->method == METHOD_GPIO_1510) {
934 /* Claim the pin for MPU */
935 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
936 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
939 spin_unlock_irqrestore(&bank->lock, flags);
944 void omap_free_gpio(int gpio)
946 struct gpio_bank *bank;
949 if (check_gpio(gpio) < 0)
951 bank = get_gpio_bank(gpio);
952 spin_lock_irqsave(&bank->lock, flags);
953 if (unlikely(!gpiochip_is_requested(&bank->chip,
954 get_gpio_index(gpio)))) {
955 spin_unlock_irqrestore(&bank->lock, flags);
956 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
960 #ifdef CONFIG_ARCH_OMAP16XX
961 if (bank->method == METHOD_GPIO_1610) {
962 /* Disable wake-up during idle for dynamic tick */
963 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
964 __raw_writel(1 << get_gpio_index(gpio), reg);
967 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
968 if (bank->method == METHOD_GPIO_24XX) {
969 /* Disable wake-up during idle for dynamic tick */
970 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
971 __raw_writel(1 << get_gpio_index(gpio), reg);
974 _reset_gpio(bank, gpio);
975 spin_unlock_irqrestore(&bank->lock, flags);
980 * We need to unmask the GPIO bank interrupt as soon as possible to
981 * avoid missing GPIO interrupts for other lines in the bank.
982 * Then we need to mask-read-clear-unmask the triggered GPIO lines
983 * in the bank to avoid missing nested interrupts for a GPIO line.
984 * If we wait to unmask individual GPIO lines in the bank after the
985 * line's interrupt handler has been run, we may miss some nested
988 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
990 void __iomem *isr_reg = NULL;
992 unsigned int gpio_irq;
993 struct gpio_bank *bank;
997 desc->chip->ack(irq);
999 bank = get_irq_data(irq);
1000 #ifdef CONFIG_ARCH_OMAP1
1001 if (bank->method == METHOD_MPUIO)
1002 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1004 #ifdef CONFIG_ARCH_OMAP15XX
1005 if (bank->method == METHOD_GPIO_1510)
1006 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1008 #if defined(CONFIG_ARCH_OMAP16XX)
1009 if (bank->method == METHOD_GPIO_1610)
1010 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1012 #ifdef CONFIG_ARCH_OMAP730
1013 if (bank->method == METHOD_GPIO_730)
1014 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1016 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1017 if (bank->method == METHOD_GPIO_24XX)
1018 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1021 u32 isr_saved, level_mask = 0;
1024 enabled = _get_gpio_irqbank_mask(bank);
1025 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1027 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1030 if (cpu_class_is_omap2()) {
1031 level_mask = bank->level_mask & enabled;
1034 /* clear edge sensitive interrupts before handler(s) are
1035 called so that we don't miss any interrupt occurred while
1037 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1038 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1039 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1041 /* if there is only edge sensitive GPIO pin interrupts
1042 configured, we could unmask GPIO bank interrupt immediately */
1043 if (!level_mask && !unmasked) {
1045 desc->chip->unmask(irq);
1053 gpio_irq = bank->virtual_irq_start;
1054 for (; isr != 0; isr >>= 1, gpio_irq++) {
1059 d = irq_desc + gpio_irq;
1061 desc_handle_irq(gpio_irq, d);
1064 /* if bank has any level sensitive GPIO pin interrupt
1065 configured, we must unmask the bank interrupt only after
1066 handler(s) are executed in order to avoid spurious bank
1069 desc->chip->unmask(irq);
1073 static void gpio_irq_shutdown(unsigned int irq)
1075 unsigned int gpio = irq - IH_GPIO_BASE;
1076 struct gpio_bank *bank = get_irq_chip_data(irq);
1078 _reset_gpio(bank, gpio);
1081 static void gpio_ack_irq(unsigned int irq)
1083 unsigned int gpio = irq - IH_GPIO_BASE;
1084 struct gpio_bank *bank = get_irq_chip_data(irq);
1086 _clear_gpio_irqstatus(bank, gpio);
1089 static void gpio_mask_irq(unsigned int irq)
1091 unsigned int gpio = irq - IH_GPIO_BASE;
1092 struct gpio_bank *bank = get_irq_chip_data(irq);
1094 _set_gpio_irqenable(bank, gpio, 0);
1097 static void gpio_unmask_irq(unsigned int irq)
1099 unsigned int gpio = irq - IH_GPIO_BASE;
1100 struct gpio_bank *bank = get_irq_chip_data(irq);
1101 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1103 /* For level-triggered GPIOs, the clearing must be done after
1104 * the HW source is cleared, thus after the handler has run */
1105 if (bank->level_mask & irq_mask) {
1106 _set_gpio_irqenable(bank, gpio, 0);
1107 _clear_gpio_irqstatus(bank, gpio);
1110 _set_gpio_irqenable(bank, gpio, 1);
1113 static struct irq_chip gpio_irq_chip = {
1115 .shutdown = gpio_irq_shutdown,
1116 .ack = gpio_ack_irq,
1117 .mask = gpio_mask_irq,
1118 .unmask = gpio_unmask_irq,
1119 .set_type = gpio_irq_type,
1120 .set_wake = gpio_wake_enable,
1123 /*---------------------------------------------------------------------*/
1125 #ifdef CONFIG_ARCH_OMAP1
1127 /* MPUIO uses the always-on 32k clock */
1129 static void mpuio_ack_irq(unsigned int irq)
1131 /* The ISR is reset automatically, so do nothing here. */
1134 static void mpuio_mask_irq(unsigned int irq)
1136 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1137 struct gpio_bank *bank = get_irq_chip_data(irq);
1139 _set_gpio_irqenable(bank, gpio, 0);
1142 static void mpuio_unmask_irq(unsigned int irq)
1144 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1145 struct gpio_bank *bank = get_irq_chip_data(irq);
1147 _set_gpio_irqenable(bank, gpio, 1);
1150 static struct irq_chip mpuio_irq_chip = {
1152 .ack = mpuio_ack_irq,
1153 .mask = mpuio_mask_irq,
1154 .unmask = mpuio_unmask_irq,
1155 .set_type = gpio_irq_type,
1156 #ifdef CONFIG_ARCH_OMAP16XX
1157 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1158 .set_wake = gpio_wake_enable,
1163 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1166 #ifdef CONFIG_ARCH_OMAP16XX
1168 #include <linux/platform_device.h>
1170 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1172 struct gpio_bank *bank = platform_get_drvdata(pdev);
1173 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1174 unsigned long flags;
1176 spin_lock_irqsave(&bank->lock, flags);
1177 bank->saved_wakeup = __raw_readl(mask_reg);
1178 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1179 spin_unlock_irqrestore(&bank->lock, flags);
1184 static int omap_mpuio_resume_early(struct platform_device *pdev)
1186 struct gpio_bank *bank = platform_get_drvdata(pdev);
1187 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1188 unsigned long flags;
1190 spin_lock_irqsave(&bank->lock, flags);
1191 __raw_writel(bank->saved_wakeup, mask_reg);
1192 spin_unlock_irqrestore(&bank->lock, flags);
1197 /* use platform_driver for this, now that there's no longer any
1198 * point to sys_device (other than not disturbing old code).
1200 static struct platform_driver omap_mpuio_driver = {
1201 .suspend_late = omap_mpuio_suspend_late,
1202 .resume_early = omap_mpuio_resume_early,
1208 static struct platform_device omap_mpuio_device = {
1212 .driver = &omap_mpuio_driver.driver,
1214 /* could list the /proc/iomem resources */
1217 static inline void mpuio_init(void)
1219 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1221 if (platform_driver_register(&omap_mpuio_driver) == 0)
1222 (void) platform_device_register(&omap_mpuio_device);
1226 static inline void mpuio_init(void) {}
1231 extern struct irq_chip mpuio_irq_chip;
1233 #define bank_is_mpuio(bank) 0
1234 static inline void mpuio_init(void) {}
1238 /*---------------------------------------------------------------------*/
1240 /* REVISIT these are stupid implementations! replace by ones that
1241 * don't switch on METHOD_* and which mostly avoid spinlocks
1244 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1246 struct gpio_bank *bank;
1247 unsigned long flags;
1249 bank = container_of(chip, struct gpio_bank, chip);
1250 spin_lock_irqsave(&bank->lock, flags);
1251 _set_gpio_direction(bank, offset, 1);
1252 spin_unlock_irqrestore(&bank->lock, flags);
1256 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1258 return omap_get_gpio_datain(chip->base + offset);
1261 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1263 struct gpio_bank *bank;
1264 unsigned long flags;
1266 bank = container_of(chip, struct gpio_bank, chip);
1267 spin_lock_irqsave(&bank->lock, flags);
1268 _set_gpio_dataout(bank, offset, value);
1269 _set_gpio_direction(bank, offset, 0);
1270 spin_unlock_irqrestore(&bank->lock, flags);
1274 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1276 struct gpio_bank *bank;
1277 unsigned long flags;
1279 bank = container_of(chip, struct gpio_bank, chip);
1280 spin_lock_irqsave(&bank->lock, flags);
1281 _set_gpio_dataout(bank, offset, value);
1282 spin_unlock_irqrestore(&bank->lock, flags);
1285 /*---------------------------------------------------------------------*/
1287 static int initialized;
1288 #if !defined(CONFIG_ARCH_OMAP3)
1289 static struct clk * gpio_ick;
1292 #if defined(CONFIG_ARCH_OMAP2)
1293 static struct clk * gpio_fck;
1296 #if defined(CONFIG_ARCH_OMAP2430)
1297 static struct clk * gpio5_ick;
1298 static struct clk * gpio5_fck;
1301 #if defined(CONFIG_ARCH_OMAP3)
1302 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1303 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1306 /* This lock class tells lockdep that GPIO irqs are in a different
1307 * category than their parents, so it won't report false recursion.
1309 static struct lock_class_key gpio_lock_class;
1311 static int __init _omap_gpio_init(void)
1315 struct gpio_bank *bank;
1316 #if defined(CONFIG_ARCH_OMAP3)
1322 #if defined(CONFIG_ARCH_OMAP1)
1323 if (cpu_is_omap15xx()) {
1324 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1325 if (IS_ERR(gpio_ick))
1326 printk("Could not get arm_gpio_ck\n");
1328 clk_enable(gpio_ick);
1331 #if defined(CONFIG_ARCH_OMAP2)
1332 if (cpu_class_is_omap2()) {
1333 gpio_ick = clk_get(NULL, "gpios_ick");
1334 if (IS_ERR(gpio_ick))
1335 printk("Could not get gpios_ick\n");
1337 clk_enable(gpio_ick);
1338 gpio_fck = clk_get(NULL, "gpios_fck");
1339 if (IS_ERR(gpio_fck))
1340 printk("Could not get gpios_fck\n");
1342 clk_enable(gpio_fck);
1345 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1347 #if defined(CONFIG_ARCH_OMAP2430)
1348 if (cpu_is_omap2430()) {
1349 gpio5_ick = clk_get(NULL, "gpio5_ick");
1350 if (IS_ERR(gpio5_ick))
1351 printk("Could not get gpio5_ick\n");
1353 clk_enable(gpio5_ick);
1354 gpio5_fck = clk_get(NULL, "gpio5_fck");
1355 if (IS_ERR(gpio5_fck))
1356 printk("Could not get gpio5_fck\n");
1358 clk_enable(gpio5_fck);
1364 #if defined(CONFIG_ARCH_OMAP3)
1365 if (cpu_is_omap34xx()) {
1366 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1367 sprintf(clk_name, "gpio%d_ick", i + 1);
1368 gpio_iclks[i] = clk_get(NULL, clk_name);
1369 if (IS_ERR(gpio_iclks[i]))
1370 printk(KERN_ERR "Could not get %s\n", clk_name);
1372 clk_enable(gpio_iclks[i]);
1373 sprintf(clk_name, "gpio%d_fck", i + 1);
1374 gpio_fclks[i] = clk_get(NULL, clk_name);
1375 if (IS_ERR(gpio_fclks[i]))
1376 printk(KERN_ERR "Could not get %s\n", clk_name);
1378 clk_enable(gpio_fclks[i]);
1384 #ifdef CONFIG_ARCH_OMAP15XX
1385 if (cpu_is_omap15xx()) {
1386 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1387 gpio_bank_count = 2;
1388 gpio_bank = gpio_bank_1510;
1391 #if defined(CONFIG_ARCH_OMAP16XX)
1392 if (cpu_is_omap16xx()) {
1395 gpio_bank_count = 5;
1396 gpio_bank = gpio_bank_1610;
1397 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1398 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1399 (rev >> 4) & 0x0f, rev & 0x0f);
1402 #ifdef CONFIG_ARCH_OMAP730
1403 if (cpu_is_omap730()) {
1404 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1405 gpio_bank_count = 7;
1406 gpio_bank = gpio_bank_730;
1410 #ifdef CONFIG_ARCH_OMAP24XX
1411 if (cpu_is_omap242x()) {
1414 gpio_bank_count = 4;
1415 gpio_bank = gpio_bank_242x;
1416 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1417 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1418 (rev >> 4) & 0x0f, rev & 0x0f);
1420 if (cpu_is_omap243x()) {
1423 gpio_bank_count = 5;
1424 gpio_bank = gpio_bank_243x;
1425 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1426 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1427 (rev >> 4) & 0x0f, rev & 0x0f);
1430 #ifdef CONFIG_ARCH_OMAP34XX
1431 if (cpu_is_omap34xx()) {
1434 gpio_bank_count = OMAP34XX_NR_GPIOS;
1435 gpio_bank = gpio_bank_34xx;
1436 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1437 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1438 (rev >> 4) & 0x0f, rev & 0x0f);
1441 for (i = 0; i < gpio_bank_count; i++) {
1442 int j, gpio_count = 16;
1444 bank = &gpio_bank[i];
1445 spin_lock_init(&bank->lock);
1446 if (bank_is_mpuio(bank))
1447 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1448 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1449 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1450 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1452 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1453 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1454 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1455 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1457 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1458 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1459 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1461 gpio_count = 32; /* 730 has 32-bit GPIOs */
1464 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1465 if (bank->method == METHOD_GPIO_24XX) {
1466 static const u32 non_wakeup_gpios[] = {
1467 0xe203ffc0, 0x08700040
1470 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1471 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1472 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1474 /* Initialize interface clock ungated, module enabled */
1475 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1476 if (i < ARRAY_SIZE(non_wakeup_gpios))
1477 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1482 /* REVISIT eventually switch from OMAP-specific gpio structs
1483 * over to the generic ones
1485 bank->chip.direction_input = gpio_input;
1486 bank->chip.get = gpio_get;
1487 bank->chip.direction_output = gpio_output;
1488 bank->chip.set = gpio_set;
1489 if (bank_is_mpuio(bank)) {
1490 bank->chip.label = "mpuio";
1491 #ifdef CONFIG_ARCH_OMAP16XX
1492 bank->chip.dev = &omap_mpuio_device.dev;
1494 bank->chip.base = OMAP_MPUIO(0);
1496 bank->chip.label = "gpio";
1497 bank->chip.base = gpio;
1500 bank->chip.ngpio = gpio_count;
1502 gpiochip_add(&bank->chip);
1504 for (j = bank->virtual_irq_start;
1505 j < bank->virtual_irq_start + gpio_count; j++) {
1506 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1507 set_irq_chip_data(j, bank);
1508 if (bank_is_mpuio(bank))
1509 set_irq_chip(j, &mpuio_irq_chip);
1511 set_irq_chip(j, &gpio_irq_chip);
1512 set_irq_handler(j, handle_simple_irq);
1513 set_irq_flags(j, IRQF_VALID);
1515 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1516 set_irq_data(bank->irq, bank);
1519 /* Enable system clock for GPIO module.
1520 * The CAM_CLK_CTRL *is* really the right place. */
1521 if (cpu_is_omap16xx())
1522 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1524 /* Enable autoidle for the OCP interface */
1525 if (cpu_is_omap24xx())
1526 omap_writel(1 << 0, 0x48019010);
1527 if (cpu_is_omap34xx())
1528 omap_writel(1 << 0, 0x48306814);
1533 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1534 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1538 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1541 for (i = 0; i < gpio_bank_count; i++) {
1542 struct gpio_bank *bank = &gpio_bank[i];
1543 void __iomem *wake_status;
1544 void __iomem *wake_clear;
1545 void __iomem *wake_set;
1546 unsigned long flags;
1548 switch (bank->method) {
1549 #ifdef CONFIG_ARCH_OMAP16XX
1550 case METHOD_GPIO_1610:
1551 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1552 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1553 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1556 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1557 case METHOD_GPIO_24XX:
1558 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1559 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1560 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1567 spin_lock_irqsave(&bank->lock, flags);
1568 bank->saved_wakeup = __raw_readl(wake_status);
1569 __raw_writel(0xffffffff, wake_clear);
1570 __raw_writel(bank->suspend_wakeup, wake_set);
1571 spin_unlock_irqrestore(&bank->lock, flags);
1577 static int omap_gpio_resume(struct sys_device *dev)
1581 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1584 for (i = 0; i < gpio_bank_count; i++) {
1585 struct gpio_bank *bank = &gpio_bank[i];
1586 void __iomem *wake_clear;
1587 void __iomem *wake_set;
1588 unsigned long flags;
1590 switch (bank->method) {
1591 #ifdef CONFIG_ARCH_OMAP16XX
1592 case METHOD_GPIO_1610:
1593 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1594 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1597 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1598 case METHOD_GPIO_24XX:
1599 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1600 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1607 spin_lock_irqsave(&bank->lock, flags);
1608 __raw_writel(0xffffffff, wake_clear);
1609 __raw_writel(bank->saved_wakeup, wake_set);
1610 spin_unlock_irqrestore(&bank->lock, flags);
1616 static struct sysdev_class omap_gpio_sysclass = {
1618 .suspend = omap_gpio_suspend,
1619 .resume = omap_gpio_resume,
1622 static struct sys_device omap_gpio_device = {
1624 .cls = &omap_gpio_sysclass,
1629 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1631 static int workaround_enabled;
1633 void omap2_gpio_prepare_for_retention(void)
1637 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1638 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1639 for (i = 0; i < gpio_bank_count; i++) {
1640 struct gpio_bank *bank = &gpio_bank[i];
1643 if (!(bank->enabled_non_wakeup_gpios))
1645 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1646 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1647 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1648 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1650 bank->saved_fallingdetect = l1;
1651 bank->saved_risingdetect = l2;
1652 l1 &= ~bank->enabled_non_wakeup_gpios;
1653 l2 &= ~bank->enabled_non_wakeup_gpios;
1654 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1655 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1656 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1661 workaround_enabled = 0;
1664 workaround_enabled = 1;
1667 void omap2_gpio_resume_after_retention(void)
1671 if (!workaround_enabled)
1673 for (i = 0; i < gpio_bank_count; i++) {
1674 struct gpio_bank *bank = &gpio_bank[i];
1677 if (!(bank->enabled_non_wakeup_gpios))
1679 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1680 __raw_writel(bank->saved_fallingdetect,
1681 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1682 __raw_writel(bank->saved_risingdetect,
1683 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1685 /* Check if any of the non-wakeup interrupt GPIOs have changed
1686 * state. If so, generate an IRQ by software. This is
1687 * horribly racy, but it's the best we can do to work around
1688 * this silicon bug. */
1689 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1690 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1692 l ^= bank->saved_datain;
1693 l &= bank->non_wakeup_gpios;
1696 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1697 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1698 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1699 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1700 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1701 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1702 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1712 * This may get called early from board specific init
1713 * for boards that have interrupts routed via FPGA.
1715 int __init omap_gpio_init(void)
1718 return _omap_gpio_init();
1723 static int __init omap_gpio_sysinit(void)
1728 ret = _omap_gpio_init();
1732 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1733 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1735 ret = sysdev_class_register(&omap_gpio_sysclass);
1737 ret = sysdev_register(&omap_gpio_device);
1745 EXPORT_SYMBOL(omap_request_gpio);
1746 EXPORT_SYMBOL(omap_free_gpio);
1747 EXPORT_SYMBOL(omap_set_gpio_direction);
1748 EXPORT_SYMBOL(omap_set_gpio_dataout);
1749 EXPORT_SYMBOL(omap_get_gpio_datain);
1751 arch_initcall(omap_gpio_sysinit);
1754 #ifdef CONFIG_DEBUG_FS
1756 #include <linux/debugfs.h>
1757 #include <linux/seq_file.h>
1759 static int gpio_is_input(struct gpio_bank *bank, int mask)
1761 void __iomem *reg = bank->base;
1763 switch (bank->method) {
1765 reg += OMAP_MPUIO_IO_CNTL;
1767 case METHOD_GPIO_1510:
1768 reg += OMAP1510_GPIO_DIR_CONTROL;
1770 case METHOD_GPIO_1610:
1771 reg += OMAP1610_GPIO_DIRECTION;
1773 case METHOD_GPIO_730:
1774 reg += OMAP730_GPIO_DIR_CONTROL;
1776 case METHOD_GPIO_24XX:
1777 reg += OMAP24XX_GPIO_OE;
1780 return __raw_readl(reg) & mask;
1784 static int dbg_gpio_show(struct seq_file *s, void *unused)
1786 unsigned i, j, gpio;
1788 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1789 struct gpio_bank *bank = gpio_bank + i;
1790 unsigned bankwidth = 16;
1793 if (bank_is_mpuio(bank))
1794 gpio = OMAP_MPUIO(0);
1795 else if (cpu_class_is_omap2() || cpu_is_omap730())
1798 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1799 unsigned irq, value, is_in, irqstat;
1802 label = gpiochip_is_requested(&bank->chip, j);
1806 irq = bank->virtual_irq_start + j;
1807 value = omap_get_gpio_datain(gpio);
1808 is_in = gpio_is_input(bank, mask);
1810 if (bank_is_mpuio(bank))
1811 seq_printf(s, "MPUIO %2d ", j);
1813 seq_printf(s, "GPIO %3d ", gpio);
1814 seq_printf(s, "(%10s): %s %s",
1816 is_in ? "in " : "out",
1817 value ? "hi" : "lo");
1819 /* FIXME for at least omap2, show pullup/pulldown state */
1821 irqstat = irq_desc[irq].status;
1822 if (is_in && ((bank->suspend_wakeup & mask)
1823 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1824 char *trigger = NULL;
1826 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1827 case IRQ_TYPE_EDGE_FALLING:
1828 trigger = "falling";
1830 case IRQ_TYPE_EDGE_RISING:
1833 case IRQ_TYPE_EDGE_BOTH:
1834 trigger = "bothedge";
1836 case IRQ_TYPE_LEVEL_LOW:
1839 case IRQ_TYPE_LEVEL_HIGH:
1846 seq_printf(s, ", irq-%d %-8s%s",
1848 (bank->suspend_wakeup & mask)
1851 seq_printf(s, "\n");
1854 if (bank_is_mpuio(bank)) {
1855 seq_printf(s, "\n");
1862 static int dbg_gpio_open(struct inode *inode, struct file *file)
1864 return single_open(file, dbg_gpio_show, &inode->i_private);
1867 static const struct file_operations debug_fops = {
1868 .open = dbg_gpio_open,
1870 .llseek = seq_lseek,
1871 .release = single_release,
1874 static int __init omap_gpio_debuginit(void)
1876 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1877 NULL, NULL, &debug_fops);
1880 late_initcall(omap_gpio_debuginit);