2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * OMAP850 specific GPIO registers
86 #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
87 #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
88 #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
89 #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
90 #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
91 #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
92 #define OMAP850_GPIO_DATA_INPUT 0x00
93 #define OMAP850_GPIO_DATA_OUTPUT 0x04
94 #define OMAP850_GPIO_DIR_CONTROL 0x08
95 #define OMAP850_GPIO_INT_CONTROL 0x0c
96 #define OMAP850_GPIO_INT_MASK 0x10
97 #define OMAP850_GPIO_INT_STATUS 0x14
100 * omap24xx specific GPIO registers
102 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
103 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
104 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
105 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
107 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
108 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
109 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
110 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
111 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
113 #define OMAP24XX_GPIO_REVISION 0x0000
114 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
115 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
116 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
117 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
118 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
119 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
120 #define OMAP24XX_GPIO_WAKE_EN 0x0020
121 #define OMAP24XX_GPIO_CTRL 0x0030
122 #define OMAP24XX_GPIO_OE 0x0034
123 #define OMAP24XX_GPIO_DATAIN 0x0038
124 #define OMAP24XX_GPIO_DATAOUT 0x003c
125 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
126 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
127 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
128 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
129 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
130 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
131 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
132 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
133 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
134 #define OMAP24XX_GPIO_SETWKUENA 0x0084
135 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
136 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
139 * omap34xx specific GPIO registers
142 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
143 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
144 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
145 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
146 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
147 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
149 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
154 u16 virtual_irq_start;
156 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
160 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
161 u32 non_wakeup_gpios;
162 u32 enabled_non_wakeup_gpios;
165 u32 saved_fallingdetect;
166 u32 saved_risingdetect;
170 struct gpio_chip chip;
174 #define METHOD_MPUIO 0
175 #define METHOD_GPIO_1510 1
176 #define METHOD_GPIO_1610 2
177 #define METHOD_GPIO_730 3
178 #define METHOD_GPIO_850 4
179 #define METHOD_GPIO_24XX 5
181 #ifdef CONFIG_ARCH_OMAP16XX
182 static struct gpio_bank gpio_bank_1610[5] = {
183 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
184 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
185 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
186 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
187 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
191 #ifdef CONFIG_ARCH_OMAP15XX
192 static struct gpio_bank gpio_bank_1510[2] = {
193 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
194 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
198 #ifdef CONFIG_ARCH_OMAP730
199 static struct gpio_bank gpio_bank_730[7] = {
200 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
201 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
202 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
203 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
204 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
205 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
206 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
210 #ifdef CONFIG_ARCH_OMAP850
211 static struct gpio_bank gpio_bank_850[7] = {
212 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
213 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
214 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
215 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
216 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
217 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
218 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
223 #ifdef CONFIG_ARCH_OMAP24XX
225 static struct gpio_bank gpio_bank_242x[4] = {
226 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
227 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
228 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
229 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
232 static struct gpio_bank gpio_bank_243x[5] = {
233 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
234 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
235 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
236 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
237 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
242 #ifdef CONFIG_ARCH_OMAP34XX
243 static struct gpio_bank gpio_bank_34xx[6] = {
244 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
245 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
246 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
247 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
248 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
249 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
254 static struct gpio_bank *gpio_bank;
255 static int gpio_bank_count;
257 static inline struct gpio_bank *get_gpio_bank(int gpio)
259 if (cpu_is_omap15xx()) {
260 if (OMAP_GPIO_IS_MPUIO(gpio))
261 return &gpio_bank[0];
262 return &gpio_bank[1];
264 if (cpu_is_omap16xx()) {
265 if (OMAP_GPIO_IS_MPUIO(gpio))
266 return &gpio_bank[0];
267 return &gpio_bank[1 + (gpio >> 4)];
269 if (cpu_is_omap7xx()) {
270 if (OMAP_GPIO_IS_MPUIO(gpio))
271 return &gpio_bank[0];
272 return &gpio_bank[1 + (gpio >> 5)];
274 if (cpu_is_omap24xx())
275 return &gpio_bank[gpio >> 5];
276 if (cpu_is_omap34xx())
277 return &gpio_bank[gpio >> 5];
282 static inline int get_gpio_index(int gpio)
284 if (cpu_is_omap7xx())
286 if (cpu_is_omap24xx())
288 if (cpu_is_omap34xx())
293 static inline int gpio_valid(int gpio)
297 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
298 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
302 if (cpu_is_omap15xx() && gpio < 16)
304 if ((cpu_is_omap16xx()) && gpio < 64)
306 if (cpu_is_omap7xx() && gpio < 192)
308 if (cpu_is_omap24xx() && gpio < 128)
310 if (cpu_is_omap34xx() && gpio < 160)
315 static int check_gpio(int gpio)
317 if (unlikely(gpio_valid(gpio)) < 0) {
318 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
325 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
327 void __iomem *reg = bank->base;
330 switch (bank->method) {
331 #ifdef CONFIG_ARCH_OMAP1
333 reg += OMAP_MPUIO_IO_CNTL;
336 #ifdef CONFIG_ARCH_OMAP15XX
337 case METHOD_GPIO_1510:
338 reg += OMAP1510_GPIO_DIR_CONTROL;
341 #ifdef CONFIG_ARCH_OMAP16XX
342 case METHOD_GPIO_1610:
343 reg += OMAP1610_GPIO_DIRECTION;
346 #ifdef CONFIG_ARCH_OMAP730
347 case METHOD_GPIO_730:
348 reg += OMAP730_GPIO_DIR_CONTROL;
351 #ifdef CONFIG_ARCH_OMAP850
352 case METHOD_GPIO_850:
353 reg += OMAP850_GPIO_DIR_CONTROL;
356 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
357 case METHOD_GPIO_24XX:
358 reg += OMAP24XX_GPIO_OE;
365 l = __raw_readl(reg);
370 __raw_writel(l, reg);
373 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
375 void __iomem *reg = bank->base;
378 switch (bank->method) {
379 #ifdef CONFIG_ARCH_OMAP1
381 reg += OMAP_MPUIO_OUTPUT;
382 l = __raw_readl(reg);
389 #ifdef CONFIG_ARCH_OMAP15XX
390 case METHOD_GPIO_1510:
391 reg += OMAP1510_GPIO_DATA_OUTPUT;
392 l = __raw_readl(reg);
399 #ifdef CONFIG_ARCH_OMAP16XX
400 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_SET_DATAOUT;
404 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
408 #ifdef CONFIG_ARCH_OMAP730
409 case METHOD_GPIO_730:
410 reg += OMAP730_GPIO_DATA_OUTPUT;
411 l = __raw_readl(reg);
418 #ifdef CONFIG_ARCH_OMAP850
419 case METHOD_GPIO_850:
420 reg += OMAP850_GPIO_DATA_OUTPUT;
421 l = __raw_readl(reg);
428 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
429 case METHOD_GPIO_24XX:
431 reg += OMAP24XX_GPIO_SETDATAOUT;
433 reg += OMAP24XX_GPIO_CLEARDATAOUT;
441 __raw_writel(l, reg);
444 static int __omap_get_gpio_datain(int gpio)
446 struct gpio_bank *bank;
449 if (check_gpio(gpio) < 0)
451 bank = get_gpio_bank(gpio);
453 switch (bank->method) {
454 #ifdef CONFIG_ARCH_OMAP1
456 reg += OMAP_MPUIO_INPUT_LATCH;
459 #ifdef CONFIG_ARCH_OMAP15XX
460 case METHOD_GPIO_1510:
461 reg += OMAP1510_GPIO_DATA_INPUT;
464 #ifdef CONFIG_ARCH_OMAP16XX
465 case METHOD_GPIO_1610:
466 reg += OMAP1610_GPIO_DATAIN;
469 #ifdef CONFIG_ARCH_OMAP730
470 case METHOD_GPIO_730:
471 reg += OMAP730_GPIO_DATA_INPUT;
474 #ifdef CONFIG_ARCH_OMAP850
475 case METHOD_GPIO_850:
476 reg += OMAP850_GPIO_DATA_INPUT;
479 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
480 case METHOD_GPIO_24XX:
481 reg += OMAP24XX_GPIO_DATAIN;
487 return (__raw_readl(reg)
488 & (1 << get_gpio_index(gpio))) != 0;
491 #define MOD_REG_BIT(reg, bit_mask, set) \
493 int l = __raw_readl(base + reg); \
494 if (set) l |= bit_mask; \
495 else l &= ~bit_mask; \
496 __raw_writel(l, base + reg); \
499 void omap_set_gpio_debounce(int gpio, int enable)
501 struct gpio_bank *bank;
504 u32 val, l = 1 << get_gpio_index(gpio);
506 if (cpu_class_is_omap1())
509 bank = get_gpio_bank(gpio);
511 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
513 spin_lock_irqsave(&bank->lock, flags);
514 val = __raw_readl(reg);
516 if (enable && !(val & l))
518 else if (!enable && (val & l))
523 if (cpu_is_omap34xx()) {
525 clk_enable(bank->dbck);
527 clk_disable(bank->dbck);
530 __raw_writel(val, reg);
532 spin_unlock_irqrestore(&bank->lock, flags);
534 EXPORT_SYMBOL(omap_set_gpio_debounce);
536 void omap_set_gpio_debounce_time(int gpio, int enc_time)
538 struct gpio_bank *bank;
541 if (cpu_class_is_omap1())
544 bank = get_gpio_bank(gpio);
548 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
549 __raw_writel(enc_time, reg);
551 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
553 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
554 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
557 void __iomem *base = bank->base;
558 u32 gpio_bit = 1 << gpio;
560 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
561 trigger & IRQ_TYPE_LEVEL_LOW);
562 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
563 trigger & IRQ_TYPE_LEVEL_HIGH);
564 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
565 trigger & IRQ_TYPE_EDGE_RISING);
566 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
567 trigger & IRQ_TYPE_EDGE_FALLING);
569 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
571 __raw_writel(1 << gpio, bank->base
572 + OMAP24XX_GPIO_SETWKUENA);
574 __raw_writel(1 << gpio, bank->base
575 + OMAP24XX_GPIO_CLEARWKUENA);
578 bank->enabled_non_wakeup_gpios |= gpio_bit;
580 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
584 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
585 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
589 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
591 void __iomem *reg = bank->base;
594 switch (bank->method) {
595 #ifdef CONFIG_ARCH_OMAP1
597 reg += OMAP_MPUIO_GPIO_INT_EDGE;
598 l = __raw_readl(reg);
599 if (trigger & IRQ_TYPE_EDGE_RISING)
601 else if (trigger & IRQ_TYPE_EDGE_FALLING)
607 #ifdef CONFIG_ARCH_OMAP15XX
608 case METHOD_GPIO_1510:
609 reg += OMAP1510_GPIO_INT_CONTROL;
610 l = __raw_readl(reg);
611 if (trigger & IRQ_TYPE_EDGE_RISING)
613 else if (trigger & IRQ_TYPE_EDGE_FALLING)
619 #ifdef CONFIG_ARCH_OMAP16XX
620 case METHOD_GPIO_1610:
622 reg += OMAP1610_GPIO_EDGE_CTRL2;
624 reg += OMAP1610_GPIO_EDGE_CTRL1;
626 l = __raw_readl(reg);
627 l &= ~(3 << (gpio << 1));
628 if (trigger & IRQ_TYPE_EDGE_RISING)
629 l |= 2 << (gpio << 1);
630 if (trigger & IRQ_TYPE_EDGE_FALLING)
631 l |= 1 << (gpio << 1);
633 /* Enable wake-up during idle for dynamic tick */
634 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
636 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
639 #ifdef CONFIG_ARCH_OMAP730
640 case METHOD_GPIO_730:
641 reg += OMAP730_GPIO_INT_CONTROL;
642 l = __raw_readl(reg);
643 if (trigger & IRQ_TYPE_EDGE_RISING)
645 else if (trigger & IRQ_TYPE_EDGE_FALLING)
651 #ifdef CONFIG_ARCH_OMAP850
652 case METHOD_GPIO_850:
653 reg += OMAP850_GPIO_INT_CONTROL;
654 l = __raw_readl(reg);
655 if (trigger & IRQ_TYPE_EDGE_RISING)
657 else if (trigger & IRQ_TYPE_EDGE_FALLING)
663 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
664 case METHOD_GPIO_24XX:
665 set_24xx_gpio_triggering(bank, gpio, trigger);
671 __raw_writel(l, reg);
677 static int gpio_irq_type(unsigned irq, unsigned type)
679 struct gpio_bank *bank;
684 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
685 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
687 gpio = irq - IH_GPIO_BASE;
689 if (check_gpio(gpio) < 0)
692 if (type & ~IRQ_TYPE_SENSE_MASK)
695 /* OMAP1 allows only only edge triggering */
696 if (!cpu_class_is_omap2()
697 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
700 bank = get_irq_chip_data(irq);
701 spin_lock_irqsave(&bank->lock, flags);
702 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
704 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
705 irq_desc[irq].status |= type;
707 spin_unlock_irqrestore(&bank->lock, flags);
709 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
710 __set_irq_handler_unlocked(irq, handle_level_irq);
711 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
712 __set_irq_handler_unlocked(irq, handle_edge_irq);
717 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
719 void __iomem *reg = bank->base;
721 switch (bank->method) {
722 #ifdef CONFIG_ARCH_OMAP1
724 /* MPUIO irqstatus is reset by reading the status register,
725 * so do nothing here */
728 #ifdef CONFIG_ARCH_OMAP15XX
729 case METHOD_GPIO_1510:
730 reg += OMAP1510_GPIO_INT_STATUS;
733 #ifdef CONFIG_ARCH_OMAP16XX
734 case METHOD_GPIO_1610:
735 reg += OMAP1610_GPIO_IRQSTATUS1;
738 #ifdef CONFIG_ARCH_OMAP730
739 case METHOD_GPIO_730:
740 reg += OMAP730_GPIO_INT_STATUS;
743 #ifdef CONFIG_ARCH_OMAP850
744 case METHOD_GPIO_850:
745 reg += OMAP850_GPIO_INT_STATUS;
748 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
749 case METHOD_GPIO_24XX:
750 reg += OMAP24XX_GPIO_IRQSTATUS1;
757 __raw_writel(gpio_mask, reg);
759 /* Workaround for clearing DSP GPIO interrupts to allow retention */
760 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
761 if (cpu_is_omap24xx() || cpu_is_omap34xx())
762 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
766 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
768 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
771 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
773 void __iomem *reg = bank->base;
778 switch (bank->method) {
779 #ifdef CONFIG_ARCH_OMAP1
781 reg += OMAP_MPUIO_GPIO_MASKIT;
786 #ifdef CONFIG_ARCH_OMAP15XX
787 case METHOD_GPIO_1510:
788 reg += OMAP1510_GPIO_INT_MASK;
793 #ifdef CONFIG_ARCH_OMAP16XX
794 case METHOD_GPIO_1610:
795 reg += OMAP1610_GPIO_IRQENABLE1;
799 #ifdef CONFIG_ARCH_OMAP730
800 case METHOD_GPIO_730:
801 reg += OMAP730_GPIO_INT_MASK;
806 #ifdef CONFIG_ARCH_OMAP850
807 case METHOD_GPIO_850:
808 reg += OMAP850_GPIO_INT_MASK;
813 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
814 case METHOD_GPIO_24XX:
815 reg += OMAP24XX_GPIO_IRQENABLE1;
824 l = __raw_readl(reg);
831 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
833 void __iomem *reg = bank->base;
836 switch (bank->method) {
837 #ifdef CONFIG_ARCH_OMAP1
839 reg += OMAP_MPUIO_GPIO_MASKIT;
840 l = __raw_readl(reg);
847 #ifdef CONFIG_ARCH_OMAP15XX
848 case METHOD_GPIO_1510:
849 reg += OMAP1510_GPIO_INT_MASK;
850 l = __raw_readl(reg);
857 #ifdef CONFIG_ARCH_OMAP16XX
858 case METHOD_GPIO_1610:
860 reg += OMAP1610_GPIO_SET_IRQENABLE1;
862 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
866 #ifdef CONFIG_ARCH_OMAP730
867 case METHOD_GPIO_730:
868 reg += OMAP730_GPIO_INT_MASK;
869 l = __raw_readl(reg);
876 #ifdef CONFIG_ARCH_OMAP850
877 case METHOD_GPIO_850:
878 reg += OMAP850_GPIO_INT_MASK;
879 l = __raw_readl(reg);
886 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
887 case METHOD_GPIO_24XX:
889 reg += OMAP24XX_GPIO_SETIRQENABLE1;
891 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
899 __raw_writel(l, reg);
902 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
904 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
908 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
909 * 1510 does not seem to have a wake-up register. If JTAG is connected
910 * to the target, system will wake up always on GPIO events. While
911 * system is running all registered GPIO interrupts need to have wake-up
912 * enabled. When system is suspended, only selected GPIO interrupts need
913 * to have wake-up enabled.
915 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
919 switch (bank->method) {
920 #ifdef CONFIG_ARCH_OMAP16XX
922 case METHOD_GPIO_1610:
923 spin_lock_irqsave(&bank->lock, flags);
925 bank->suspend_wakeup |= (1 << gpio);
927 bank->suspend_wakeup &= ~(1 << gpio);
928 spin_unlock_irqrestore(&bank->lock, flags);
931 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
932 case METHOD_GPIO_24XX:
933 if (bank->non_wakeup_gpios & (1 << gpio)) {
934 printk(KERN_ERR "Unable to modify wakeup on "
935 "non-wakeup GPIO%d\n",
936 (bank - gpio_bank) * 32 + gpio);
939 spin_lock_irqsave(&bank->lock, flags);
941 bank->suspend_wakeup |= (1 << gpio);
943 bank->suspend_wakeup &= ~(1 << gpio);
944 spin_unlock_irqrestore(&bank->lock, flags);
948 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
954 static void _reset_gpio(struct gpio_bank *bank, int gpio)
956 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
957 _set_gpio_irqenable(bank, gpio, 0);
958 _clear_gpio_irqstatus(bank, gpio);
959 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
962 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
963 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
965 unsigned int gpio = irq - IH_GPIO_BASE;
966 struct gpio_bank *bank;
969 if (check_gpio(gpio) < 0)
971 bank = get_irq_chip_data(irq);
972 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
977 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
979 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
982 spin_lock_irqsave(&bank->lock, flags);
984 /* Set trigger to none. You need to enable the desired trigger with
985 * request_irq() or set_irq_type().
987 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
989 #ifdef CONFIG_ARCH_OMAP15XX
990 if (bank->method == METHOD_GPIO_1510) {
993 /* Claim the pin for MPU */
994 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
995 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
998 spin_unlock_irqrestore(&bank->lock, flags);
1003 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1005 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1006 unsigned long flags;
1008 spin_lock_irqsave(&bank->lock, flags);
1009 #ifdef CONFIG_ARCH_OMAP16XX
1010 if (bank->method == METHOD_GPIO_1610) {
1011 /* Disable wake-up during idle for dynamic tick */
1012 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1013 __raw_writel(1 << offset, reg);
1016 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1017 if (bank->method == METHOD_GPIO_24XX) {
1018 /* Disable wake-up during idle for dynamic tick */
1019 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1020 __raw_writel(1 << offset, reg);
1023 _reset_gpio(bank, bank->chip.base + offset);
1024 spin_unlock_irqrestore(&bank->lock, flags);
1028 * We need to unmask the GPIO bank interrupt as soon as possible to
1029 * avoid missing GPIO interrupts for other lines in the bank.
1030 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1031 * in the bank to avoid missing nested interrupts for a GPIO line.
1032 * If we wait to unmask individual GPIO lines in the bank after the
1033 * line's interrupt handler has been run, we may miss some nested
1036 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1038 void __iomem *isr_reg = NULL;
1040 unsigned int gpio_irq;
1041 struct gpio_bank *bank;
1045 desc->chip->ack(irq);
1047 bank = get_irq_data(irq);
1048 #ifdef CONFIG_ARCH_OMAP1
1049 if (bank->method == METHOD_MPUIO)
1050 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1052 #ifdef CONFIG_ARCH_OMAP15XX
1053 if (bank->method == METHOD_GPIO_1510)
1054 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1056 #if defined(CONFIG_ARCH_OMAP16XX)
1057 if (bank->method == METHOD_GPIO_1610)
1058 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1060 #ifdef CONFIG_ARCH_OMAP730
1061 if (bank->method == METHOD_GPIO_730)
1062 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1064 #ifdef CONFIG_ARCH_OMAP850
1065 if (bank->method == METHOD_GPIO_850)
1066 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1068 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1069 if (bank->method == METHOD_GPIO_24XX)
1070 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1073 u32 isr_saved, level_mask = 0;
1076 enabled = _get_gpio_irqbank_mask(bank);
1077 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1079 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1082 if (cpu_class_is_omap2()) {
1083 level_mask = bank->level_mask & enabled;
1086 /* clear edge sensitive interrupts before handler(s) are
1087 called so that we don't miss any interrupt occurred while
1089 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1090 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1091 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1093 /* if there is only edge sensitive GPIO pin interrupts
1094 configured, we could unmask GPIO bank interrupt immediately */
1095 if (!level_mask && !unmasked) {
1097 desc->chip->unmask(irq);
1105 gpio_irq = bank->virtual_irq_start;
1106 for (; isr != 0; isr >>= 1, gpio_irq++) {
1110 generic_handle_irq(gpio_irq);
1113 /* if bank has any level sensitive GPIO pin interrupt
1114 configured, we must unmask the bank interrupt only after
1115 handler(s) are executed in order to avoid spurious bank
1118 desc->chip->unmask(irq);
1122 static void gpio_irq_shutdown(unsigned int irq)
1124 unsigned int gpio = irq - IH_GPIO_BASE;
1125 struct gpio_bank *bank = get_irq_chip_data(irq);
1127 _reset_gpio(bank, gpio);
1130 static void gpio_ack_irq(unsigned int irq)
1132 unsigned int gpio = irq - IH_GPIO_BASE;
1133 struct gpio_bank *bank = get_irq_chip_data(irq);
1135 _clear_gpio_irqstatus(bank, gpio);
1138 static void gpio_mask_irq(unsigned int irq)
1140 unsigned int gpio = irq - IH_GPIO_BASE;
1141 struct gpio_bank *bank = get_irq_chip_data(irq);
1143 _set_gpio_irqenable(bank, gpio, 0);
1146 static void gpio_unmask_irq(unsigned int irq)
1148 unsigned int gpio = irq - IH_GPIO_BASE;
1149 struct gpio_bank *bank = get_irq_chip_data(irq);
1150 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1152 /* For level-triggered GPIOs, the clearing must be done after
1153 * the HW source is cleared, thus after the handler has run */
1154 if (bank->level_mask & irq_mask) {
1155 _set_gpio_irqenable(bank, gpio, 0);
1156 _clear_gpio_irqstatus(bank, gpio);
1159 _set_gpio_irqenable(bank, gpio, 1);
1162 static struct irq_chip gpio_irq_chip = {
1164 .shutdown = gpio_irq_shutdown,
1165 .ack = gpio_ack_irq,
1166 .mask = gpio_mask_irq,
1167 .unmask = gpio_unmask_irq,
1168 .set_type = gpio_irq_type,
1169 .set_wake = gpio_wake_enable,
1172 /*---------------------------------------------------------------------*/
1174 #ifdef CONFIG_ARCH_OMAP1
1176 /* MPUIO uses the always-on 32k clock */
1178 static void mpuio_ack_irq(unsigned int irq)
1180 /* The ISR is reset automatically, so do nothing here. */
1183 static void mpuio_mask_irq(unsigned int irq)
1185 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1186 struct gpio_bank *bank = get_irq_chip_data(irq);
1188 _set_gpio_irqenable(bank, gpio, 0);
1191 static void mpuio_unmask_irq(unsigned int irq)
1193 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1194 struct gpio_bank *bank = get_irq_chip_data(irq);
1196 _set_gpio_irqenable(bank, gpio, 1);
1199 static struct irq_chip mpuio_irq_chip = {
1201 .ack = mpuio_ack_irq,
1202 .mask = mpuio_mask_irq,
1203 .unmask = mpuio_unmask_irq,
1204 .set_type = gpio_irq_type,
1205 #ifdef CONFIG_ARCH_OMAP16XX
1206 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1207 .set_wake = gpio_wake_enable,
1212 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1215 #ifdef CONFIG_ARCH_OMAP16XX
1217 #include <linux/platform_device.h>
1219 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1221 struct gpio_bank *bank = platform_get_drvdata(pdev);
1222 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1223 unsigned long flags;
1225 spin_lock_irqsave(&bank->lock, flags);
1226 bank->saved_wakeup = __raw_readl(mask_reg);
1227 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1228 spin_unlock_irqrestore(&bank->lock, flags);
1233 static int omap_mpuio_resume_early(struct platform_device *pdev)
1235 struct gpio_bank *bank = platform_get_drvdata(pdev);
1236 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1237 unsigned long flags;
1239 spin_lock_irqsave(&bank->lock, flags);
1240 __raw_writel(bank->saved_wakeup, mask_reg);
1241 spin_unlock_irqrestore(&bank->lock, flags);
1246 /* use platform_driver for this, now that there's no longer any
1247 * point to sys_device (other than not disturbing old code).
1249 static struct platform_driver omap_mpuio_driver = {
1250 .suspend_late = omap_mpuio_suspend_late,
1251 .resume_early = omap_mpuio_resume_early,
1257 static struct platform_device omap_mpuio_device = {
1261 .driver = &omap_mpuio_driver.driver,
1263 /* could list the /proc/iomem resources */
1266 static inline void mpuio_init(void)
1268 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1270 if (platform_driver_register(&omap_mpuio_driver) == 0)
1271 (void) platform_device_register(&omap_mpuio_device);
1275 static inline void mpuio_init(void) {}
1280 extern struct irq_chip mpuio_irq_chip;
1282 #define bank_is_mpuio(bank) 0
1283 static inline void mpuio_init(void) {}
1287 /*---------------------------------------------------------------------*/
1289 /* REVISIT these are stupid implementations! replace by ones that
1290 * don't switch on METHOD_* and which mostly avoid spinlocks
1293 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1295 struct gpio_bank *bank;
1296 unsigned long flags;
1298 bank = container_of(chip, struct gpio_bank, chip);
1299 spin_lock_irqsave(&bank->lock, flags);
1300 _set_gpio_direction(bank, offset, 1);
1301 spin_unlock_irqrestore(&bank->lock, flags);
1305 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1307 return __omap_get_gpio_datain(chip->base + offset);
1310 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1312 struct gpio_bank *bank;
1313 unsigned long flags;
1315 bank = container_of(chip, struct gpio_bank, chip);
1316 spin_lock_irqsave(&bank->lock, flags);
1317 _set_gpio_dataout(bank, offset, value);
1318 _set_gpio_direction(bank, offset, 0);
1319 spin_unlock_irqrestore(&bank->lock, flags);
1323 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1325 struct gpio_bank *bank;
1326 unsigned long flags;
1328 bank = container_of(chip, struct gpio_bank, chip);
1329 spin_lock_irqsave(&bank->lock, flags);
1330 _set_gpio_dataout(bank, offset, value);
1331 spin_unlock_irqrestore(&bank->lock, flags);
1334 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1336 struct gpio_bank *bank;
1338 bank = container_of(chip, struct gpio_bank, chip);
1339 return bank->virtual_irq_start + offset;
1342 /*---------------------------------------------------------------------*/
1344 static int initialized;
1345 #if !defined(CONFIG_ARCH_OMAP3)
1346 static struct clk * gpio_ick;
1349 #if defined(CONFIG_ARCH_OMAP2)
1350 static struct clk * gpio_fck;
1353 #if defined(CONFIG_ARCH_OMAP2430)
1354 static struct clk * gpio5_ick;
1355 static struct clk * gpio5_fck;
1358 #if defined(CONFIG_ARCH_OMAP3)
1359 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1362 /* This lock class tells lockdep that GPIO irqs are in a different
1363 * category than their parents, so it won't report false recursion.
1365 static struct lock_class_key gpio_lock_class;
1367 static int __init _omap_gpio_init(void)
1371 struct gpio_bank *bank;
1376 #if defined(CONFIG_ARCH_OMAP1)
1377 if (cpu_is_omap15xx()) {
1378 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1379 if (IS_ERR(gpio_ick))
1380 printk("Could not get arm_gpio_ck\n");
1382 clk_enable(gpio_ick);
1385 #if defined(CONFIG_ARCH_OMAP2)
1386 if (cpu_class_is_omap2()) {
1387 gpio_ick = clk_get(NULL, "gpios_ick");
1388 if (IS_ERR(gpio_ick))
1389 printk("Could not get gpios_ick\n");
1391 clk_enable(gpio_ick);
1392 gpio_fck = clk_get(NULL, "gpios_fck");
1393 if (IS_ERR(gpio_fck))
1394 printk("Could not get gpios_fck\n");
1396 clk_enable(gpio_fck);
1399 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1401 #if defined(CONFIG_ARCH_OMAP2430)
1402 if (cpu_is_omap2430()) {
1403 gpio5_ick = clk_get(NULL, "gpio5_ick");
1404 if (IS_ERR(gpio5_ick))
1405 printk("Could not get gpio5_ick\n");
1407 clk_enable(gpio5_ick);
1408 gpio5_fck = clk_get(NULL, "gpio5_fck");
1409 if (IS_ERR(gpio5_fck))
1410 printk("Could not get gpio5_fck\n");
1412 clk_enable(gpio5_fck);
1418 #if defined(CONFIG_ARCH_OMAP3)
1419 if (cpu_is_omap34xx()) {
1420 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1421 sprintf(clk_name, "gpio%d_ick", i + 1);
1422 gpio_iclks[i] = clk_get(NULL, clk_name);
1423 if (IS_ERR(gpio_iclks[i]))
1424 printk(KERN_ERR "Could not get %s\n", clk_name);
1426 clk_enable(gpio_iclks[i]);
1432 #ifdef CONFIG_ARCH_OMAP15XX
1433 if (cpu_is_omap15xx()) {
1434 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1435 gpio_bank_count = 2;
1436 gpio_bank = gpio_bank_1510;
1439 #if defined(CONFIG_ARCH_OMAP16XX)
1440 if (cpu_is_omap16xx()) {
1443 gpio_bank_count = 5;
1444 gpio_bank = gpio_bank_1610;
1445 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f);
1450 #ifdef CONFIG_ARCH_OMAP730
1451 if (cpu_is_omap730()) {
1452 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1453 gpio_bank_count = 7;
1454 gpio_bank = gpio_bank_730;
1457 #ifdef CONFIG_ARCH_OMAP850
1458 if (cpu_is_omap850()) {
1459 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1460 gpio_bank_count = 7;
1461 gpio_bank = gpio_bank_850;
1465 #ifdef CONFIG_ARCH_OMAP24XX
1466 if (cpu_is_omap242x()) {
1469 gpio_bank_count = 4;
1470 gpio_bank = gpio_bank_242x;
1471 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1472 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1473 (rev >> 4) & 0x0f, rev & 0x0f);
1475 if (cpu_is_omap243x()) {
1478 gpio_bank_count = 5;
1479 gpio_bank = gpio_bank_243x;
1480 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1481 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1482 (rev >> 4) & 0x0f, rev & 0x0f);
1485 #ifdef CONFIG_ARCH_OMAP34XX
1486 if (cpu_is_omap34xx()) {
1489 gpio_bank_count = OMAP34XX_NR_GPIOS;
1490 gpio_bank = gpio_bank_34xx;
1491 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1492 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1493 (rev >> 4) & 0x0f, rev & 0x0f);
1496 for (i = 0; i < gpio_bank_count; i++) {
1497 int j, gpio_count = 16;
1499 bank = &gpio_bank[i];
1500 spin_lock_init(&bank->lock);
1501 if (bank_is_mpuio(bank))
1502 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1503 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1504 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1505 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1507 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1508 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1509 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1510 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1512 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1513 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1514 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1516 gpio_count = 32; /* 730 has 32-bit GPIOs */
1519 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1520 if (bank->method == METHOD_GPIO_24XX) {
1521 static const u32 non_wakeup_gpios[] = {
1522 0xe203ffc0, 0x08700040
1525 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1526 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1527 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1529 /* Initialize interface clock ungated, module enabled */
1530 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1531 if (i < ARRAY_SIZE(non_wakeup_gpios))
1532 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1537 /* REVISIT eventually switch from OMAP-specific gpio structs
1538 * over to the generic ones
1540 bank->chip.request = omap_gpio_request;
1541 bank->chip.free = omap_gpio_free;
1542 bank->chip.direction_input = gpio_input;
1543 bank->chip.get = gpio_get;
1544 bank->chip.direction_output = gpio_output;
1545 bank->chip.set = gpio_set;
1546 bank->chip.to_irq = gpio_2irq;
1547 if (bank_is_mpuio(bank)) {
1548 bank->chip.label = "mpuio";
1549 #ifdef CONFIG_ARCH_OMAP16XX
1550 bank->chip.dev = &omap_mpuio_device.dev;
1552 bank->chip.base = OMAP_MPUIO(0);
1554 bank->chip.label = "gpio";
1555 bank->chip.base = gpio;
1558 bank->chip.ngpio = gpio_count;
1560 gpiochip_add(&bank->chip);
1562 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + gpio_count; j++) {
1564 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1565 set_irq_chip_data(j, bank);
1566 if (bank_is_mpuio(bank))
1567 set_irq_chip(j, &mpuio_irq_chip);
1569 set_irq_chip(j, &gpio_irq_chip);
1570 set_irq_handler(j, handle_simple_irq);
1571 set_irq_flags(j, IRQF_VALID);
1573 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1574 set_irq_data(bank->irq, bank);
1576 if (cpu_is_omap34xx()) {
1577 sprintf(clk_name, "gpio%d_dbck", i + 1);
1578 bank->dbck = clk_get(NULL, clk_name);
1579 if (IS_ERR(bank->dbck))
1580 printk(KERN_ERR "Could not get %s\n", clk_name);
1584 /* Enable system clock for GPIO module.
1585 * The CAM_CLK_CTRL *is* really the right place. */
1586 if (cpu_is_omap16xx())
1587 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1589 /* Enable autoidle for the OCP interface */
1590 if (cpu_is_omap24xx())
1591 omap_writel(1 << 0, 0x48019010);
1592 if (cpu_is_omap34xx())
1593 omap_writel(1 << 0, 0x48306814);
1598 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1599 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1603 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1606 for (i = 0; i < gpio_bank_count; i++) {
1607 struct gpio_bank *bank = &gpio_bank[i];
1608 void __iomem *wake_status;
1609 void __iomem *wake_clear;
1610 void __iomem *wake_set;
1611 unsigned long flags;
1613 switch (bank->method) {
1614 #ifdef CONFIG_ARCH_OMAP16XX
1615 case METHOD_GPIO_1610:
1616 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1617 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1618 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1621 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1622 case METHOD_GPIO_24XX:
1623 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1624 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1625 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1632 spin_lock_irqsave(&bank->lock, flags);
1633 bank->saved_wakeup = __raw_readl(wake_status);
1634 __raw_writel(0xffffffff, wake_clear);
1635 __raw_writel(bank->suspend_wakeup, wake_set);
1636 spin_unlock_irqrestore(&bank->lock, flags);
1642 static int omap_gpio_resume(struct sys_device *dev)
1646 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1649 for (i = 0; i < gpio_bank_count; i++) {
1650 struct gpio_bank *bank = &gpio_bank[i];
1651 void __iomem *wake_clear;
1652 void __iomem *wake_set;
1653 unsigned long flags;
1655 switch (bank->method) {
1656 #ifdef CONFIG_ARCH_OMAP16XX
1657 case METHOD_GPIO_1610:
1658 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1659 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1662 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1663 case METHOD_GPIO_24XX:
1664 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1665 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1672 spin_lock_irqsave(&bank->lock, flags);
1673 __raw_writel(0xffffffff, wake_clear);
1674 __raw_writel(bank->saved_wakeup, wake_set);
1675 spin_unlock_irqrestore(&bank->lock, flags);
1681 static struct sysdev_class omap_gpio_sysclass = {
1683 .suspend = omap_gpio_suspend,
1684 .resume = omap_gpio_resume,
1687 static struct sys_device omap_gpio_device = {
1689 .cls = &omap_gpio_sysclass,
1694 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1696 static int workaround_enabled;
1698 void omap2_gpio_prepare_for_retention(void)
1702 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1703 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1704 for (i = 0; i < gpio_bank_count; i++) {
1705 struct gpio_bank *bank = &gpio_bank[i];
1708 if (!(bank->enabled_non_wakeup_gpios))
1710 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1711 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1712 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1713 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1715 bank->saved_fallingdetect = l1;
1716 bank->saved_risingdetect = l2;
1717 l1 &= ~bank->enabled_non_wakeup_gpios;
1718 l2 &= ~bank->enabled_non_wakeup_gpios;
1719 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1720 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1721 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1726 workaround_enabled = 0;
1729 workaround_enabled = 1;
1732 void omap2_gpio_resume_after_retention(void)
1736 if (!workaround_enabled)
1738 for (i = 0; i < gpio_bank_count; i++) {
1739 struct gpio_bank *bank = &gpio_bank[i];
1742 if (!(bank->enabled_non_wakeup_gpios))
1744 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1745 __raw_writel(bank->saved_fallingdetect,
1746 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1747 __raw_writel(bank->saved_risingdetect,
1748 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1750 /* Check if any of the non-wakeup interrupt GPIOs have changed
1751 * state. If so, generate an IRQ by software. This is
1752 * horribly racy, but it's the best we can do to work around
1753 * this silicon bug. */
1754 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1755 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1757 l ^= bank->saved_datain;
1758 l &= bank->non_wakeup_gpios;
1761 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1762 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1763 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1764 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1765 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1766 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1767 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1777 * This may get called early from board specific init
1778 * for boards that have interrupts routed via FPGA.
1780 int __init omap_gpio_init(void)
1783 return _omap_gpio_init();
1788 static int __init omap_gpio_sysinit(void)
1793 ret = _omap_gpio_init();
1797 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1798 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1800 ret = sysdev_class_register(&omap_gpio_sysclass);
1802 ret = sysdev_register(&omap_gpio_device);
1810 arch_initcall(omap_gpio_sysinit);
1813 #ifdef CONFIG_DEBUG_FS
1815 #include <linux/debugfs.h>
1816 #include <linux/seq_file.h>
1818 static int gpio_is_input(struct gpio_bank *bank, int mask)
1820 void __iomem *reg = bank->base;
1822 switch (bank->method) {
1824 reg += OMAP_MPUIO_IO_CNTL;
1826 case METHOD_GPIO_1510:
1827 reg += OMAP1510_GPIO_DIR_CONTROL;
1829 case METHOD_GPIO_1610:
1830 reg += OMAP1610_GPIO_DIRECTION;
1832 case METHOD_GPIO_730:
1833 reg += OMAP730_GPIO_DIR_CONTROL;
1835 case METHOD_GPIO_850:
1836 reg += OMAP850_GPIO_DIR_CONTROL;
1838 case METHOD_GPIO_24XX:
1839 reg += OMAP24XX_GPIO_OE;
1842 return __raw_readl(reg) & mask;
1846 static int dbg_gpio_show(struct seq_file *s, void *unused)
1848 unsigned i, j, gpio;
1850 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1851 struct gpio_bank *bank = gpio_bank + i;
1852 unsigned bankwidth = 16;
1855 if (bank_is_mpuio(bank))
1856 gpio = OMAP_MPUIO(0);
1857 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1861 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1862 unsigned irq, value, is_in, irqstat;
1865 label = gpiochip_is_requested(&bank->chip, j);
1869 irq = bank->virtual_irq_start + j;
1870 value = gpio_get_value(gpio);
1871 is_in = gpio_is_input(bank, mask);
1873 if (bank_is_mpuio(bank))
1874 seq_printf(s, "MPUIO %2d ", j);
1876 seq_printf(s, "GPIO %3d ", gpio);
1877 seq_printf(s, "(%-20.20s): %s %s",
1879 is_in ? "in " : "out",
1880 value ? "hi" : "lo");
1882 /* FIXME for at least omap2, show pullup/pulldown state */
1884 irqstat = irq_desc[irq].status;
1885 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1886 defined(CONFIG_ARCH_OMAP34XX)
1887 if (is_in && ((bank->suspend_wakeup & mask)
1888 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1889 char *trigger = NULL;
1891 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1892 case IRQ_TYPE_EDGE_FALLING:
1893 trigger = "falling";
1895 case IRQ_TYPE_EDGE_RISING:
1898 case IRQ_TYPE_EDGE_BOTH:
1899 trigger = "bothedge";
1901 case IRQ_TYPE_LEVEL_LOW:
1904 case IRQ_TYPE_LEVEL_HIGH:
1911 seq_printf(s, ", irq-%d %-8s%s",
1913 (bank->suspend_wakeup & mask)
1917 seq_printf(s, "\n");
1920 if (bank_is_mpuio(bank)) {
1921 seq_printf(s, "\n");
1928 static int dbg_gpio_open(struct inode *inode, struct file *file)
1930 return single_open(file, dbg_gpio_show, &inode->i_private);
1933 static const struct file_operations debug_fops = {
1934 .open = dbg_gpio_open,
1936 .llseek = seq_lseek,
1937 .release = single_release,
1940 static int __init omap_gpio_debuginit(void)
1942 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1943 NULL, NULL, &debug_fops);
1946 late_initcall(omap_gpio_debuginit);