2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #ifndef DRIVER_DSP_COMMON_H
25 #define DRIVER_DSP_COMMON_H
27 #include "hardware_dsp.h"
29 #define DSPSPACE_SIZE 0x1000000
31 #define omap_set_bit_regw(b,r) \
32 do { omap_writew(omap_readw(r) | (b), (r)); } while(0)
33 #define omap_clr_bit_regw(b,r) \
34 do { omap_writew(omap_readw(r) & ~(b), (r)); } while(0)
35 #define omap_set_bit_regl(b,r) \
36 do { omap_writel(omap_readl(r) | (b), (r)); } while(0)
37 #define omap_clr_bit_regl(b,r) \
38 do { omap_writel(omap_readl(r) & ~(b), (r)); } while(0)
39 #define omap_set_bits_regl(val,mask,r) \
40 do { omap_writel((omap_readl(r) & ~(mask)) | (val), (r)); } while(0)
42 #define dspword_to_virt(dw) ((void *)(dspmem_base + ((dw) << 1)))
43 #define dspbyte_to_virt(db) ((void *)(dspmem_base + (db)))
44 #define virt_to_dspword(va) \
45 ((dsp_long_t)(((unsigned long)(va) - dspmem_base) >> 1))
46 #define virt_to_dspbyte(va) \
47 ((dsp_long_t)((unsigned long)(va) - dspmem_base))
48 #define is_dsp_internal_mem(va) \
49 (((unsigned long)(va) >= dspmem_base) && \
50 ((unsigned long)(va) < dspmem_base + dspmem_size))
51 #define is_dspbyte_internal_mem(db) ((db) < dspmem_size)
52 #define is_dspword_internal_mem(dw) (((dw) << 1) < dspmem_size)
54 #ifdef CONFIG_ARCH_OMAP1
56 * MPUI byteswap/wordswap on/off
57 * default setting: wordswap = all, byteswap = APIMEM only
59 #define mpui_wordswap_on() \
60 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_ALL, MPUI_CTRL_WORDSWAP_MASK, \
63 #define mpui_wordswap_off() \
64 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_NONE, MPUI_CTRL_WORDSWAP_MASK, \
67 #define mpui_byteswap_on() \
68 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_API, MPUI_CTRL_BYTESWAP_MASK, \
71 #define mpui_byteswap_off() \
72 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_NONE, MPUI_CTRL_BYTESWAP_MASK, \
76 * TC wordswap on / off
78 #define tc_wordswap() \
80 omap_writel(TC_ENDIANISM_SWAP_WORD | TC_ENDIANISM_EN, \
84 #define tc_noswap() omap_clr_bit_regl(TC_ENDIANISM_EN, TC_ENDIANISM)
87 * enable priority registers, EMIF, MPUI control logic
89 #define __dsp_enable() omap_set_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
90 #define __dsp_disable() omap_clr_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
91 #define __dsp_run() omap_set_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
92 #define __dsp_reset() omap_clr_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
93 #endif /* CONFIG_ARCH_OMAP1 */
95 #ifdef CONFIG_ARCH_OMAP2
97 * PRCM / IPI control logic
99 #define RSTCTRL_RST1_DSP 0x00000001
100 #define RSTCTRL_RST2_DSP 0x00000002
101 #define __dsp_core_enable() \
102 do { RM_RSTCTRL_DSP &= ~RSTCTRL_RST1_DSP; } while (0)
103 #define __dsp_core_disable() \
104 do { RM_RSTCTRL_DSP |= RSTCTRL_RST1_DSP; } while (0)
105 #define __dsp_per_enable() \
106 do { RM_RSTCTRL_DSP &= ~RSTCTRL_RST2_DSP; } while (0)
107 #define __dsp_per_disable() \
108 do { RM_RSTCTRL_DSP |= RSTCTRL_RST2_DSP; } while (0)
109 #endif /* CONFIG_ARCH_OMAP2 */
111 typedef u32 dsp_long_t; /* must have ability to carry TADD_ABORTADR */
113 #if defined(CONFIG_ARCH_OMAP1)
114 extern struct clk *dsp_ck_handle;
115 extern struct clk *api_ck_handle;
116 #elif defined(CONFIG_ARCH_OMAP2)
117 extern struct clk *dsp_fck_handle;
118 extern struct clk *dsp_ick_handle;
120 extern dsp_long_t dspmem_base, dspmem_size,
121 daram_base, daram_size,
122 saram_base, saram_size;
126 #ifdef CONFIG_ARCH_OMAP1
134 int dsp_set_rstvect(dsp_long_t adr);
135 dsp_long_t dsp_get_rstvect(void);
136 #ifdef CONFIG_ARCH_OMAP1
137 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size);
138 void dsp_reset_idle_boot_base(void);
140 void dsp_cpustat_request(enum cpustat_e req);
141 enum cpustat_e dsp_cpustat_get_stat(void);
142 u16 dsp_cpustat_get_icrmask(void);
143 void dsp_cpustat_set_icrmask(u16 mask);
144 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void));
145 void dsp_unregister_mem_cb(void);
147 #if defined(CONFIG_ARCH_OMAP1)
148 static inline void dsp_clk_autoidle(void) {}
149 #elif defined(CONFIG_ARCH_OMAP2)
150 static inline void dsp_clk_autoidle(void)
152 /*XXX should be handled in mach-omap[1,2] XXX*/
153 PM_PWSTCTRL_DSP = (1 << 18) | (1 << 0);
154 CM_AUTOIDLE_DSP |= (1 << 1);
155 CM_CLKSTCTRL_DSP |= (1 << 0);
159 struct dsp_kfunc_device {
166 #define DSP_KFUNC_DEV_TYPE_COMMON 1
167 #define DSP_KFUNC_DEV_TYPE_AUDIO 2
169 struct list_head entry;
171 int (*probe)(struct dsp_kfunc_device *);
172 int (*remove)(struct dsp_kfunc_device *);
173 int (*enable)(struct dsp_kfunc_device *, int);
174 int (*disable)(struct dsp_kfunc_device *, int);
177 extern int dsp_kfunc_device_register(struct dsp_kfunc_device *);
179 struct dsp_platform_data {
180 struct list_head kdev_list;
185 int enabled; /* stored peripheral status */
187 struct omap_mbox *mbox;
189 struct list_head *kdev_list;
193 #if defined(CONFIG_ARCH_OMAP1)
194 #define command_dvfs_stop(m) (0)
195 #define command_dvfs_start(m) (0)
196 #elif defined(CONFIG_ARCH_OMAP2)
197 #define command_dvfs_stop(m) \
198 (((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_STOP))
199 #define command_dvfs_start(m) \
200 (((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_START))
203 extern struct omap_dsp *omap_dsp;
205 extern int dsp_late_init(void);
207 #endif /* DRIVER_DSP_COMMON_H */