2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #ifndef DRIVER_DSP_COMMON_H
25 #define DRIVER_DSP_COMMON_H
27 #include "hardware_dsp.h"
29 #define DSPSPACE_SIZE 0x1000000
31 #define omap_set_bit_regw(b,r) \
32 do { omap_writew(omap_readw(r) | (b), (r)); } while(0)
33 #define omap_clr_bit_regw(b,r) \
34 do { omap_writew(omap_readw(r) & ~(b), (r)); } while(0)
35 #define omap_set_bit_regl(b,r) \
36 do { omap_writel(omap_readl(r) | (b), (r)); } while(0)
37 #define omap_clr_bit_regl(b,r) \
38 do { omap_writel(omap_readl(r) & ~(b), (r)); } while(0)
39 #define omap_set_bits_regl(val,mask,r) \
40 do { omap_writel((omap_readl(r) & ~(mask)) | (val), (r)); } while(0)
42 #if defined(CONFIG_ARCH_OMAP15XX)
43 #define INT_DSP_MMU INT_1510_DSP_MMU
44 #elif defined(CONFIG_ARCH_OMAP16XX)
45 #define INT_DSP_MMU INT_1610_DSP_MMU
46 #elif defined(CONFIG_ARCH_OMAP24XX)
47 #define INT_DSP_MMU INT_24XX_DSP_MMU
50 #define dspword_to_virt(dw) ((void *)(dspmem_base + ((dw) << 1)))
51 #define dspbyte_to_virt(db) ((void *)(dspmem_base + (db)))
52 #define virt_to_dspword(va) \
53 ((dsp_long_t)(((unsigned long)(va) - dspmem_base) >> 1))
54 #define virt_to_dspbyte(va) \
55 ((dsp_long_t)((unsigned long)(va) - dspmem_base))
56 #define is_dsp_internal_mem(va) \
57 (((unsigned long)(va) >= dspmem_base) && \
58 ((unsigned long)(va) < dspmem_base + dspmem_size))
59 #define is_dspbyte_internal_mem(db) ((db) < dspmem_size)
60 #define is_dspword_internal_mem(dw) (((dw) << 1) < dspmem_size)
62 #ifdef CONFIG_ARCH_OMAP1
64 * MPUI byteswap/wordswap on/off
65 * default setting: wordswap = all, byteswap = APIMEM only
67 #define mpui_wordswap_on() \
68 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_ALL, MPUI_CTRL_WORDSWAP_MASK, \
71 #define mpui_wordswap_off() \
72 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_NONE, MPUI_CTRL_WORDSWAP_MASK, \
75 #define mpui_byteswap_on() \
76 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_API, MPUI_CTRL_BYTESWAP_MASK, \
79 #define mpui_byteswap_off() \
80 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_NONE, MPUI_CTRL_BYTESWAP_MASK, \
84 * TC wordswap on / off
86 #define tc_wordswap() \
88 omap_writel(TC_ENDIANISM_SWAP_WORD | TC_ENDIANISM_EN, \
92 #define tc_noswap() omap_clr_bit_regl(TC_ENDIANISM_EN, TC_ENDIANISM)
95 * enable priority registers, EMIF, MPUI control logic
97 #define __dsp_enable() omap_set_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
98 #define __dsp_disable() omap_clr_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
99 #define __dsp_run() omap_set_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
100 #define __dsp_reset() omap_clr_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
101 #endif /* CONFIG_ARCH_OMAP1 */
103 #ifdef CONFIG_ARCH_OMAP2
105 * PRCM / IPI control logic
107 #define RSTCTRL_RST1_DSP 0x00000001
108 #define RSTCTRL_RST2_DSP 0x00000002
109 #define __dsp_core_enable() \
110 do { RM_RSTCTRL_DSP &= ~RSTCTRL_RST1_DSP; } while (0)
111 #define __dsp_core_disable() \
112 do { RM_RSTCTRL_DSP |= RSTCTRL_RST1_DSP; } while (0)
113 #define __dsp_per_enable() \
114 do { RM_RSTCTRL_DSP &= ~RSTCTRL_RST2_DSP; } while (0)
115 #define __dsp_per_disable() \
116 do { RM_RSTCTRL_DSP |= RSTCTRL_RST2_DSP; } while (0)
117 #endif /* CONFIG_ARCH_OMAP2 */
119 typedef u32 dsp_long_t; /* must have ability to carry TADD_ABORTADR */
121 #if defined(CONFIG_ARCH_OMAP1)
122 extern struct clk *dsp_ck_handle;
123 extern struct clk *api_ck_handle;
124 #elif defined(CONFIG_ARCH_OMAP2)
125 extern struct clk *dsp_fck_handle;
126 extern struct clk *dsp_ick_handle;
128 extern dsp_long_t dspmem_base, dspmem_size,
129 daram_base, daram_size,
130 saram_base, saram_size;
134 #ifdef CONFIG_ARCH_OMAP1
142 int dsp_set_rstvect(dsp_long_t adr);
143 dsp_long_t dsp_get_rstvect(void);
144 #ifdef CONFIG_ARCH_OMAP1
145 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size);
146 void dsp_reset_idle_boot_base(void);
148 void dsp_cpustat_request(enum cpustat_e req);
149 enum cpustat_e dsp_cpustat_get_stat(void);
150 u16 dsp_cpustat_get_icrmask(void);
151 void dsp_cpustat_set_icrmask(u16 mask);
152 #ifdef CONFIG_ARCH_OMAP1
153 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void));
154 void dsp_unregister_mem_cb(void);
157 #endif /* DRIVER_DSP_COMMON_H */