2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #ifndef DRIVER_DSP_COMMON_H
25 #define DRIVER_DSP_COMMON_H
27 #include <linux/clk.h>
28 #include <asm/arch/mmu.h>
29 #include "hardware_dsp.h"
31 #ifdef CONFIG_ARCH_OMAP2
32 #include "../../mach-omap2/prm.h"
33 #include "../../mach-omap2/prm_regbits_24xx.h"
34 #include "../../mach-omap2/cm.h"
35 #include "../../mach-omap2/cm_regbits_24xx.h"
38 #define DSPSPACE_SIZE 0x1000000
40 #define omap_set_bit_regw(b,r) \
41 do { omap_writew(omap_readw(r) | (b), (r)); } while(0)
42 #define omap_clr_bit_regw(b,r) \
43 do { omap_writew(omap_readw(r) & ~(b), (r)); } while(0)
44 #define omap_set_bit_regl(b,r) \
45 do { omap_writel(omap_readl(r) | (b), (r)); } while(0)
46 #define omap_clr_bit_regl(b,r) \
47 do { omap_writel(omap_readl(r) & ~(b), (r)); } while(0)
48 #define omap_set_bits_regl(val,mask,r) \
49 do { omap_writel((omap_readl(r) & ~(mask)) | (val), (r)); } while(0)
51 #define dspword_to_virt(dw) ((void *)(dspmem_base + ((dw) << 1)))
52 #define dspbyte_to_virt(db) ((void *)(dspmem_base + (db)))
53 #define virt_to_dspword(va) \
54 ((dsp_long_t)(((unsigned long)(va) - dspmem_base) >> 1))
55 #define virt_to_dspbyte(va) \
56 ((dsp_long_t)((unsigned long)(va) - dspmem_base))
57 #define is_dsp_internal_mem(va) \
58 (((unsigned long)(va) >= dspmem_base) && \
59 ((unsigned long)(va) < dspmem_base + dspmem_size))
60 #define is_dspbyte_internal_mem(db) ((db) < dspmem_size)
61 #define is_dspword_internal_mem(dw) (((dw) << 1) < dspmem_size)
63 #ifdef CONFIG_ARCH_OMAP1
65 * MPUI byteswap/wordswap on/off
66 * default setting: wordswap = all, byteswap = APIMEM only
68 #define mpui_wordswap_on() \
69 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_ALL, MPUI_CTRL_WORDSWAP_MASK, \
72 #define mpui_wordswap_off() \
73 omap_set_bits_regl(MPUI_CTRL_WORDSWAP_NONE, MPUI_CTRL_WORDSWAP_MASK, \
76 #define mpui_byteswap_on() \
77 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_API, MPUI_CTRL_BYTESWAP_MASK, \
80 #define mpui_byteswap_off() \
81 omap_set_bits_regl(MPUI_CTRL_BYTESWAP_NONE, MPUI_CTRL_BYTESWAP_MASK, \
85 * TC wordswap on / off
87 #define tc_wordswap() \
89 omap_writel(TC_ENDIANISM_SWAP_WORD | TC_ENDIANISM_EN, \
93 #define tc_noswap() omap_clr_bit_regl(TC_ENDIANISM_EN, TC_ENDIANISM)
96 * enable priority registers, EMIF, MPUI control logic
98 #define __dsp_enable() omap_set_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
99 #define __dsp_disable() omap_clr_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
100 #define __dsp_run() omap_set_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
101 #define __dsp_reset() omap_clr_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
102 #endif /* CONFIG_ARCH_OMAP1 */
104 #ifdef CONFIG_ARCH_OMAP2
106 * PRCM / IPI control logic
108 * REVISIT: these macros should probably be static inline functions
110 #define __dsp_core_enable() \
111 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
112 & ~OMAP24XX_RST1_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
113 #define __dsp_core_disable() \
114 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
115 | OMAP24XX_RST1_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
116 #define __dsp_per_enable() \
117 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
118 & ~OMAP24XX_RST2_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
119 #define __dsp_per_disable() \
120 do { prm_write_mod_reg(prm_read_mod_reg(OMAP24XX_DSP_MOD, RM_RSTCTRL) \
121 | OMAP24XX_RST2_DSP, OMAP24XX_DSP_MOD, RM_RSTCTRL); } while (0)
122 #endif /* CONFIG_ARCH_OMAP2 */
124 typedef u32 dsp_long_t; /* must have ability to carry TADD_ABORTADR */
126 #if defined(CONFIG_ARCH_OMAP1)
127 extern struct clk *dsp_ck_handle;
128 extern struct clk *api_ck_handle;
129 #elif defined(CONFIG_ARCH_OMAP2)
130 extern struct clk *dsp_fck_handle;
131 extern struct clk *dsp_ick_handle;
133 extern dsp_long_t dspmem_base, dspmem_size,
134 daram_base, daram_size,
135 saram_base, saram_size;
139 #ifdef CONFIG_ARCH_OMAP1
147 int dsp_set_rstvect(dsp_long_t adr);
148 dsp_long_t dsp_get_rstvect(void);
149 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size);
150 void dsp_reset_idle_boot_base(void);
151 void dsp_cpustat_request(enum cpustat_e req);
152 enum cpustat_e dsp_cpustat_get_stat(void);
153 u16 dsp_cpustat_get_icrmask(void);
154 void dsp_cpustat_set_icrmask(u16 mask);
155 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void));
156 void dsp_unregister_mem_cb(void);
158 #if defined(CONFIG_ARCH_OMAP1)
159 static inline void dsp_clk_enable(void) {}
160 static inline void dsp_clk_disable(void) {}
161 #elif defined(CONFIG_ARCH_OMAP2)
162 static inline void dsp_clk_enable(void)
166 /*XXX should be handled in mach-omap[1,2] XXX*/
167 prm_write_mod_reg(OMAP24XX_FORCESTATE | (1 << OMAP_POWERSTATE_SHIFT),
168 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
170 r = cm_read_mod_reg(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
171 r |= OMAP2420_AUTO_DSP_IPI;
172 cm_write_mod_reg(r, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
174 r = cm_read_mod_reg(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
175 r |= OMAP24XX_AUTOSTATE_DSP;
176 cm_write_mod_reg(r, OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
178 clk_enable(dsp_fck_handle);
179 clk_enable(dsp_ick_handle);
182 static inline void dsp_clk_disable(void)
185 clk_disable(dsp_ick_handle);
186 clk_disable(dsp_fck_handle);
188 prm_write_mod_reg(OMAP24XX_FORCESTATE | (3 << OMAP_POWERSTATE_SHIFT),
189 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
193 struct dsp_kfunc_device {
200 #define DSP_KFUNC_DEV_TYPE_COMMON 1
201 #define DSP_KFUNC_DEV_TYPE_AUDIO 2
203 struct list_head entry;
205 int (*probe)(struct dsp_kfunc_device *, int);
206 int (*remove)(struct dsp_kfunc_device *, int);
207 int (*enable)(struct dsp_kfunc_device *, int);
208 int (*disable)(struct dsp_kfunc_device *, int);
211 extern int dsp_kfunc_device_register(struct dsp_kfunc_device *);
213 struct dsp_platform_data {
214 struct list_head kdev_list;
219 int enabled; /* stored peripheral status */
220 struct omap_mmu *mmu;
221 struct omap_mbox *mbox;
223 struct list_head *kdev_list;
227 #if defined(CONFIG_ARCH_OMAP1)
228 #define command_dvfs_stop(m) (0)
229 #define command_dvfs_start(m) (0)
230 #elif defined(CONFIG_ARCH_OMAP2)
231 #define command_dvfs_stop(m) \
232 (((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_STOP))
233 #define command_dvfs_start(m) \
234 (((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_START))
237 extern struct omap_dsp *omap_dsp;
239 extern int dsp_late_init(void);
241 #endif /* DRIVER_DSP_COMMON_H */