2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/delay.h>
29 #include <linux/err.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/interrupt.h>
34 #include <asm/tlbflush.h>
36 #ifdef CONFIG_ARCH_OMAP1
37 #include <asm/arch/tc.h>
39 #include "dsp_common.h"
41 #if defined(CONFIG_ARCH_OMAP1)
42 #define dsp_boot_config(mode) omap_writew((mode), MPUI_DSP_BOOT_CONFIG)
44 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
45 #define dsp_boot_config(mode) writel((mode), DSP_IPI_DSPBOOTCONFIG)
48 struct omap_dsp *omap_dsp;
50 #if defined(CONFIG_ARCH_OMAP1)
51 struct clk *dsp_ck_handle;
52 struct clk *api_ck_handle;
53 #elif defined(CONFIG_ARCH_OMAP2)
54 struct clk *dsp_fck_handle;
55 struct clk *dsp_ick_handle;
57 dsp_long_t dspmem_base, dspmem_size,
58 daram_base, daram_size,
59 saram_base, saram_size;
61 static struct cpustat {
66 #ifdef CONFIG_ARCH_OMAP1
72 int (*mem_req_cb)(void);
73 void (*mem_rel_cb)(void);
76 .stat = CPUSTAT_RESET,
80 int dsp_set_rstvect(dsp_long_t adr)
82 unsigned long *dst_adr;
84 if (adr >= DSPSPACE_SIZE)
87 dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
89 *dst_adr = ((adr & 0xffff) << 16) | (adr >> 16);
93 dsp_boot_config(DSP_BOOT_CONFIG_DIRECT);
98 dsp_long_t dsp_get_rstvect(void)
100 unsigned long *dst_adr;
102 dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
103 return ((*dst_adr & 0xffff) << 16) | (*dst_adr >> 16);
106 #ifdef CONFIG_ARCH_OMAP1
107 static void simple_load_code(unsigned char *src_c, u16 *dst, int len)
110 u16 *src = (u16 *)src_c;
113 /* len must be multiple of 2. */
118 for (i = 0; i < len_w; i++) {
120 *dst = ((*src & 0x00ff) << 8) |
121 ((*src & 0xff00) >> 8);
127 /* program size must be multiple of 2 */
128 #define GBL_IDLE_TEXT_SIZE 52
129 #define GBL_IDLE_TEXT_INIT { \
131 0x3c, 0x4a, /* 0x3c4a: MOV 0x4, AR2 */ \
132 0xf4, 0x41, 0xfc, 0xff, /* 0xf441fcff: AND 0xfcff, *AR2 */ \
134 0x76, 0x34, 0x04, 0xb8, /* 0x763404b8: MOV 0x3404, AR3 */ \
135 0xfb, 0x61, 0x00, 0xf5, /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
136 0x9a, /* 0x9a: PORT */ \
137 0xfb, 0x61, 0x00, 0xa0, /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
138 0x9a, /* 0x9a: PORT */ \
139 /* *IER0 = 0, *IER1 = 0 */ \
140 0x3c, 0x0b, /* 0x3c0b: MOV 0x0, AR3 */ \
141 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
142 0x76, 0x00, 0x45, 0xb8, /* 0x76004508: MOV 0x45, AR3 */ \
143 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
144 /* *ICR = 0xffff */ \
145 0x3c, 0x1b, /* 0x3c1b: MOV 0x1, AR3 */ \
146 0xfb, 0x61, 0xff, 0xff, /* 0xfb61ffff: MOV 0xffff, *AR3 */ \
147 0x9a, /* 0x9a: PORT */ \
149 0xf5, 0x41, 0x03, 0x00, /* 0xf5410300: OR 0x0300, *AR2 */ \
150 /* idle and loop forever */ \
151 0x7a, 0x00, 0x00, 0x0c, /* 0x7a00000c: IDLE */ \
152 0x4a, 0x7a, /* 0x4a7a: B -6 (infinite loop) */ \
153 0x20, 0x20, 0x20, /* 0x20: NOP */ \
156 /* program size must be multiple of 2 */
157 #define CPU_IDLE_TEXT_SIZE 48
158 #define CPU_IDLE_TEXT_INIT(icrh, icrl) { \
160 0x3c, 0x4b, /* 0x3c4b: MOV 0x4, AR3 */ \
161 0xf4, 0x61, 0xfc, 0xff, /* 0xf461fcff: AND 0xfcff, *AR3 */ \
163 0x76, 0x34, 0x04, 0xb8, /* 0x763404b8: MOV 0x3404, AR3 */ \
164 0xfb, 0x61, 0x00, 0xf5, /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
165 0x9a, /* 0x9a: PORT */ \
166 0xfb, 0x61, 0x00, 0xa0, /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
167 0x9a, /* 0x9a: PORT */ \
168 /* *IER0 = 0, *IER1 = 0 */ \
169 0x3c, 0x0b, /* 0x3c0b: MOV 0x0, AR3 */ \
170 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
171 0x76, 0x00, 0x45, 0xb8, /* 0x76004508: MOV 0x45, AR3 */ \
172 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
173 /* set ICR = icr */ \
174 0x3c, 0x1b, /* 0x3c1b: MOV AR3 0x1 */ \
175 0xfb, 0x61, (icrh), (icrl), /* 0xfb61****: MOV *AR3, icr */ \
176 0x9a, /* 0x9a: PORT */ \
177 /* idle and loop forever */ \
178 0x7a, 0x00, 0x00, 0x0c, /* 0x7a00000c: IDLE */ \
179 0x4a, 0x7a, /* 0x4a7a: B -6 (infinite loop) */ \
180 0x20, 0x20, 0x20 /* 0x20: nop */ \
185 * Initialized with DSP_BOOT_ADR_MPUI (=0x010000).
186 * This value is used before DSP Gateway driver is initialized.
187 * DSP Gateway driver will overwrite this value with other value,
188 * to avoid confliction with the user program.
190 static dsp_long_t idle_boot_base = DSP_BOOT_ADR_MPUI;
192 static void dsp_gbl_idle(void)
194 unsigned char idle_text[GBL_IDLE_TEXT_SIZE] = GBL_IDLE_TEXT_INIT;
197 clk_enable(api_ck_handle);
200 dsp_boot_config(DSP_BOOT_CONFIG_IDLE);
202 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
204 if (idle_boot_base == DSP_BOOT_ADR_MPUI)
205 dsp_boot_config(DSP_BOOT_CONFIG_MPUI);
207 dsp_set_rstvect(idle_boot_base);
210 udelay(100); /* to make things stable */
211 clk_disable(api_ck_handle);
214 static void dsp_cpu_idle(void)
217 unsigned char icrh, icrl;
220 clk_enable(api_ck_handle);
224 * DMA should not sleep for DARAM/SARAM access
225 * DPLL should not sleep while any other domain is active
227 icr_tmp = cpustat.icrmask & ~(DSPREG_ICR_DMA | DSPREG_ICR_DPLL);
229 icrl = icr_tmp & 0xff;
231 unsigned char idle_text[CPU_IDLE_TEXT_SIZE] = CPU_IDLE_TEXT_INIT(icrh, icrl);
232 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
235 if (idle_boot_base == DSP_BOOT_ADR_MPUI)
236 dsp_boot_config(DSP_BOOT_CONFIG_MPUI);
238 dsp_set_rstvect(idle_boot_base);
240 udelay(100); /* to make things stable */
241 clk_disable(api_ck_handle);
244 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size)
246 if (adr == idle_boot_base)
248 idle_boot_base = adr;
249 if ((size < GBL_IDLE_TEXT_SIZE) ||
250 (size < CPU_IDLE_TEXT_SIZE)) {
252 "omapdsp: size for idle program is not enough!\n");
256 /* restart idle program with new base address */
257 if (cpustat.stat == CPUSTAT_GBL_IDLE)
259 if (cpustat.stat == CPUSTAT_CPU_IDLE)
263 void dsp_reset_idle_boot_base(void)
265 idle_boot_base = DSP_BOOT_ADR_MPUI;
268 void dsp_reset_idle_boot_base(void) { }
269 #endif /* CONFIG_ARCH_OMAP1 */
271 static int init_done;
273 static int omap_dsp_init(void)
275 mutex_init(&cpustat.lock);
278 #ifdef CONFIG_ARCH_OMAP15XX
279 if (cpu_is_omap15xx()) {
280 dspmem_base = OMAP1510_DSP_BASE;
281 dspmem_size = OMAP1510_DSP_SIZE;
282 daram_base = OMAP1510_DARAM_BASE;
283 daram_size = OMAP1510_DARAM_SIZE;
284 saram_base = OMAP1510_SARAM_BASE;
285 saram_size = OMAP1510_SARAM_SIZE;
288 #ifdef CONFIG_ARCH_OMAP16XX
289 if (cpu_is_omap16xx()) {
290 dspmem_base = OMAP16XX_DSP_BASE;
291 dspmem_size = OMAP16XX_DSP_SIZE;
292 daram_base = OMAP16XX_DARAM_BASE;
293 daram_size = OMAP16XX_DARAM_SIZE;
294 saram_base = OMAP16XX_SARAM_BASE;
295 saram_size = OMAP16XX_SARAM_SIZE;
298 #ifdef CONFIG_ARCH_OMAP24XX
299 if (cpu_is_omap24xx()) {
300 dspmem_base = DSP_MEM_24XX_VIRT;
301 dspmem_size = DSP_MEM_24XX_SIZE;
302 daram_base = OMAP24XX_DARAM_BASE;
303 daram_size = OMAP24XX_DARAM_SIZE;
304 saram_base = OMAP24XX_SARAM_BASE;
305 saram_size = OMAP24XX_SARAM_SIZE;
308 #ifdef CONFIG_ARCH_OMAP34XX
309 /* To be Revisited for 3430 */
310 if (cpu_is_omap34xx()) {
314 if (dspmem_size == 0) {
315 printk(KERN_ERR "omapdsp: unsupported omap architecture.\n");
319 #if defined(CONFIG_ARCH_OMAP1)
320 dsp_ck_handle = clk_get(NULL, "dsp_ck");
321 if (IS_ERR(dsp_ck_handle)) {
322 printk(KERN_ERR "omapdsp: could not acquire dsp_ck handle.\n");
323 return PTR_ERR(dsp_ck_handle);
326 api_ck_handle = clk_get(NULL, "api_ck");
327 if (IS_ERR(api_ck_handle)) {
328 printk(KERN_ERR "omapdsp: could not acquire api_ck handle.\n");
329 if (dsp_ck_handle != NULL)
330 clk_put(dsp_ck_handle);
331 return PTR_ERR(api_ck_handle);
334 /* This is needed for McBSP init, released in late_initcall */
335 clk_enable(api_ck_handle);
341 #elif defined(CONFIG_ARCH_OMAP2)
342 dsp_fck_handle = clk_get(NULL, "dsp_fck");
343 if (IS_ERR(dsp_fck_handle)) {
344 printk(KERN_ERR "omapdsp: could not acquire dsp_fck handle.\n");
345 return PTR_ERR(dsp_fck_handle);
348 dsp_ick_handle = clk_get(NULL, "dsp_ick");
349 if (IS_ERR(dsp_ick_handle)) {
350 printk(KERN_ERR "omapdsp: could not acquire dsp_ick handle.\n");
351 if (dsp_fck_handle != NULL)
352 clk_put(dsp_fck_handle);
353 return PTR_ERR(dsp_ick_handle);
358 pr_info("omap_dsp_init() done\n");
362 #if defined(CONFIG_ARCH_OMAP1)
363 static int __dsp_late_init(void)
365 clk_disable(api_ck_handle);
368 late_initcall(__dsp_late_init);
371 static void dsp_cpustat_update(void)
376 if (cpustat.req == CPUSTAT_RUN) {
377 if (cpustat.stat < CPUSTAT_RUN) {
378 #if defined(CONFIG_ARCH_OMAP1)
380 clk_enable(api_ck_handle);
383 #elif defined(CONFIG_ARCH_OMAP2)
384 __dsp_core_disable();
388 cpustat.stat = CPUSTAT_RUN;
393 /* cpustat.req < CPUSTAT_RUN */
395 if (cpustat.stat == CPUSTAT_RUN) {
396 #ifdef CONFIG_ARCH_OMAP1
397 clk_disable(api_ck_handle);
401 #ifdef CONFIG_ARCH_OMAP1
403 * (1) when ARM wants DARAM access, MPUI should be SAM and
404 * DSP needs to be on.
405 * (2) if any bits of icr is masked, we can not enter global idle.
407 if ((cpustat.req == CPUSTAT_CPU_IDLE) ||
408 (cpustat.usecount.mem > 0) ||
409 (cpustat.usecount.mem_delayed > 0) ||
410 ((cpustat.usecount.mpui > 0) && (cpustat.icrmask != 0xffff))) {
411 if (cpustat.stat != CPUSTAT_CPU_IDLE) {
413 cpustat.stat = CPUSTAT_CPU_IDLE;
419 * when ARM only needs MPUI access, MPUI can be HOM and
422 if ((cpustat.req == CPUSTAT_GBL_IDLE) ||
423 (cpustat.usecount.mpui > 0)) {
424 if (cpustat.stat != CPUSTAT_GBL_IDLE) {
426 cpustat.stat = CPUSTAT_GBL_IDLE;
430 #endif /* CONFIG_ARCH_OMAP1 */
433 * no user, no request
435 if (cpustat.stat != CPUSTAT_RESET) {
436 #if defined(CONFIG_ARCH_OMAP1)
438 #elif defined(CONFIG_ARCH_OMAP2)
439 __dsp_core_disable();
441 cpustat.stat = CPUSTAT_RESET;
445 void dsp_cpustat_request(enum cpustat_e req)
447 mutex_lock(&cpustat.lock);
449 dsp_cpustat_update();
450 mutex_unlock(&cpustat.lock);
453 enum cpustat_e dsp_cpustat_get_stat(void)
458 u16 dsp_cpustat_get_icrmask(void)
460 return cpustat.icrmask;
463 void dsp_cpustat_set_icrmask(u16 mask)
465 mutex_lock(&cpustat.lock);
466 cpustat.icrmask = mask;
467 dsp_cpustat_update();
468 mutex_unlock(&cpustat.lock);
471 #ifdef CONFIG_ARCH_OMAP1
472 void omap_dsp_request_mpui(void)
474 mutex_lock(&cpustat.lock);
475 if (cpustat.usecount.mpui++ == 0)
476 dsp_cpustat_update();
477 mutex_unlock(&cpustat.lock);
480 void omap_dsp_release_mpui(void)
482 mutex_lock(&cpustat.lock);
483 if (cpustat.usecount.mpui-- == 0) {
485 "omapdsp: unbalanced mpui request/release detected.\n"
486 " cpustat.usecount.mpui is going to be "
487 "less than zero! ... fixed to be zero.\n");
488 cpustat.usecount.mpui = 0;
490 if (cpustat.usecount.mpui == 0)
491 dsp_cpustat_update();
492 mutex_unlock(&cpustat.lock);
495 int omap_dsp_request_mem(void)
499 mutex_lock(&cpustat.lock);
500 if ((cpustat.usecount.mem++ == 0) &&
501 (cpustat.usecount.mem_delayed == 0)) {
502 if (cpustat.mem_req_cb) {
503 if ((ret = cpustat.mem_req_cb()) < 0) {
504 cpustat.usecount.mem--;
508 dsp_cpustat_update();
511 mutex_unlock(&cpustat.lock);
517 * release_mem will be delayed.
519 static void do_release_mem(struct work_struct *dummy)
521 mutex_lock(&cpustat.lock);
522 cpustat.usecount.mem_delayed = 0;
523 if (cpustat.usecount.mem == 0) {
524 dsp_cpustat_update();
525 if (cpustat.mem_rel_cb)
526 cpustat.mem_rel_cb();
528 mutex_unlock(&cpustat.lock);
531 static DECLARE_DELAYED_WORK(mem_rel_work, do_release_mem);
533 int omap_dsp_release_mem(void)
535 mutex_lock(&cpustat.lock);
537 /* cancel previous release work */
538 cancel_delayed_work(&mem_rel_work);
539 cpustat.usecount.mem_delayed = 0;
541 if (cpustat.usecount.mem-- == 0) {
543 "omapdsp: unbalanced memory request/release detected.\n"
544 " cpustat.usecount.mem is going to be "
545 "less than zero! ... fixed to be zero.\n");
546 cpustat.usecount.mem = 0;
548 if (cpustat.usecount.mem == 0) {
549 cpustat.usecount.mem_delayed = 1;
550 schedule_delayed_work(&mem_rel_work, HZ);
553 mutex_unlock(&cpustat.lock);
558 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void))
560 mutex_lock(&cpustat.lock);
562 cpustat.mem_req_cb = req_cb;
563 cpustat.mem_rel_cb = rel_cb;
566 * This function must be called while mem is enabled!
568 BUG_ON(cpustat.usecount.mem == 0);
570 mutex_unlock(&cpustat.lock);
573 void dsp_unregister_mem_cb(void)
575 mutex_lock(&cpustat.lock);
576 cpustat.mem_req_cb = NULL;
577 cpustat.mem_rel_cb = NULL;
578 mutex_unlock(&cpustat.lock);
581 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void)) { }
582 void dsp_unregister_mem_cb(void) { }
583 #endif /* CONFIG_ARCH_OMAP1 */
585 arch_initcall(omap_dsp_init);
587 #ifdef CONFIG_ARCH_OMAP1
588 EXPORT_SYMBOL(omap_dsp_request_mpui);
589 EXPORT_SYMBOL(omap_dsp_release_mpui);
590 EXPORT_SYMBOL(omap_dsp_request_mem);
591 EXPORT_SYMBOL(omap_dsp_release_mem);
592 #endif /* CONFIG_ARCH_OMAP1 */
594 #ifdef CONFIG_OMAP_DSP_MODULE
595 #if defined(CONFIG_ARCH_OMAP1)
596 EXPORT_SYMBOL(dsp_ck_handle);
597 EXPORT_SYMBOL(api_ck_handle);
598 #elif defined(CONFIG_ARCH_OMAP2)
599 EXPORT_SYMBOL(dsp_fck_handle);
600 EXPORT_SYMBOL(dsp_ick_handle);
602 EXPORT_SYMBOL(omap_dsp);
603 EXPORT_SYMBOL(dspmem_base);
604 EXPORT_SYMBOL(dspmem_size);
605 EXPORT_SYMBOL(daram_base);
606 EXPORT_SYMBOL(daram_size);
607 EXPORT_SYMBOL(saram_base);
608 EXPORT_SYMBOL(saram_size);
609 EXPORT_SYMBOL(dsp_set_rstvect);
610 EXPORT_SYMBOL(dsp_get_rstvect);
611 #ifdef CONFIG_ARCH_OMAP1
612 EXPORT_SYMBOL(dsp_set_idle_boot_base);
613 EXPORT_SYMBOL(dsp_reset_idle_boot_base);
614 #endif /* CONFIG_ARCH_OMAP1 */
615 EXPORT_SYMBOL(dsp_cpustat_request);
616 EXPORT_SYMBOL(dsp_cpustat_get_stat);
617 EXPORT_SYMBOL(dsp_cpustat_get_icrmask);
618 EXPORT_SYMBOL(dsp_cpustat_set_icrmask);
619 EXPORT_SYMBOL(dsp_register_mem_cb);
620 EXPORT_SYMBOL(dsp_unregister_mem_cb);
622 EXPORT_SYMBOL(__cpu_flush_kern_tlb_range);
623 EXPORT_SYMBOL(cpu_architecture);
624 EXPORT_SYMBOL(pmd_clear_bad);