2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/delay.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/interrupt.h>
33 #include <asm/tlbflush.h>
35 #ifdef CONFIG_ARCH_OMAP1
36 #include <asm/arch/tc.h>
38 #include "dsp_common.h"
40 #if defined(CONFIG_ARCH_OMAP1)
41 #define dsp_boot_config(mode) omap_writew((mode), MPUI_DSP_BOOT_CONFIG)
43 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
44 #define dsp_boot_config(mode) writel((mode), DSP_IPI_DSPBOOTCONFIG)
47 struct omap_dsp *omap_dsp;
49 #if defined(CONFIG_ARCH_OMAP1)
50 struct clk *dsp_ck_handle;
51 struct clk *api_ck_handle;
52 #elif defined(CONFIG_ARCH_OMAP2)
53 struct clk *dsp_fck_handle;
54 struct clk *dsp_ick_handle;
56 dsp_long_t dspmem_base, dspmem_size,
57 daram_base, daram_size,
58 saram_base, saram_size;
60 static struct cpustat {
65 #ifdef CONFIG_ARCH_OMAP1
71 int (*mem_req_cb)(void);
72 void (*mem_rel_cb)(void);
75 .stat = CPUSTAT_RESET,
79 int dsp_set_rstvect(dsp_long_t adr)
81 unsigned long *dst_adr;
83 if (adr >= DSPSPACE_SIZE)
86 dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
88 *dst_adr = ((adr & 0xffff) << 16) | (adr >> 16);
92 dsp_boot_config(DSP_BOOT_CONFIG_DIRECT);
97 dsp_long_t dsp_get_rstvect(void)
99 unsigned long *dst_adr;
101 dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
102 return ((*dst_adr & 0xffff) << 16) | (*dst_adr >> 16);
105 #ifdef CONFIG_ARCH_OMAP1
106 static void simple_load_code(unsigned char *src_c, u16 *dst, int len)
109 u16 *src = (u16 *)src_c;
112 /* len must be multiple of 2. */
117 for (i = 0; i < len_w; i++) {
119 *dst = ((*src & 0x00ff) << 8) |
120 ((*src & 0xff00) >> 8);
126 /* program size must be multiple of 2 */
127 #define GBL_IDLE_TEXT_SIZE 52
128 #define GBL_IDLE_TEXT_INIT { \
130 0x3c, 0x4a, /* 0x3c4a: MOV 0x4, AR2 */ \
131 0xf4, 0x41, 0xfc, 0xff, /* 0xf441fcff: AND 0xfcff, *AR2 */ \
133 0x76, 0x34, 0x04, 0xb8, /* 0x763404b8: MOV 0x3404, AR3 */ \
134 0xfb, 0x61, 0x00, 0xf5, /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
135 0x9a, /* 0x9a: PORT */ \
136 0xfb, 0x61, 0x00, 0xa0, /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
137 0x9a, /* 0x9a: PORT */ \
138 /* *IER0 = 0, *IER1 = 0 */ \
139 0x3c, 0x0b, /* 0x3c0b: MOV 0x0, AR3 */ \
140 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
141 0x76, 0x00, 0x45, 0xb8, /* 0x76004508: MOV 0x45, AR3 */ \
142 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
143 /* *ICR = 0xffff */ \
144 0x3c, 0x1b, /* 0x3c1b: MOV 0x1, AR3 */ \
145 0xfb, 0x61, 0xff, 0xff, /* 0xfb61ffff: MOV 0xffff, *AR3 */ \
146 0x9a, /* 0x9a: PORT */ \
148 0xf5, 0x41, 0x03, 0x00, /* 0xf5410300: OR 0x0300, *AR2 */ \
149 /* idle and loop forever */ \
150 0x7a, 0x00, 0x00, 0x0c, /* 0x7a00000c: IDLE */ \
151 0x4a, 0x7a, /* 0x4a7a: B -6 (infinite loop) */ \
152 0x20, 0x20, 0x20, /* 0x20: NOP */ \
155 /* program size must be multiple of 2 */
156 #define CPU_IDLE_TEXT_SIZE 48
157 #define CPU_IDLE_TEXT_INIT(icrh, icrl) { \
159 0x3c, 0x4b, /* 0x3c4b: MOV 0x4, AR3 */ \
160 0xf4, 0x61, 0xfc, 0xff, /* 0xf461fcff: AND 0xfcff, *AR3 */ \
162 0x76, 0x34, 0x04, 0xb8, /* 0x763404b8: MOV 0x3404, AR3 */ \
163 0xfb, 0x61, 0x00, 0xf5, /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
164 0x9a, /* 0x9a: PORT */ \
165 0xfb, 0x61, 0x00, 0xa0, /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
166 0x9a, /* 0x9a: PORT */ \
167 /* *IER0 = 0, *IER1 = 0 */ \
168 0x3c, 0x0b, /* 0x3c0b: MOV 0x0, AR3 */ \
169 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
170 0x76, 0x00, 0x45, 0xb8, /* 0x76004508: MOV 0x45, AR3 */ \
171 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
172 /* set ICR = icr */ \
173 0x3c, 0x1b, /* 0x3c1b: MOV AR3 0x1 */ \
174 0xfb, 0x61, (icrh), (icrl), /* 0xfb61****: MOV *AR3, icr */ \
175 0x9a, /* 0x9a: PORT */ \
176 /* idle and loop forever */ \
177 0x7a, 0x00, 0x00, 0x0c, /* 0x7a00000c: IDLE */ \
178 0x4a, 0x7a, /* 0x4a7a: B -6 (infinite loop) */ \
179 0x20, 0x20, 0x20 /* 0x20: nop */ \
184 * Initialized with DSP_BOOT_ADR_MPUI (=0x010000).
185 * This value is used before DSP Gateway driver is initialized.
186 * DSP Gateway driver will overwrite this value with other value,
187 * to avoid confliction with the user program.
189 static dsp_long_t idle_boot_base = DSP_BOOT_ADR_MPUI;
191 static void dsp_gbl_idle(void)
193 unsigned char idle_text[GBL_IDLE_TEXT_SIZE] = GBL_IDLE_TEXT_INIT;
196 clk_enable(api_ck_handle);
199 dsp_boot_config(DSP_BOOT_CONFIG_IDLE);
201 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
203 if (idle_boot_base == DSP_BOOT_ADR_MPUI)
204 dsp_boot_config(DSP_BOOT_CONFIG_MPUI);
206 dsp_set_rstvect(idle_boot_base);
209 udelay(100); /* to make things stable */
210 clk_disable(api_ck_handle);
213 static void dsp_cpu_idle(void)
216 unsigned char icrh, icrl;
219 clk_enable(api_ck_handle);
223 * DMA should not sleep for DARAM/SARAM access
224 * DPLL should not sleep while any other domain is active
226 icr_tmp = cpustat.icrmask & ~(DSPREG_ICR_DMA | DSPREG_ICR_DPLL);
228 icrl = icr_tmp & 0xff;
230 unsigned char idle_text[CPU_IDLE_TEXT_SIZE] = CPU_IDLE_TEXT_INIT(icrh, icrl);
231 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
234 if (idle_boot_base == DSP_BOOT_ADR_MPUI)
235 dsp_boot_config(DSP_BOOT_CONFIG_MPUI);
237 dsp_set_rstvect(idle_boot_base);
239 udelay(100); /* to make things stable */
240 clk_disable(api_ck_handle);
243 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size)
245 if (adr == idle_boot_base)
247 idle_boot_base = adr;
248 if ((size < GBL_IDLE_TEXT_SIZE) ||
249 (size < CPU_IDLE_TEXT_SIZE)) {
251 "omapdsp: size for idle program is not enough!\n");
255 /* restart idle program with new base address */
256 if (cpustat.stat == CPUSTAT_GBL_IDLE)
258 if (cpustat.stat == CPUSTAT_CPU_IDLE)
262 void dsp_reset_idle_boot_base(void)
264 idle_boot_base = DSP_BOOT_ADR_MPUI;
267 void dsp_reset_idle_boot_base(void) { }
268 #endif /* CONFIG_ARCH_OMAP1 */
270 static int init_done;
272 static int omap_dsp_init(void)
274 mutex_init(&cpustat.lock);
277 #ifdef CONFIG_ARCH_OMAP15XX
278 if (cpu_is_omap15xx()) {
279 dspmem_base = OMAP1510_DSP_BASE;
280 dspmem_size = OMAP1510_DSP_SIZE;
281 daram_base = OMAP1510_DARAM_BASE;
282 daram_size = OMAP1510_DARAM_SIZE;
283 saram_base = OMAP1510_SARAM_BASE;
284 saram_size = OMAP1510_SARAM_SIZE;
287 #ifdef CONFIG_ARCH_OMAP16XX
288 if (cpu_is_omap16xx()) {
289 dspmem_base = OMAP16XX_DSP_BASE;
290 dspmem_size = OMAP16XX_DSP_SIZE;
291 daram_base = OMAP16XX_DARAM_BASE;
292 daram_size = OMAP16XX_DARAM_SIZE;
293 saram_base = OMAP16XX_SARAM_BASE;
294 saram_size = OMAP16XX_SARAM_SIZE;
297 #ifdef CONFIG_ARCH_OMAP24XX
298 if (cpu_is_omap24xx()) {
299 dspmem_base = DSP_MEM_24XX_VIRT;
300 dspmem_size = DSP_MEM_24XX_SIZE;
301 daram_base = OMAP24XX_DARAM_BASE;
302 daram_size = OMAP24XX_DARAM_SIZE;
303 saram_base = OMAP24XX_SARAM_BASE;
304 saram_size = OMAP24XX_SARAM_SIZE;
307 #ifdef CONFIG_ARCH_OMAP34XX
308 /* To be Revisited for 3430 */
309 if (cpu_is_omap34xx()) {
313 if (dspmem_size == 0) {
314 printk(KERN_ERR "omapdsp: unsupported omap architecture.\n");
318 #if defined(CONFIG_ARCH_OMAP1)
319 dsp_ck_handle = clk_get(NULL, "dsp_ck");
320 if (IS_ERR(dsp_ck_handle)) {
321 printk(KERN_ERR "omapdsp: could not acquire dsp_ck handle.\n");
322 return PTR_ERR(dsp_ck_handle);
325 api_ck_handle = clk_get(NULL, "api_ck");
326 if (IS_ERR(api_ck_handle)) {
327 printk(KERN_ERR "omapdsp: could not acquire api_ck handle.\n");
328 if (dsp_ck_handle != NULL)
329 clk_put(dsp_ck_handle);
330 return PTR_ERR(api_ck_handle);
333 /* This is needed for McBSP init, released in late_initcall */
334 clk_enable(api_ck_handle);
340 #elif defined(CONFIG_ARCH_OMAP2)
341 dsp_fck_handle = clk_get(NULL, "dsp_fck");
342 if (IS_ERR(dsp_fck_handle)) {
343 printk(KERN_ERR "omapdsp: could not acquire dsp_fck handle.\n");
344 return PTR_ERR(dsp_fck_handle);
347 dsp_ick_handle = clk_get(NULL, "dsp_ick");
348 if (IS_ERR(dsp_ick_handle)) {
349 printk(KERN_ERR "omapdsp: could not acquire dsp_ick handle.\n");
350 if (dsp_fck_handle != NULL)
351 clk_put(dsp_fck_handle);
352 return PTR_ERR(dsp_ick_handle);
357 pr_info("omap_dsp_init() done\n");
361 #if defined(CONFIG_ARCH_OMAP1)
362 static int __dsp_late_init(void)
364 clk_disable(api_ck_handle);
367 late_initcall(__dsp_late_init);
370 static void dsp_cpustat_update(void)
375 if (cpustat.req == CPUSTAT_RUN) {
376 if (cpustat.stat < CPUSTAT_RUN) {
377 #if defined(CONFIG_ARCH_OMAP1)
379 clk_enable(api_ck_handle);
382 #elif defined(CONFIG_ARCH_OMAP2)
383 __dsp_core_disable();
387 cpustat.stat = CPUSTAT_RUN;
392 /* cpustat.req < CPUSTAT_RUN */
394 if (cpustat.stat == CPUSTAT_RUN) {
395 #ifdef CONFIG_ARCH_OMAP1
396 clk_disable(api_ck_handle);
400 #ifdef CONFIG_ARCH_OMAP1
402 * (1) when ARM wants DARAM access, MPUI should be SAM and
403 * DSP needs to be on.
404 * (2) if any bits of icr is masked, we can not enter global idle.
406 if ((cpustat.req == CPUSTAT_CPU_IDLE) ||
407 (cpustat.usecount.mem > 0) ||
408 (cpustat.usecount.mem_delayed > 0) ||
409 ((cpustat.usecount.mpui > 0) && (cpustat.icrmask != 0xffff))) {
410 if (cpustat.stat != CPUSTAT_CPU_IDLE) {
412 cpustat.stat = CPUSTAT_CPU_IDLE;
418 * when ARM only needs MPUI access, MPUI can be HOM and
421 if ((cpustat.req == CPUSTAT_GBL_IDLE) ||
422 (cpustat.usecount.mpui > 0)) {
423 if (cpustat.stat != CPUSTAT_GBL_IDLE) {
425 cpustat.stat = CPUSTAT_GBL_IDLE;
429 #endif /* CONFIG_ARCH_OMAP1 */
432 * no user, no request
434 if (cpustat.stat != CPUSTAT_RESET) {
435 #if defined(CONFIG_ARCH_OMAP1)
437 #elif defined(CONFIG_ARCH_OMAP2)
438 __dsp_core_disable();
440 cpustat.stat = CPUSTAT_RESET;
444 void dsp_cpustat_request(enum cpustat_e req)
446 mutex_lock(&cpustat.lock);
448 dsp_cpustat_update();
449 mutex_unlock(&cpustat.lock);
452 enum cpustat_e dsp_cpustat_get_stat(void)
457 u16 dsp_cpustat_get_icrmask(void)
459 return cpustat.icrmask;
462 void dsp_cpustat_set_icrmask(u16 mask)
464 mutex_lock(&cpustat.lock);
465 cpustat.icrmask = mask;
466 dsp_cpustat_update();
467 mutex_unlock(&cpustat.lock);
470 #ifdef CONFIG_ARCH_OMAP1
471 void omap_dsp_request_mpui(void)
473 mutex_lock(&cpustat.lock);
474 if (cpustat.usecount.mpui++ == 0)
475 dsp_cpustat_update();
476 mutex_unlock(&cpustat.lock);
479 void omap_dsp_release_mpui(void)
481 mutex_lock(&cpustat.lock);
482 if (cpustat.usecount.mpui-- == 0) {
484 "omapdsp: unbalanced mpui request/release detected.\n"
485 " cpustat.usecount.mpui is going to be "
486 "less than zero! ... fixed to be zero.\n");
487 cpustat.usecount.mpui = 0;
489 if (cpustat.usecount.mpui == 0)
490 dsp_cpustat_update();
491 mutex_unlock(&cpustat.lock);
494 int omap_dsp_request_mem(void)
498 mutex_lock(&cpustat.lock);
499 if ((cpustat.usecount.mem++ == 0) &&
500 (cpustat.usecount.mem_delayed == 0)) {
501 if (cpustat.mem_req_cb) {
502 if ((ret = cpustat.mem_req_cb()) < 0) {
503 cpustat.usecount.mem--;
507 dsp_cpustat_update();
510 mutex_unlock(&cpustat.lock);
516 * release_mem will be delayed.
518 static void do_release_mem(struct work_struct *dummy)
520 mutex_lock(&cpustat.lock);
521 cpustat.usecount.mem_delayed = 0;
522 if (cpustat.usecount.mem == 0) {
523 dsp_cpustat_update();
524 if (cpustat.mem_rel_cb)
525 cpustat.mem_rel_cb();
527 mutex_unlock(&cpustat.lock);
530 static DECLARE_DELAYED_WORK(mem_rel_work, do_release_mem);
532 int omap_dsp_release_mem(void)
534 mutex_lock(&cpustat.lock);
536 /* cancel previous release work */
537 cancel_delayed_work(&mem_rel_work);
538 cpustat.usecount.mem_delayed = 0;
540 if (cpustat.usecount.mem-- == 0) {
542 "omapdsp: unbalanced memory request/release detected.\n"
543 " cpustat.usecount.mem is going to be "
544 "less than zero! ... fixed to be zero.\n");
545 cpustat.usecount.mem = 0;
547 if (cpustat.usecount.mem == 0) {
548 cpustat.usecount.mem_delayed = 1;
549 schedule_delayed_work(&mem_rel_work, HZ);
552 mutex_unlock(&cpustat.lock);
557 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void))
559 mutex_lock(&cpustat.lock);
561 cpustat.mem_req_cb = req_cb;
562 cpustat.mem_rel_cb = rel_cb;
565 * This function must be called while mem is enabled!
567 BUG_ON(cpustat.usecount.mem == 0);
569 mutex_unlock(&cpustat.lock);
572 void dsp_unregister_mem_cb(void)
574 mutex_lock(&cpustat.lock);
575 cpustat.mem_req_cb = NULL;
576 cpustat.mem_rel_cb = NULL;
577 mutex_unlock(&cpustat.lock);
580 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void)) { }
581 void dsp_unregister_mem_cb(void) { }
582 #endif /* CONFIG_ARCH_OMAP1 */
584 arch_initcall(omap_dsp_init);
586 #ifdef CONFIG_ARCH_OMAP1
587 EXPORT_SYMBOL(omap_dsp_request_mpui);
588 EXPORT_SYMBOL(omap_dsp_release_mpui);
589 EXPORT_SYMBOL(omap_dsp_request_mem);
590 EXPORT_SYMBOL(omap_dsp_release_mem);
591 #endif /* CONFIG_ARCH_OMAP1 */
593 #ifdef CONFIG_OMAP_DSP_MODULE
594 #if defined(CONFIG_ARCH_OMAP1)
595 EXPORT_SYMBOL(dsp_ck_handle);
596 EXPORT_SYMBOL(api_ck_handle);
597 #elif defined(CONFIG_ARCH_OMAP2)
598 EXPORT_SYMBOL(dsp_fck_handle);
599 EXPORT_SYMBOL(dsp_ick_handle);
601 EXPORT_SYMBOL(omap_dsp);
602 EXPORT_SYMBOL(dspmem_base);
603 EXPORT_SYMBOL(dspmem_size);
604 EXPORT_SYMBOL(daram_base);
605 EXPORT_SYMBOL(daram_size);
606 EXPORT_SYMBOL(saram_base);
607 EXPORT_SYMBOL(saram_size);
608 EXPORT_SYMBOL(dsp_set_rstvect);
609 EXPORT_SYMBOL(dsp_get_rstvect);
610 #ifdef CONFIG_ARCH_OMAP1
611 EXPORT_SYMBOL(dsp_set_idle_boot_base);
612 EXPORT_SYMBOL(dsp_reset_idle_boot_base);
613 #endif /* CONFIG_ARCH_OMAP1 */
614 EXPORT_SYMBOL(dsp_cpustat_request);
615 EXPORT_SYMBOL(dsp_cpustat_get_stat);
616 EXPORT_SYMBOL(dsp_cpustat_get_icrmask);
617 EXPORT_SYMBOL(dsp_cpustat_set_icrmask);
618 EXPORT_SYMBOL(dsp_register_mem_cb);
619 EXPORT_SYMBOL(dsp_unregister_mem_cb);
621 EXPORT_SYMBOL(__cpu_flush_kern_tlb_range);
622 EXPORT_SYMBOL(cpu_architecture);
623 EXPORT_SYMBOL(pmd_clear_bad);