2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
4 * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/delay.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/interrupt.h>
33 #include <asm/tlbflush.h>
35 #ifdef CONFIG_ARCH_OMAP1
36 #include <asm/arch/tc.h>
38 #include "dsp_common.h"
40 #if defined(CONFIG_ARCH_OMAP1)
41 #define dsp_boot_config(mode) omap_writew((mode), MPUI_DSP_BOOT_CONFIG)
42 #elif defined(CONFIG_ARCH_OMAP2)
43 #define dsp_boot_config(mode) writel((mode), DSP_IPI_DSPBOOTCONFIG)
46 struct omap_dsp *omap_dsp;
48 #if defined(CONFIG_ARCH_OMAP1)
49 struct clk *dsp_ck_handle;
50 struct clk *api_ck_handle;
51 #elif defined(CONFIG_ARCH_OMAP2)
52 struct clk *dsp_fck_handle;
53 struct clk *dsp_ick_handle;
55 dsp_long_t dspmem_base, dspmem_size,
56 daram_base, daram_size,
57 saram_base, saram_size;
59 static struct cpustat {
64 #ifdef CONFIG_ARCH_OMAP1
70 int (*mem_req_cb)(void);
71 void (*mem_rel_cb)(void);
74 .stat = CPUSTAT_RESET,
78 int dsp_set_rstvect(dsp_long_t adr)
80 unsigned long *dst_adr;
82 if (adr >= DSPSPACE_SIZE)
85 dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
87 *dst_adr = ((adr & 0xffff) << 16) | (adr >> 16);
91 dsp_boot_config(DSP_BOOT_CONFIG_DIRECT);
96 dsp_long_t dsp_get_rstvect(void)
98 unsigned long *dst_adr;
100 dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
101 return ((*dst_adr & 0xffff) << 16) | (*dst_adr >> 16);
104 #ifdef CONFIG_ARCH_OMAP1
105 static void simple_load_code(unsigned char *src_c, u16 *dst, int len)
108 u16 *src = (u16 *)src_c;
111 /* len must be multiple of 2. */
116 for (i = 0; i < len_w; i++) {
118 *dst = ((*src & 0x00ff) << 8) |
119 ((*src & 0xff00) >> 8);
125 /* program size must be multiple of 2 */
126 #define GBL_IDLE_TEXT_SIZE 52
127 #define GBL_IDLE_TEXT_INIT { \
129 0x3c, 0x4a, /* 0x3c4a: MOV 0x4, AR2 */ \
130 0xf4, 0x41, 0xfc, 0xff, /* 0xf441fcff: AND 0xfcff, *AR2 */ \
132 0x76, 0x34, 0x04, 0xb8, /* 0x763404b8: MOV 0x3404, AR3 */ \
133 0xfb, 0x61, 0x00, 0xf5, /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
134 0x9a, /* 0x9a: PORT */ \
135 0xfb, 0x61, 0x00, 0xa0, /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
136 0x9a, /* 0x9a: PORT */ \
137 /* *IER0 = 0, *IER1 = 0 */ \
138 0x3c, 0x0b, /* 0x3c0b: MOV 0x0, AR3 */ \
139 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
140 0x76, 0x00, 0x45, 0xb8, /* 0x76004508: MOV 0x45, AR3 */ \
141 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
142 /* *ICR = 0xffff */ \
143 0x3c, 0x1b, /* 0x3c1b: MOV 0x1, AR3 */ \
144 0xfb, 0x61, 0xff, 0xff, /* 0xfb61ffff: MOV 0xffff, *AR3 */ \
145 0x9a, /* 0x9a: PORT */ \
147 0xf5, 0x41, 0x03, 0x00, /* 0xf5410300: OR 0x0300, *AR2 */ \
148 /* idle and loop forever */ \
149 0x7a, 0x00, 0x00, 0x0c, /* 0x7a00000c: IDLE */ \
150 0x4a, 0x7a, /* 0x4a7a: B -6 (infinite loop) */ \
151 0x20, 0x20, 0x20, /* 0x20: NOP */ \
154 /* program size must be multiple of 2 */
155 #define CPU_IDLE_TEXT_SIZE 48
156 #define CPU_IDLE_TEXT_INIT(icrh, icrl) { \
158 0x3c, 0x4b, /* 0x3c4b: MOV 0x4, AR3 */ \
159 0xf4, 0x61, 0xfc, 0xff, /* 0xf461fcff: AND 0xfcff, *AR3 */ \
161 0x76, 0x34, 0x04, 0xb8, /* 0x763404b8: MOV 0x3404, AR3 */ \
162 0xfb, 0x61, 0x00, 0xf5, /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
163 0x9a, /* 0x9a: PORT */ \
164 0xfb, 0x61, 0x00, 0xa0, /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
165 0x9a, /* 0x9a: PORT */ \
166 /* *IER0 = 0, *IER1 = 0 */ \
167 0x3c, 0x0b, /* 0x3c0b: MOV 0x0, AR3 */ \
168 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
169 0x76, 0x00, 0x45, 0xb8, /* 0x76004508: MOV 0x45, AR3 */ \
170 0xe6, 0x61, 0x00, /* 0xe66100: MOV 0, *AR3 */ \
171 /* set ICR = icr */ \
172 0x3c, 0x1b, /* 0x3c1b: MOV AR3 0x1 */ \
173 0xfb, 0x61, (icrh), (icrl), /* 0xfb61****: MOV *AR3, icr */ \
174 0x9a, /* 0x9a: PORT */ \
175 /* idle and loop forever */ \
176 0x7a, 0x00, 0x00, 0x0c, /* 0x7a00000c: IDLE */ \
177 0x4a, 0x7a, /* 0x4a7a: B -6 (infinite loop) */ \
178 0x20, 0x20, 0x20 /* 0x20: nop */ \
183 * Initialized with DSP_BOOT_ADR_MPUI (=0x010000).
184 * This value is used before DSP Gateway driver is initialized.
185 * DSP Gateway driver will overwrite this value with other value,
186 * to avoid confliction with the user program.
188 static dsp_long_t idle_boot_base = DSP_BOOT_ADR_MPUI;
190 static void dsp_gbl_idle(void)
192 unsigned char idle_text[GBL_IDLE_TEXT_SIZE] = GBL_IDLE_TEXT_INIT;
195 clk_enable(api_ck_handle);
198 dsp_boot_config(DSP_BOOT_CONFIG_IDLE);
200 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
202 if (idle_boot_base == DSP_BOOT_ADR_MPUI)
203 dsp_boot_config(DSP_BOOT_CONFIG_MPUI);
205 dsp_set_rstvect(idle_boot_base);
208 udelay(100); /* to make things stable */
209 clk_disable(api_ck_handle);
212 static void dsp_cpu_idle(void)
215 unsigned char icrh, icrl;
218 clk_enable(api_ck_handle);
222 * DMA should not sleep for DARAM/SARAM access
223 * DPLL should not sleep while any other domain is active
225 icr_tmp = cpustat.icrmask & ~(DSPREG_ICR_DMA | DSPREG_ICR_DPLL);
227 icrl = icr_tmp & 0xff;
229 unsigned char idle_text[CPU_IDLE_TEXT_SIZE] = CPU_IDLE_TEXT_INIT(icrh, icrl);
230 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
233 if (idle_boot_base == DSP_BOOT_ADR_MPUI)
234 dsp_boot_config(DSP_BOOT_CONFIG_MPUI);
236 dsp_set_rstvect(idle_boot_base);
238 udelay(100); /* to make things stable */
239 clk_disable(api_ck_handle);
242 void dsp_set_idle_boot_base(dsp_long_t adr, size_t size)
244 if (adr == idle_boot_base)
246 idle_boot_base = adr;
247 if ((size < GBL_IDLE_TEXT_SIZE) ||
248 (size < CPU_IDLE_TEXT_SIZE)) {
250 "omapdsp: size for idle program is not enough!\n");
254 /* restart idle program with new base address */
255 if (cpustat.stat == CPUSTAT_GBL_IDLE)
257 if (cpustat.stat == CPUSTAT_CPU_IDLE)
261 void dsp_reset_idle_boot_base(void)
263 idle_boot_base = DSP_BOOT_ADR_MPUI;
266 #endif /* CONFIG_ARCH_OMAP1 */
268 static int init_done;
270 static int __init omap_dsp_init(void)
272 mutex_init(&cpustat.lock);
275 #ifdef CONFIG_ARCH_OMAP15XX
276 if (cpu_is_omap15xx()) {
277 dspmem_base = OMAP1510_DSP_BASE;
278 dspmem_size = OMAP1510_DSP_SIZE;
279 daram_base = OMAP1510_DARAM_BASE;
280 daram_size = OMAP1510_DARAM_SIZE;
281 saram_base = OMAP1510_SARAM_BASE;
282 saram_size = OMAP1510_SARAM_SIZE;
285 #ifdef CONFIG_ARCH_OMAP16XX
286 if (cpu_is_omap16xx()) {
287 dspmem_base = OMAP16XX_DSP_BASE;
288 dspmem_size = OMAP16XX_DSP_SIZE;
289 daram_base = OMAP16XX_DARAM_BASE;
290 daram_size = OMAP16XX_DARAM_SIZE;
291 saram_base = OMAP16XX_SARAM_BASE;
292 saram_size = OMAP16XX_SARAM_SIZE;
295 #ifdef CONFIG_ARCH_OMAP24XX
296 if (cpu_is_omap24xx()) {
297 dspmem_base = DSP_MEM_24XX_VIRT;
298 dspmem_size = DSP_MEM_24XX_SIZE;
299 daram_base = OMAP24XX_DARAM_BASE;
300 daram_size = OMAP24XX_DARAM_SIZE;
301 saram_base = OMAP24XX_SARAM_BASE;
302 saram_size = OMAP24XX_SARAM_SIZE;
305 if (dspmem_size == 0) {
306 printk(KERN_ERR "omapdsp: unsupported omap architecture.\n");
310 #if defined(CONFIG_ARCH_OMAP1)
311 dsp_ck_handle = clk_get(NULL, "dsp_ck");
312 if (IS_ERR(dsp_ck_handle)) {
313 printk(KERN_ERR "omapdsp: could not acquire dsp_ck handle.\n");
314 return PTR_ERR(dsp_ck_handle);
317 api_ck_handle = clk_get(NULL, "api_ck");
318 if (IS_ERR(api_ck_handle)) {
319 printk(KERN_ERR "omapdsp: could not acquire api_ck handle.\n");
320 if (dsp_ck_handle != NULL)
321 clk_put(dsp_ck_handle);
322 return PTR_ERR(api_ck_handle);
325 /* This is needed for McBSP init, released in late_initcall */
326 clk_enable(api_ck_handle);
332 #elif defined(CONFIG_ARCH_OMAP2)
333 dsp_fck_handle = clk_get(NULL, "dsp_fck");
334 if (IS_ERR(dsp_fck_handle)) {
335 printk(KERN_ERR "omapdsp: could not acquire dsp_fck handle.\n");
336 return PTR_ERR(dsp_fck_handle);
339 dsp_ick_handle = clk_get(NULL, "dsp_ick");
340 if (IS_ERR(dsp_ick_handle)) {
341 printk(KERN_ERR "omapdsp: could not acquire dsp_ick handle.\n");
342 if (dsp_fck_handle != NULL)
343 clk_put(dsp_fck_handle);
344 return PTR_ERR(dsp_ick_handle);
349 pr_info("omap_dsp_init() done\n");
353 #if defined(CONFIG_ARCH_OMAP1)
354 static int __dsp_late_init(void)
356 clk_disable(api_ck_handle);
359 late_initcall(__dsp_late_init);
362 static void dsp_cpustat_update(void)
367 if (cpustat.req == CPUSTAT_RUN) {
368 if (cpustat.stat < CPUSTAT_RUN) {
369 #if defined(CONFIG_ARCH_OMAP1)
371 clk_enable(api_ck_handle);
374 #elif defined(CONFIG_ARCH_OMAP2)
375 __dsp_core_disable();
379 cpustat.stat = CPUSTAT_RUN;
380 if (omap_dsp != NULL)
381 enable_irq(omap_dsp->mmu_irq);
386 /* cpustat.req < CPUSTAT_RUN */
388 if (cpustat.stat == CPUSTAT_RUN) {
389 if (omap_dsp != NULL)
390 disable_irq(omap_dsp->mmu_irq);
391 #ifdef CONFIG_ARCH_OMAP1
392 clk_disable(api_ck_handle);
396 #ifdef CONFIG_ARCH_OMAP1
398 * (1) when ARM wants DARAM access, MPUI should be SAM and
399 * DSP needs to be on.
400 * (2) if any bits of icr is masked, we can not enter global idle.
402 if ((cpustat.req == CPUSTAT_CPU_IDLE) ||
403 (cpustat.usecount.mem > 0) ||
404 (cpustat.usecount.mem_delayed > 0) ||
405 ((cpustat.usecount.mpui > 0) && (cpustat.icrmask != 0xffff))) {
406 if (cpustat.stat != CPUSTAT_CPU_IDLE) {
408 cpustat.stat = CPUSTAT_CPU_IDLE;
414 * when ARM only needs MPUI access, MPUI can be HOM and
417 if ((cpustat.req == CPUSTAT_GBL_IDLE) ||
418 (cpustat.usecount.mpui > 0)) {
419 if (cpustat.stat != CPUSTAT_GBL_IDLE) {
421 cpustat.stat = CPUSTAT_GBL_IDLE;
425 #endif /* CONFIG_ARCH_OMAP1 */
428 * no user, no request
430 if (cpustat.stat != CPUSTAT_RESET) {
431 #if defined(CONFIG_ARCH_OMAP1)
433 #elif defined(CONFIG_ARCH_OMAP2)
434 __dsp_core_disable();
436 cpustat.stat = CPUSTAT_RESET;
440 void dsp_cpustat_request(enum cpustat_e req)
442 mutex_lock(&cpustat.lock);
444 dsp_cpustat_update();
445 mutex_unlock(&cpustat.lock);
448 enum cpustat_e dsp_cpustat_get_stat(void)
453 u16 dsp_cpustat_get_icrmask(void)
455 return cpustat.icrmask;
458 void dsp_cpustat_set_icrmask(u16 mask)
460 mutex_lock(&cpustat.lock);
461 cpustat.icrmask = mask;
462 dsp_cpustat_update();
463 mutex_unlock(&cpustat.lock);
466 #ifdef CONFIG_ARCH_OMAP1
467 void omap_dsp_request_mpui(void)
469 mutex_lock(&cpustat.lock);
470 if (cpustat.usecount.mpui++ == 0)
471 dsp_cpustat_update();
472 mutex_unlock(&cpustat.lock);
475 void omap_dsp_release_mpui(void)
477 mutex_lock(&cpustat.lock);
478 if (cpustat.usecount.mpui-- == 0) {
480 "omapdsp: unbalanced mpui request/release detected.\n"
481 " cpustat.usecount.mpui is going to be "
482 "less than zero! ... fixed to be zero.\n");
483 cpustat.usecount.mpui = 0;
485 if (cpustat.usecount.mpui == 0)
486 dsp_cpustat_update();
487 mutex_unlock(&cpustat.lock);
490 int omap_dsp_request_mem(void)
494 mutex_lock(&cpustat.lock);
495 if ((cpustat.usecount.mem++ == 0) &&
496 (cpustat.usecount.mem_delayed == 0)) {
497 if (cpustat.mem_req_cb) {
498 if ((ret = cpustat.mem_req_cb()) < 0) {
499 cpustat.usecount.mem--;
503 dsp_cpustat_update();
506 mutex_unlock(&cpustat.lock);
512 * release_mem will be delayed.
514 static void do_release_mem(struct work_struct *dummy)
516 mutex_lock(&cpustat.lock);
517 cpustat.usecount.mem_delayed = 0;
518 if (cpustat.usecount.mem == 0) {
519 dsp_cpustat_update();
520 if (cpustat.mem_rel_cb)
521 cpustat.mem_rel_cb();
523 mutex_unlock(&cpustat.lock);
526 static DECLARE_DELAYED_WORK(mem_rel_work, do_release_mem);
528 int omap_dsp_release_mem(void)
530 mutex_lock(&cpustat.lock);
532 /* cancel previous release work */
533 cancel_delayed_work(&mem_rel_work);
534 cpustat.usecount.mem_delayed = 0;
536 if (cpustat.usecount.mem-- == 0) {
538 "omapdsp: unbalanced memory request/release detected.\n"
539 " cpustat.usecount.mem is going to be "
540 "less than zero! ... fixed to be zero.\n");
541 cpustat.usecount.mem = 0;
543 if (cpustat.usecount.mem == 0) {
544 cpustat.usecount.mem_delayed = 1;
545 schedule_delayed_work(&mem_rel_work, HZ);
548 mutex_unlock(&cpustat.lock);
553 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void))
555 mutex_lock(&cpustat.lock);
557 cpustat.mem_req_cb = req_cb;
558 cpustat.mem_rel_cb = rel_cb;
561 * This function must be called while mem is enabled!
563 BUG_ON(cpustat.usecount.mem == 0);
565 mutex_unlock(&cpustat.lock);
568 void dsp_unregister_mem_cb(void)
570 mutex_lock(&cpustat.lock);
571 cpustat.mem_req_cb = NULL;
572 cpustat.mem_rel_cb = NULL;
573 mutex_unlock(&cpustat.lock);
576 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void)) { }
577 void dsp_unregister_mem_cb(void) { }
578 #endif /* CONFIG_ARCH_OMAP1 */
580 arch_initcall(omap_dsp_init);
582 #ifdef CONFIG_ARCH_OMAP1
583 EXPORT_SYMBOL(omap_dsp_request_mpui);
584 EXPORT_SYMBOL(omap_dsp_release_mpui);
585 EXPORT_SYMBOL(omap_dsp_request_mem);
586 EXPORT_SYMBOL(omap_dsp_release_mem);
587 #endif /* CONFIG_ARCH_OMAP1 */
589 #ifdef CONFIG_OMAP_DSP_MODULE
590 #if defined(CONFIG_ARCH_OMAP1)
591 EXPORT_SYMBOL(dsp_ck_handle);
592 EXPORT_SYMBOL(api_ck_handle);
593 #elif defined(CONFIG_ARCH_OMAP2)
594 EXPORT_SYMBOL(dsp_fck_handle);
595 EXPORT_SYMBOL(dsp_ick_handle);
597 EXPORT_SYMBOL(omap_dsp);
598 EXPORT_SYMBOL(dspmem_base);
599 EXPORT_SYMBOL(dspmem_size);
600 EXPORT_SYMBOL(daram_base);
601 EXPORT_SYMBOL(daram_size);
602 EXPORT_SYMBOL(saram_base);
603 EXPORT_SYMBOL(saram_size);
604 EXPORT_SYMBOL(dsp_set_rstvect);
605 EXPORT_SYMBOL(dsp_get_rstvect);
606 #ifdef CONFIG_ARCH_OMAP1
607 EXPORT_SYMBOL(dsp_set_idle_boot_base);
608 EXPORT_SYMBOL(dsp_reset_idle_boot_base);
609 #endif /* CONFIG_ARCH_OMAP1 */
610 EXPORT_SYMBOL(dsp_cpustat_request);
611 EXPORT_SYMBOL(dsp_cpustat_get_stat);
612 EXPORT_SYMBOL(dsp_cpustat_get_icrmask);
613 EXPORT_SYMBOL(dsp_cpustat_set_icrmask);
614 EXPORT_SYMBOL(dsp_register_mem_cb);
615 EXPORT_SYMBOL(dsp_unregister_mem_cb);
617 EXPORT_SYMBOL(__cpu_flush_kern_tlb_range);
618 EXPORT_SYMBOL(cpu_architecture);
619 EXPORT_SYMBOL(pmd_clear_bad);