arch/arm/plat-omap/dsp/dsp_common.c

   1 /*
   2  * linux/arch/arm/mach-omap/dsp/dsp_common.c
   3  *
   4  * OMAP DSP driver static part
   5  *
   6  * Copyright (C) 2002-2005 Nokia Corporation
   7  *
   8  * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23  *
  24  * 2005/06/13:  DSP Gateway version 3.3
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/errno.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/delay.h>
  32 #include <linux/mm.h>
  33 #include <asm/io.h>
  34 #include <asm/tlbflush.h>
  35 #include <asm/irq.h>
  36 #include <asm/arch/dsp.h>
  37 #include <asm/arch/tc.h>
  38 #include <asm/hardware/clock.h>
  39 #include "dsp_common.h"
  40
  41 struct clk *dsp_ck_handle;
  42 struct clk *api_ck_handle;
  43 unsigned long dspmem_base, dspmem_size,
  44               daram_base, daram_size,
  45               saram_base, saram_size;
  46
  47 struct cpustat {
  48         struct semaphore sem;
  49         enum e_cpustat stat;
  50         enum e_cpustat req;
  51         unsigned short icrmask;
  52         struct {
  53                 int mpui;
  54                 int mem;
  55                 int mem_delayed;
  56         } usecount;
  57         int (*mem_req_cb)(void);
  58         void (*mem_rel_cb)(void);
  59 };
  60 struct cpustat cpustat = {
  61         .sem = __SEMAPHORE_INIT(cpustat.sem, 1),
  62         .stat = CPUSTAT_RESET,
  63         .icrmask = 0xffff,
  64 };
  65
  66 int dsp_set_rstvect(unsigned long adr)
  67 {
  68         unsigned long *dst_adr;
  69
  70         if (adr >= DSPSPACE_SIZE)
  71                 return -EINVAL;
  72
  73         dst_adr = dspbyte_to_virt(DSP_BOOT_ADR_DIRECT);
  74         /* word swap */
  75         *dst_adr = ((adr & 0xffff) << 16) | (adr >> 16);
  76         /* fill 8 bytes! */
  77         *(dst_adr+1) = 0;
  78         /* direct boot */
  79         omap_writew(MPUI_DSP_BOOT_CONFIG_DIRECT, MPUI_DSP_BOOT_CONFIG);
  80
  81         return 0;
  82 }
  83
  84 static void simple_load_code(unsigned char *src_c, unsigned short *dst, int len)
  85 {
  86         int i;
  87         unsigned short *src = (unsigned short *)src_c;
  88         int len_w;
  89
  90         /* len must be multiple of 2. */
  91         if (len & 1)
  92                 BUG();
  93
  94         len_w = len / 2;
  95         for (i = 0; i < len_w; i++) {
  96                 /* byte swap copy */
  97                 *dst = ((*src & 0x00ff) << 8) |
  98                        ((*src & 0xff00) >> 8);
  99                 src++;
 100                 dst++;
 101         }
 102 }
 103
 104 /* program size must be multiple of 2 */
 105 #define GBL_IDLE_TEXT_SIZE      52
 106 #define GBL_IDLE_TEXT_INIT { \
 107         /* SAM */ \
 108         0x3c, 0x4a,                     /* 0x3c4a:     MOV 0x4, AR2 */ \
 109         0xf4, 0x41, 0xfc, 0xff,         /* 0xf441fcff: AND 0xfcff, *AR2 */ \
 110         /* disable WDT */ \
 111         0x76, 0x34, 0x04, 0xb8,         /* 0x763404b8: MOV 0x3404, AR3 */ \
 112         0xfb, 0x61, 0x00, 0xf5,         /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
 113         0x9a,                           /* 0x9a:       PORT */ \
 114         0xfb, 0x61, 0x00, 0xa0,         /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
 115         0x9a,                           /* 0x9a:       PORT */ \
 116         /* *IER0 = 0, *IER1 = 0 */ \
 117         0x3c, 0x0b,                     /* 0x3c0b:     MOV 0x0, AR3 */ \
 118         0xe6, 0x61, 0x00,               /* 0xe66100:   MOV 0, *AR3 */ \
 119         0x76, 0x00, 0x45, 0xb8,         /* 0x76004508: MOV 0x45, AR3 */ \
 120         0xe6, 0x61, 0x00,               /* 0xe66100:   MOV 0, *AR3 */ \
 121         /* *ICR = 0xffff */ \
 122         0x3c, 0x1b,                     /* 0x3c1b:     MOV 0x1, AR3 */ \
 123         0xfb, 0x61, 0xff, 0xff,         /* 0xfb61ffff: MOV 0xffff, *AR3 */ \
 124         0x9a,                           /* 0x9a:       PORT */ \
 125         /* HOM */ \
 126         0xf5, 0x41, 0x03, 0x00,         /* 0xf5410300: OR 0x0300, *AR2 */ \
 127         /* idle and loop forever */ \
 128         0x7a, 0x00, 0x00, 0x0c,         /* 0x7a00000c: IDLE */ \
 129         0x4a, 0x7a,                     /* 0x4a7a:     B -6 (infinite loop) */ \
 130         0x20, 0x20, 0x20,               /* 0x20:       NOP */ \
 131 }
 132
 133 /* program size must be multiple of 2 */
 134 #define CPU_IDLE_TEXT_SIZE      48
 135 #define CPU_IDLE_TEXT_INIT(icrh, icrl) { \
 136         /* SAM */ \
 137         0x3c, 0x4b,                     /* 0x3c4b:     MOV 0x4, AR3 */ \
 138         0xf4, 0x61, 0xfc, 0xff,         /* 0xf461fcff: AND 0xfcff, *AR3 */ \
 139         /* disable WDT */ \
 140         0x76, 0x34, 0x04, 0xb8,         /* 0x763404b8: MOV 0x3404, AR3 */ \
 141         0xfb, 0x61, 0x00, 0xf5,         /* 0xfb6100f5: MOV 0x00f5, *AR3 */ \
 142         0x9a,                           /* 0x9a:       PORT */ \
 143         0xfb, 0x61, 0x00, 0xa0,         /* 0xfb6100a0: MOV 0x00a0, *AR3 */ \
 144         0x9a,                           /* 0x9a:       PORT */ \
 145         /* *IER0 = 0, *IER1 = 0 */ \
 146         0x3c, 0x0b,                     /* 0x3c0b:     MOV 0x0, AR3 */ \
 147         0xe6, 0x61, 0x00,               /* 0xe66100:   MOV 0, *AR3 */ \
 148         0x76, 0x00, 0x45, 0xb8,         /* 0x76004508: MOV 0x45, AR3 */ \
 149         0xe6, 0x61, 0x00,               /* 0xe66100:   MOV 0, *AR3 */ \
 150         /* set ICR = icr */ \
 151         0x3c, 0x1b,                     /* 0x3c1b:     MOV AR3 0x1 */ \
 152         0xfb, 0x61, (icrh), (icrl),     /* 0xfb61****: MOV *AR3, icr */ \
 153         0x9a,                           /* 0x9a:       PORT */ \
 154         /* idle and loop forever */ \
 155         0x7a, 0x00, 0x00, 0x0c,         /* 0x7a00000c: IDLE */ \
 156         0x4a, 0x7a,                     /* 0x4a7a:     B -6 (infinite loop) */ \
 157         0x20, 0x20, 0x20                /* 0x20: nop */ \
 158 }
 159
 160 /*
 161  * idle_boot base:
 162  * Initialized with DSP_BOOT_ADR_MPUI (=0x010000).
 163  * This value is used before DSP Gateway driver is initialized.
 164  * DSP Gateway driver will overwrite this value with other value,
 165  * to avoid confliction with the user program.
 166  */
 167 static unsigned long idle_boot_base = DSP_BOOT_ADR_MPUI;
 168
 169 static void dsp_gbl_idle(void)
 170 {
 171         unsigned char idle_text[GBL_IDLE_TEXT_SIZE] = GBL_IDLE_TEXT_INIT;
 172
 173         __dsp_reset();
 174         clk_enable(api_ck_handle);
 175
 176 #if 0
 177         omap_writew(MPUI_DSP_BOOT_CONFIG_IDLE, MPUI_DSP_BOOT_CONFIG);
 178 #endif
 179         simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
 180                          GBL_IDLE_TEXT_SIZE);
 181         if (idle_boot_base == DSP_BOOT_ADR_MPUI)
 182                 omap_writew(MPUI_DSP_BOOT_CONFIG_MPUI, MPUI_DSP_BOOT_CONFIG);
 183         else
 184                 dsp_set_rstvect(idle_boot_base);
 185
 186         __dsp_run();
 187         udelay(100);    /* to make things stable */
 188         clk_disable(api_ck_handle);
 189 }
 190
 191 static void dsp_cpu_idle(void)
 192 {
 193         unsigned short icr_tmp;
 194         unsigned char icrh, icrl;
 195
 196         __dsp_reset();
 197         clk_enable(api_ck_handle);
 198
 199         /*
 200          * icr settings:
 201          * DMA should not sleep for DARAM/SARAM access
 202          * DPLL should not sleep while any other domain is active
 203          */
 204         icr_tmp = cpustat.icrmask & ~(DSPREG_ICR_DMA_IDLE_DOMAIN |
 205                                       DSPREG_ICR_DPLL_IDLE_DOMAIN);
 206         icrh = icr_tmp >> 8;
 207         icrl = icr_tmp & 0xff;
 208         {
 209                 unsigned char idle_text[CPU_IDLE_TEXT_SIZE] = CPU_IDLE_TEXT_INIT(icrh, icrl);
 210                 simple_load_code(idle_text, dspbyte_to_virt(idle_boot_base),
 211                                  CPU_IDLE_TEXT_SIZE);
 212         }
 213         if (idle_boot_base == DSP_BOOT_ADR_MPUI)
 214                 omap_writew(MPUI_DSP_BOOT_CONFIG_MPUI, MPUI_DSP_BOOT_CONFIG);
 215         else
 216                 dsp_set_rstvect(idle_boot_base);
 217         __dsp_run();
 218         udelay(100);    /* to make things stable */
 219         clk_disable(api_ck_handle);
 220 }
 221
 222 void dsp_set_idle_boot_base(unsigned long adr, size_t size)
 223 {
 224         if (adr == idle_boot_base)
 225                 return;
 226         idle_boot_base = adr;
 227         if ((size < GBL_IDLE_TEXT_SIZE) ||
 228             (size < CPU_IDLE_TEXT_SIZE)) {
 229                 printk(KERN_ERR
 230                        "omapdsp: size for idle program is not enough!\n");
 231                 BUG();
 232         }
 233
 234         /* restart idle program with new base address */
 235         if (cpustat.stat == CPUSTAT_GBL_IDLE)
 236                 dsp_gbl_idle();
 237         if (cpustat.stat == CPUSTAT_CPU_IDLE)
 238                 dsp_cpu_idle();
 239 }
 240
 241 static int init_done;
 242
 243 static int __init omap_dsp_init(void)
 244 {
 245         dspmem_size = 0;
 246 #ifdef CONFIG_ARCH_OMAP15XX
 247         if (cpu_is_omap1510()) {
 248                 dspmem_base = OMAP1510_DSP_BASE;
 249                 dspmem_size = OMAP1510_DSP_SIZE;
 250                 daram_base = OMAP1510_DARAM_BASE;
 251                 daram_size = OMAP1510_DARAM_SIZE;
 252                 saram_base = OMAP1510_SARAM_BASE;
 253                 saram_size = OMAP1510_SARAM_SIZE;
 254         }
 255 #endif
 256 #ifdef CONFIG_ARCH_OMAP16XX
 257         if (cpu_is_omap16xx()) {
 258                 dspmem_base = OMAP16XX_DSP_BASE;
 259                 dspmem_size = OMAP16XX_DSP_SIZE;
 260                 daram_base = OMAP16XX_DARAM_BASE;
 261                 daram_size = OMAP16XX_DARAM_SIZE;
 262                 saram_base = OMAP16XX_SARAM_BASE;
 263                 saram_size = OMAP16XX_SARAM_SIZE;
 264         }
 265 #endif
 266         if (dspmem_size == 0) {
 267                 printk(KERN_ERR "omapdsp: unsupported omap architecture.\n");
 268                 return -ENODEV;
 269         }
 270
 271         dsp_ck_handle = clk_get(0, "dsp_ck");
 272         if (IS_ERR(dsp_ck_handle)) {
 273                 printk(KERN_ERR "omapdsp: could not acquire dsp_ck handle.\n");
 274                 return PTR_ERR(dsp_ck_handle);
 275         }
 276
 277         api_ck_handle = clk_get(0, "api_ck");
 278         if (IS_ERR(api_ck_handle)) {
 279                 printk(KERN_ERR "omapdsp: could not acquire api_ck handle.\n");
 280                 return PTR_ERR(api_ck_handle);
 281         }
 282
 283         __dsp_enable();
 284         mpui_byteswap_off();
 285         mpui_wordswap_on();
 286         tc_wordswap();
 287
 288         init_done = 1;
 289         return 0;
 290 }
 291
 292 static void dsp_cpustat_update(void)
 293 {
 294         if (!init_done)
 295                 omap_dsp_init();
 296
 297         if (cpustat.req == CPUSTAT_RUN) {
 298                 if (cpustat.stat < CPUSTAT_RUN) {
 299                         __dsp_reset();
 300                         clk_enable(api_ck_handle);
 301                         udelay(10);
 302                         __dsp_run();
 303                         cpustat.stat = CPUSTAT_RUN;
 304                         enable_irq(INT_DSP_MMU);
 305                 }
 306                 return;
 307         }
 308
 309         /* cpustat.stat < CPUSTAT_RUN */
 310
 311         if (cpustat.stat == CPUSTAT_RUN) {
 312                 disable_irq(INT_DSP_MMU);
 313                 clk_disable(api_ck_handle);
 314         }
 315
 316         /*
 317          * (1) when ARM wants DARAM access, MPUI should be SAM and
 318          *     DSP needs to be on.
 319          * (2) if any bits of icr is masked, we can not enter global idle.
 320          */
 321         if ((cpustat.req == CPUSTAT_CPU_IDLE) ||
 322             (cpustat.usecount.mem > 0) ||
 323             (cpustat.usecount.mem_delayed > 0) ||
 324             ((cpustat.usecount.mpui > 0) && (cpustat.icrmask != 0xffff))) {
 325                 if (cpustat.stat != CPUSTAT_CPU_IDLE) {
 326                         dsp_cpu_idle();
 327                         cpustat.stat = CPUSTAT_CPU_IDLE;
 328                 }
 329                 return;
 330         }
 331
 332         /*
 333          * when ARM only needs MPUI access, MPUI can be HOM and
 334          * DSP can be idling.
 335          */
 336         if ((cpustat.req == CPUSTAT_GBL_IDLE) ||
 337             (cpustat.usecount.mpui > 0)) {
 338                 if (cpustat.stat != CPUSTAT_GBL_IDLE) {
 339                         dsp_gbl_idle();
 340                         cpustat.stat = CPUSTAT_GBL_IDLE;
 341                 }
 342                 return;
 343         }
 344
 345         /*
 346          * no user, no request
 347          */
 348         if (cpustat.stat != CPUSTAT_RESET) {
 349                 __dsp_reset();
 350                 cpustat.stat = CPUSTAT_RESET;
 351         }
 352 }
 353
 354 void dsp_cpustat_request(enum e_cpustat req)
 355 {
 356         down(&cpustat.sem);
 357         cpustat.req = req;
 358         dsp_cpustat_update();
 359         up(&cpustat.sem);
 360 }
 361
 362 enum e_cpustat dsp_cpustat_get_stat(void)
 363 {
 364         return cpustat.stat;
 365 }
 366
 367 unsigned short dsp_cpustat_get_icrmask(void)
 368 {
 369         return cpustat.icrmask;
 370 }
 371
 372 void dsp_cpustat_set_icrmask(unsigned short mask)
 373 {
 374         down(&cpustat.sem);
 375         cpustat.icrmask = mask;
 376         dsp_cpustat_update();
 377         up(&cpustat.sem);
 378 }
 379
 380 void omap_dsp_request_mpui(void)
 381 {
 382         down(&cpustat.sem);
 383         if (cpustat.usecount.mpui++ == 0)
 384                 dsp_cpustat_update();
 385         up(&cpustat.sem);
 386 }
 387
 388 void omap_dsp_release_mpui(void)
 389 {
 390         down(&cpustat.sem);
 391         if (cpustat.usecount.mpui-- == 0) {
 392                 printk(KERN_ERR
 393                        "omapdsp: unbalanced mpui request/release detected.\n"
 394                        "         cpustat.usecount.mpui is going to be "
 395                        "less than zero! ... fixed to be zero.\n");
 396                 cpustat.usecount.mpui = 0;
 397         }
 398         if (cpustat.usecount.mpui == 0)
 399                 dsp_cpustat_update();
 400         up(&cpustat.sem);
 401 }
 402
 403 int omap_dsp_request_mem(void)
 404 {
 405         int ret = 0;
 406
 407         down(&cpustat.sem);
 408         if ((cpustat.usecount.mem++ == 0) &&
 409             (cpustat.usecount.mem_delayed == 0)) {
 410                 if (cpustat.mem_req_cb) {
 411                         if ((ret = cpustat.mem_req_cb()) < 0) {
 412                                 cpustat.usecount.mem--;
 413                                 goto out;
 414                         }
 415                 }
 416                 dsp_cpustat_update();
 417         }
 418 out:
 419         up(&cpustat.sem);
 420
 421         return ret;
 422 }
 423
 424 /*
 425  * release_mem will be delayed.
 426  */
 427 static void do_release_mem(void) {
 428         down(&cpustat.sem);
 429         cpustat.usecount.mem_delayed = 0;
 430         if (cpustat.usecount.mem == 0) {
 431                 dsp_cpustat_update();
 432                 if (cpustat.mem_rel_cb)
 433                         cpustat.mem_rel_cb();
 434         }
 435         up(&cpustat.sem);
 436 }
 437
 438 static DECLARE_WORK(mem_rel_work, (void (*)(void *))do_release_mem, NULL);
 439
 440 int omap_dsp_release_mem(void)
 441 {
 442         down(&cpustat.sem);
 443
 444         /* cancel previous release work */
 445         cancel_delayed_work(&mem_rel_work);
 446         cpustat.usecount.mem_delayed = 0;
 447
 448         if (cpustat.usecount.mem-- == 0) {
 449                 printk(KERN_ERR
 450                        "omapdsp: unbalanced memory request/release detected.\n"
 451                        "         cpustat.usecount.mem is going to be "
 452                        "less than zero! ... fixed to be zero.\n");
 453                 cpustat.usecount.mem = 0;
 454         }
 455         if (cpustat.usecount.mem == 0) {
 456                 cpustat.usecount.mem_delayed = 1;
 457                 schedule_delayed_work(&mem_rel_work, HZ);
 458         }
 459
 460         up(&cpustat.sem);
 461
 462         return 0;
 463 }
 464
 465 void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void))
 466 {
 467         down(&cpustat.sem);
 468
 469         cpustat.mem_req_cb = req_cb;
 470         cpustat.mem_rel_cb = rel_cb;
 471
 472         /*
 473          * This function must be called while mem is enabled!
 474          */
 475         BUG_ON(cpustat.usecount.mem == 0);
 476
 477         up(&cpustat.sem);
 478 }
 479
 480 void dsp_unregister_mem_cb(void)
 481 {
 482         down(&cpustat.sem);
 483         cpustat.mem_req_cb = NULL;
 484         cpustat.mem_rel_cb = NULL;
 485         up(&cpustat.sem);
 486 }
 487
 488 arch_initcall(omap_dsp_init);
 489
 490 EXPORT_SYMBOL(omap_dsp_request_mpui);
 491 EXPORT_SYMBOL(omap_dsp_release_mpui);
 492 EXPORT_SYMBOL(omap_dsp_request_mem);
 493 EXPORT_SYMBOL(omap_dsp_release_mem);
 494
 495 #ifdef CONFIG_OMAP_DSP_MODULE
 496 EXPORT_SYMBOL(dsp_ck_handle);
 497 EXPORT_SYMBOL(api_ck_handle);
 498 EXPORT_SYMBOL(dspmem_base);
 499 EXPORT_SYMBOL(dspmem_size);
 500 EXPORT_SYMBOL(daram_base);
 501 EXPORT_SYMBOL(daram_size);
 502 EXPORT_SYMBOL(saram_base);
 503 EXPORT_SYMBOL(saram_size);
 504 EXPORT_SYMBOL(dsp_set_rstvect);
 505 EXPORT_SYMBOL(dsp_set_idle_boot_base);
 506 EXPORT_SYMBOL(dsp_cpustat_request);
 507 EXPORT_SYMBOL(dsp_cpustat_get_stat);
 508 EXPORT_SYMBOL(dsp_cpustat_get_icrmask);
 509 EXPORT_SYMBOL(dsp_cpustat_set_icrmask);
 510 EXPORT_SYMBOL(dsp_register_mem_cb);
 511 EXPORT_SYMBOL(dsp_unregister_mem_cb);
 512
 513 EXPORT_SYMBOL(__cpu_flush_kern_tlb_range);
 514 #endif