arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * You should have received a copy of the  GNU General Public License along
  25  * with this program; if not, write  to the Free Software Foundation, Inc.,
  26  * 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/errno.h>
  32 #include <linux/list.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <asm/hardware.h>
  36 #include <asm/arch/dmtimer.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/irqs.h>
  39
  40 /* register offsets */
  41 #define OMAP_TIMER_ID_REG               0x00
  42 #define OMAP_TIMER_OCP_CFG_REG          0x10
  43 #define OMAP_TIMER_SYS_STAT_REG         0x14
  44 #define OMAP_TIMER_STAT_REG             0x18
  45 #define OMAP_TIMER_INT_EN_REG           0x1c
  46 #define OMAP_TIMER_WAKEUP_EN_REG        0x20
  47 #define OMAP_TIMER_CTRL_REG             0x24
  48 #define OMAP_TIMER_COUNTER_REG          0x28
  49 #define OMAP_TIMER_LOAD_REG             0x2c
  50 #define OMAP_TIMER_TRIGGER_REG          0x30
  51 #define OMAP_TIMER_WRITE_PEND_REG       0x34
  52 #define OMAP_TIMER_MATCH_REG            0x38
  53 #define OMAP_TIMER_CAPTURE_REG          0x3c
  54 #define OMAP_TIMER_IF_CTRL_REG          0x40
  55
  56 /* timer control reg bits */
  57 #define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  58 #define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  59 #define OMAP_TIMER_CTRL_PT              (1 << 12)
  60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  63 #define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  64 #define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
  65 #define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
  66 #define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
  67 #define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
  68 #define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
  69
  70 struct omap_dm_timer {
  71         unsigned long phys_base;
  72         int irq;
  73 #ifdef CONFIG_ARCH_OMAP2
  74         struct clk *iclk, *fclk;
  75 #endif
  76         void __iomem *io_base;
  77         unsigned reserved:1;
  78         unsigned enabled:1;
  79 };
  80
  81 #ifdef CONFIG_ARCH_OMAP1
  82
  83 #define omap_dm_clk_enable(x)
  84 #define omap_dm_clk_disable(x)
  85 #define omap2_dm_timers                 NULL
  86 #define omap2_dm_source_names           NULL
  87 #define omap2_dm_source_clocks          NULL
  88
  89 static struct omap_dm_timer omap1_dm_timers[] = {
  90         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
  91         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
  92         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
  93         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
  94         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
  95         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
  96         { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
  97         { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
  98 };
  99
 100 static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
 101
 102 #elif defined(CONFIG_ARCH_OMAP2)
 103
 104 #define omap_dm_clk_enable(x)           clk_enable(x)
 105 #define omap_dm_clk_disable(x)          clk_disable(x)
 106 #define omap1_dm_timers                 NULL
 107
 108 static struct omap_dm_timer omap2_dm_timers[] = {
 109         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
 110         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
 111         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
 112         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 113         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 114         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 115         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 116         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 117         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 118         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 119         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 120         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 121 };
 122
 123 static const char *omap2_dm_source_names[] __initdata = {
 124         "sys_ck",
 125         "func_32k_ck",
 126         "alt_ck",
 127         NULL
 128 };
 129
 130 static struct clk **omap2_dm_source_clocks[3];
 131 static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 132
 133 #else
 134
 135 #error OMAP architecture not supported!
 136
 137 #endif
 138
 139 static struct omap_dm_timer *dm_timers;
 140 static char **dm_source_names;
 141 static struct clk **dm_source_clocks;
 142
 143 static spinlock_t dm_timer_lock;
 144
 145 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
 146 {
 147         return readl(timer->io_base + reg);
 148 }
 149
 150 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
 151 {
 152         writel(value, timer->io_base + reg);
 153         while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
 154                 ;
 155 }
 156
 157 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 158 {
 159         int c;
 160
 161         c = 0;
 162         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 163                 c++;
 164                 if (c > 100000) {
 165                         printk(KERN_ERR "Timer failed to reset\n");
 166                         return;
 167                 }
 168         }
 169 }
 170
 171 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 172 {
 173         u32 l;
 174
 175         if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
 176                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 177                 omap_dm_timer_wait_for_reset(timer);
 178         }
 179         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 180
 181         /* Set to smart-idle mode */
 182         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 183         l |= 0x02 << 3;
 184
 185         if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
 186                 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
 187                 l |= 1 << 2;
 188                 /* Non-posted mode */
 189                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
 190         }
 191         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 192 }
 193
 194 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
 195 {
 196         omap_dm_timer_enable(timer);
 197         omap_dm_timer_reset(timer);
 198 }
 199
 200 struct omap_dm_timer *omap_dm_timer_request(void)
 201 {
 202         struct omap_dm_timer *timer = NULL;
 203         unsigned long flags;
 204         int i;
 205
 206         spin_lock_irqsave(&dm_timer_lock, flags);
 207         for (i = 0; i < dm_timer_count; i++) {
 208                 if (dm_timers[i].reserved)
 209                         continue;
 210
 211                 timer = &dm_timers[i];
 212                 timer->reserved = 1;
 213                 break;
 214         }
 215         spin_unlock_irqrestore(&dm_timer_lock, flags);
 216
 217         if (timer != NULL)
 218                 omap_dm_timer_prepare(timer);
 219
 220         return timer;
 221 }
 222
 223 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 224 {
 225         struct omap_dm_timer *timer;
 226         unsigned long flags;
 227
 228         spin_lock_irqsave(&dm_timer_lock, flags);
 229         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 230                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 231                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 232                        __FILE__, __LINE__, __FUNCTION__, id);
 233                 dump_stack();
 234                 return NULL;
 235         }
 236
 237         timer = &dm_timers[id-1];
 238         timer->reserved = 1;
 239         spin_unlock_irqrestore(&dm_timer_lock, flags);
 240
 241         omap_dm_timer_prepare(timer);
 242
 243         return timer;
 244 }
 245
 246 void omap_dm_timer_free(struct omap_dm_timer *timer)
 247 {
 248         omap_dm_timer_enable(timer);
 249         omap_dm_timer_reset(timer);
 250         omap_dm_timer_disable(timer);
 251
 252         WARN_ON(!timer->reserved);
 253         timer->reserved = 0;
 254 }
 255
 256 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 257 {
 258         if (timer->enabled)
 259                 return;
 260
 261         omap_dm_clk_enable(timer->fclk);
 262         omap_dm_clk_enable(timer->iclk);
 263
 264         timer->enabled = 1;
 265 }
 266
 267 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 268 {
 269         if (!timer->enabled)
 270                 return;
 271
 272         omap_dm_clk_disable(timer->iclk);
 273         omap_dm_clk_disable(timer->fclk);
 274
 275         timer->enabled = 0;
 276 }
 277
 278 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 279 {
 280         return timer->irq;
 281 }
 282
 283 #if defined(CONFIG_ARCH_OMAP1)
 284
 285 /**
 286  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 287  * @inputmask: current value of idlect mask
 288  */
 289 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 290 {
 291         int i;
 292
 293         /* If ARMXOR cannot be idled this function call is unnecessary */
 294         if (!(inputmask & (1 << 1)))
 295                 return inputmask;
 296
 297         /* If any active timer is using ARMXOR return modified mask */
 298         for (i = 0; i < dm_timer_count; i++) {
 299                 u32 l;
 300
 301                 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
 302                 if (l & OMAP_TIMER_CTRL_ST) {
 303                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 304                                 inputmask &= ~(1 << 1);
 305                         else
 306                                 inputmask &= ~(1 << 2);
 307                 }
 308         }
 309
 310         return inputmask;
 311 }
 312
 313 #elif defined(CONFIG_ARCH_OMAP2)
 314
 315 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 316 {
 317         return timer->fclk;
 318 }
 319
 320 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 321 {
 322         BUG();
 323
 324         return 0;
 325 }
 326
 327 #endif
 328
 329 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 330 {
 331         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 332 }
 333
 334 void omap_dm_timer_start(struct omap_dm_timer *timer)
 335 {
 336         u32 l;
 337
 338         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 339         if (!(l & OMAP_TIMER_CTRL_ST)) {
 340                 l |= OMAP_TIMER_CTRL_ST;
 341                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 342         }
 343 }
 344
 345 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 346 {
 347         u32 l;
 348
 349         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 350         if (l & OMAP_TIMER_CTRL_ST) {
 351                 l &= ~0x1;
 352                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 353         }
 354 }
 355
 356 #ifdef CONFIG_ARCH_OMAP1
 357
 358 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 359 {
 360         int n = (timer - dm_timers) << 1;
 361         u32 l;
 362
 363         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 364         l |= source << n;
 365         omap_writel(l, MOD_CONF_CTRL_1);
 366 }
 367
 368 #else
 369
 370 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 371 {
 372         if (source < 0 || source >= 3)
 373                 return;
 374
 375         clk_disable(timer->fclk);
 376         clk_set_parent(timer->fclk, dm_source_clocks[source]);
 377         clk_enable(timer->fclk);
 378
 379         /* When the functional clock disappears, too quick writes seem to
 380          * cause an abort. */
 381         __delay(150000);
 382 }
 383
 384 #endif
 385
 386 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 387                             unsigned int load)
 388 {
 389         u32 l;
 390
 391         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 392         if (autoreload)
 393                 l |= OMAP_TIMER_CTRL_AR;
 394         else
 395                 l &= ~OMAP_TIMER_CTRL_AR;
 396         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 397         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 398         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 399 }
 400
 401 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 402                              unsigned int match)
 403 {
 404         u32 l;
 405
 406         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 407         if (enable)
 408                 l |= OMAP_TIMER_CTRL_CE;
 409         else
 410                 l &= ~OMAP_TIMER_CTRL_CE;
 411         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 412         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 413 }
 414
 415
 416 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 417                            int toggle, int trigger)
 418 {
 419         u32 l;
 420
 421         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 422         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 423                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 424         if (def_on)
 425                 l |= OMAP_TIMER_CTRL_SCPWM;
 426         if (toggle)
 427                 l |= OMAP_TIMER_CTRL_PT;
 428         l |= trigger << 10;
 429         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 430 }
 431
 432 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 433 {
 434         u32 l;
 435
 436         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 437         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 438         if (prescaler >= 0x00 && prescaler <= 0x07) {
 439                 l |= OMAP_TIMER_CTRL_PRE;
 440                 l |= prescaler << 2;
 441         }
 442         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 443 }
 444
 445 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 446                                   unsigned int value)
 447 {
 448         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 449         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
 450 }
 451
 452 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 453 {
 454         unsigned int l;
 455
 456         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 457
 458         return l;
 459 }
 460
 461 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 462 {
 463         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 464 }
 465
 466 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 467 {
 468         unsigned int l;
 469
 470         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 471
 472         return l;
 473 }
 474
 475 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 476 {
 477         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 478 }
 479
 480 int omap_dm_timers_active(void)
 481 {
 482         int i;
 483
 484         for (i = 0; i < dm_timer_count; i++) {
 485                 struct omap_dm_timer *timer;
 486
 487                 timer = &dm_timers[i];
 488
 489                 if (!timer->enabled)
 490                         continue;
 491
 492                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 493                     OMAP_TIMER_CTRL_ST) {
 494                         return 1;
 495                 }
 496         }
 497         return 0;
 498 }
 499
 500 int __init omap_dm_timer_init(void)
 501 {
 502         struct omap_dm_timer *timer;
 503         int i;
 504
 505         if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
 506                 return -ENODEV;
 507
 508         spin_lock_init(&dm_timer_lock);
 509
 510         if (cpu_class_is_omap1())
 511                 dm_timers = omap1_dm_timers;
 512         else if (cpu_is_omap24xx()) {
 513                 dm_timers = omap2_dm_timers;
 514                 dm_source_names = (char **)omap2_dm_source_names;
 515                 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
 516         }
 517
 518         if (cpu_class_is_omap2())
 519                 for (i = 0; dm_source_names[i] != NULL; i++)
 520                         dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
 521
 522         if (cpu_is_omap243x())
 523                 dm_timers[0].phys_base = 0x49018000;
 524
 525         for (i = 0; i < dm_timer_count; i++) {
 526                 timer = &dm_timers[i];
 527                 timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
 528 #ifdef CONFIG_ARCH_OMAP2
 529                 if (cpu_class_is_omap2()) {
 530                         char clk_name[16];
 531                         sprintf(clk_name, "gpt%d_ick", i + 1);
 532                         timer->iclk = clk_get(NULL, clk_name);
 533                         sprintf(clk_name, "gpt%d_fck", i + 1);
 534                         timer->fclk = clk_get(NULL, clk_name);
 535                 }
 536 #endif
 537         }
 538
 539         return 0;
 540 }