2 * linux/arch/arm/plat-omap/dmtimer.c
4 * OMAP Dual-Mode Timers
6 * Copyright (C) 2005 Nokia Corporation
7 * OMAP2 support by Juha Yrjola
8 * API improvements and OMAP2 clock framework support by Timo Teras
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
31 #include <linux/errno.h>
32 #include <linux/list.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <asm/hardware.h>
36 #include <asm/arch/dmtimer.h>
38 #include <asm/arch/irqs.h>
40 /* register offsets */
41 #define OMAP_TIMER_ID_REG 0x00
42 #define OMAP_TIMER_OCP_CFG_REG 0x10
43 #define OMAP_TIMER_SYS_STAT_REG 0x14
44 #define OMAP_TIMER_STAT_REG 0x18
45 #define OMAP_TIMER_INT_EN_REG 0x1c
46 #define OMAP_TIMER_WAKEUP_EN_REG 0x20
47 #define OMAP_TIMER_CTRL_REG 0x24
48 #define OMAP_TIMER_COUNTER_REG 0x28
49 #define OMAP_TIMER_LOAD_REG 0x2c
50 #define OMAP_TIMER_TRIGGER_REG 0x30
51 #define OMAP_TIMER_WRITE_PEND_REG 0x34
52 #define OMAP_TIMER_MATCH_REG 0x38
53 #define OMAP_TIMER_CAPTURE_REG 0x3c
54 #define OMAP_TIMER_IF_CTRL_REG 0x40
56 /* timer control reg bits */
57 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
58 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
59 #define OMAP_TIMER_CTRL_PT (1 << 12)
60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
63 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
64 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
65 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
66 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
67 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
68 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
70 struct omap_dm_timer {
71 unsigned long phys_base;
73 #ifdef CONFIG_ARCH_OMAP2
74 struct clk *iclk, *fclk;
76 void __iomem *io_base;
81 #ifdef CONFIG_ARCH_OMAP1
83 #define omap_dm_clk_enable(x)
84 #define omap_dm_clk_disable(x)
85 #define omap2_dm_timers NULL
86 #define omap2_dm_source_names NULL
87 #define omap2_dm_source_clocks NULL
89 static struct omap_dm_timer omap1_dm_timers[] = {
90 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
91 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
92 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
93 { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
94 { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
95 { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
96 { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
97 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
100 static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
102 #elif defined(CONFIG_ARCH_OMAP2)
104 #define omap_dm_clk_enable(x) clk_enable(x)
105 #define omap_dm_clk_disable(x) clk_disable(x)
106 #define omap1_dm_timers NULL
108 static struct omap_dm_timer omap2_dm_timers[] = {
109 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
110 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
111 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
112 { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
113 { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
114 { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
115 { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
116 { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
117 { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
118 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
119 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
120 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
123 static const char *omap2_dm_source_names[] __initdata = {
130 static struct clk **omap2_dm_source_clocks[3];
131 static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
135 #error OMAP architecture not supported!
139 static struct omap_dm_timer *dm_timers;
140 static char **dm_source_names;
141 static struct clk **dm_source_clocks;
143 static spinlock_t dm_timer_lock;
145 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
147 return readl(timer->io_base + reg);
150 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
152 writel(value, timer->io_base + reg);
153 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
157 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
162 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
165 printk(KERN_ERR "Timer failed to reset\n");
171 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
175 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
176 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
177 omap_dm_timer_wait_for_reset(timer);
179 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
181 /* Set to smart-idle mode */
182 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
185 if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
186 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
188 /* Non-posted mode */
189 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
191 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
194 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
196 omap_dm_timer_enable(timer);
197 omap_dm_timer_reset(timer);
200 struct omap_dm_timer *omap_dm_timer_request(void)
202 struct omap_dm_timer *timer = NULL;
206 spin_lock_irqsave(&dm_timer_lock, flags);
207 for (i = 0; i < dm_timer_count; i++) {
208 if (dm_timers[i].reserved)
211 timer = &dm_timers[i];
215 spin_unlock_irqrestore(&dm_timer_lock, flags);
218 omap_dm_timer_prepare(timer);
223 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
225 struct omap_dm_timer *timer;
228 spin_lock_irqsave(&dm_timer_lock, flags);
229 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
230 spin_unlock_irqrestore(&dm_timer_lock, flags);
231 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
232 __FILE__, __LINE__, __FUNCTION__, id);
237 timer = &dm_timers[id-1];
239 spin_unlock_irqrestore(&dm_timer_lock, flags);
241 omap_dm_timer_prepare(timer);
246 void omap_dm_timer_free(struct omap_dm_timer *timer)
248 omap_dm_timer_enable(timer);
249 omap_dm_timer_reset(timer);
250 omap_dm_timer_disable(timer);
252 WARN_ON(!timer->reserved);
256 void omap_dm_timer_enable(struct omap_dm_timer *timer)
261 omap_dm_clk_enable(timer->fclk);
262 omap_dm_clk_enable(timer->iclk);
267 void omap_dm_timer_disable(struct omap_dm_timer *timer)
272 omap_dm_clk_disable(timer->iclk);
273 omap_dm_clk_disable(timer->fclk);
278 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
283 #if defined(CONFIG_ARCH_OMAP1)
286 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
287 * @inputmask: current value of idlect mask
289 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
293 /* If ARMXOR cannot be idled this function call is unnecessary */
294 if (!(inputmask & (1 << 1)))
297 /* If any active timer is using ARMXOR return modified mask */
298 for (i = 0; i < dm_timer_count; i++) {
301 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
302 if (l & OMAP_TIMER_CTRL_ST) {
303 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
304 inputmask &= ~(1 << 1);
306 inputmask &= ~(1 << 2);
313 #elif defined(CONFIG_ARCH_OMAP2)
315 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
320 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
329 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
331 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
334 void omap_dm_timer_start(struct omap_dm_timer *timer)
338 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
339 if (!(l & OMAP_TIMER_CTRL_ST)) {
340 l |= OMAP_TIMER_CTRL_ST;
341 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
345 void omap_dm_timer_stop(struct omap_dm_timer *timer)
349 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
350 if (l & OMAP_TIMER_CTRL_ST) {
352 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
356 #ifdef CONFIG_ARCH_OMAP1
358 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
360 int n = (timer - dm_timers) << 1;
363 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
365 omap_writel(l, MOD_CONF_CTRL_1);
370 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
372 if (source < 0 || source >= 3)
375 clk_disable(timer->fclk);
376 clk_set_parent(timer->fclk, dm_source_clocks[source]);
377 clk_enable(timer->fclk);
379 /* When the functional clock disappears, too quick writes seem to
386 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
391 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
393 l |= OMAP_TIMER_CTRL_AR;
395 l &= ~OMAP_TIMER_CTRL_AR;
396 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
397 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
398 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
401 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
406 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
408 l |= OMAP_TIMER_CTRL_CE;
410 l &= ~OMAP_TIMER_CTRL_CE;
411 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
412 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
416 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
417 int toggle, int trigger)
421 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
422 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
423 OMAP_TIMER_CTRL_PT | (0x03 << 10));
425 l |= OMAP_TIMER_CTRL_SCPWM;
427 l |= OMAP_TIMER_CTRL_PT;
429 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
432 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
436 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
437 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
438 if (prescaler >= 0x00 && prescaler <= 0x07) {
439 l |= OMAP_TIMER_CTRL_PRE;
442 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
445 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
448 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
449 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
452 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
456 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
461 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
463 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
466 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
470 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
475 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
477 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
480 int omap_dm_timers_active(void)
484 for (i = 0; i < dm_timer_count; i++) {
485 struct omap_dm_timer *timer;
487 timer = &dm_timers[i];
492 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
493 OMAP_TIMER_CTRL_ST) {
500 int __init omap_dm_timer_init(void)
502 struct omap_dm_timer *timer;
505 if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
508 spin_lock_init(&dm_timer_lock);
510 if (cpu_class_is_omap1())
511 dm_timers = omap1_dm_timers;
512 else if (cpu_is_omap24xx()) {
513 dm_timers = omap2_dm_timers;
514 dm_source_names = (char **)omap2_dm_source_names;
515 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
518 if (cpu_class_is_omap2())
519 for (i = 0; dm_source_names[i] != NULL; i++)
520 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
522 if (cpu_is_omap243x())
523 dm_timers[0].phys_base = 0x49018000;
525 for (i = 0; i < dm_timer_count; i++) {
526 timer = &dm_timers[i];
527 timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
528 #ifdef CONFIG_ARCH_OMAP2
529 if (cpu_class_is_omap2()) {
531 sprintf(clk_name, "gpt%d_ick", i + 1);
532 timer->iclk = clk_get(NULL, clk_name);
533 sprintf(clk_name, "gpt%d_fck", i + 1);
534 timer->fclk = clk_get(NULL, clk_name);