arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/system.h>
  31 #include <mach/hardware.h>
  32 #include <asm/dma.h>
  33
  34 #include <mach/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE                 0x01
  47 #define OMAP_DMA_CCR_EN                 (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (*callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126
 127 static spinlock_t dma_chan_lock;
 128 static struct omap_dma_lch *dma_chan;
 129 static void __iomem *omap_dma_base;
 130
 131 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 132         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 133         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 134         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 135         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 136         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 137 };
 138
 139 static inline void disable_lnk(int lch);
 140 static void omap_disable_channel_irq(int lch);
 141 static inline void omap_enable_channel_irq(int lch);
 142
 143 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 144                                                 __func__);
 145
 146 #define dma_read(reg)                                                   \
 147 ({                                                                      \
 148         u32 __val;                                                      \
 149         if (cpu_class_is_omap1())                                       \
 150                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 151         else                                                            \
 152                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 153         __val;                                                          \
 154 })
 155
 156 #define dma_write(val, reg)                                             \
 157 ({                                                                      \
 158         if (cpu_class_is_omap1())                                       \
 159                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 160         else                                                            \
 161                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 162 })
 163
 164 #ifdef CONFIG_ARCH_OMAP15XX
 165 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 166 int omap_dma_in_1510_mode(void)
 167 {
 168         return enable_1510_mode;
 169 }
 170 #else
 171 #define omap_dma_in_1510_mode()         0
 172 #endif
 173
 174 #ifdef CONFIG_ARCH_OMAP1
 175 static inline int get_gdma_dev(int req)
 176 {
 177         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 178         int shift = ((req - 1) % 5) * 6;
 179
 180         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 181 }
 182
 183 static inline void set_gdma_dev(int req, int dev)
 184 {
 185         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 186         int shift = ((req - 1) % 5) * 6;
 187         u32 l;
 188
 189         l = omap_readl(reg);
 190         l &= ~(0x3f << shift);
 191         l |= (dev - 1) << shift;
 192         omap_writel(l, reg);
 193 }
 194 #else
 195 #define set_gdma_dev(req, dev)  do {} while (0)
 196 #endif
 197
 198 /* Omap1 only */
 199 static void clear_lch_regs(int lch)
 200 {
 201         int i;
 202         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 203
 204         for (i = 0; i < 0x2c; i += 2)
 205                 __raw_writew(0, lch_base + i);
 206 }
 207
 208 void omap_set_dma_priority(int lch, int dst_port, int priority)
 209 {
 210         unsigned long reg;
 211         u32 l;
 212
 213         if (cpu_class_is_omap1()) {
 214                 switch (dst_port) {
 215                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 216                         reg = OMAP_TC_OCPT1_PRIOR;
 217                         break;
 218                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 219                         reg = OMAP_TC_OCPT2_PRIOR;
 220                         break;
 221                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 222                         reg = OMAP_TC_EMIFF_PRIOR;
 223                         break;
 224                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 225                         reg = OMAP_TC_EMIFS_PRIOR;
 226                         break;
 227                 default:
 228                         BUG();
 229                         return;
 230                 }
 231                 l = omap_readl(reg);
 232                 l &= ~(0xf << 8);
 233                 l |= (priority & 0xf) << 8;
 234                 omap_writel(l, reg);
 235         }
 236
 237         if (cpu_class_is_omap2()) {
 238                 u32 ccr;
 239
 240                 ccr = dma_read(CCR(lch));
 241                 if (priority)
 242                         ccr |= (1 << 6);
 243                 else
 244                         ccr &= ~(1 << 6);
 245                 dma_write(ccr, CCR(lch));
 246         }
 247 }
 248 EXPORT_SYMBOL(omap_set_dma_priority);
 249
 250 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 251                                   int frame_count, int sync_mode,
 252                                   int dma_trigger, int src_or_dst_synch)
 253 {
 254         u32 l;
 255
 256         l = dma_read(CSDP(lch));
 257         l &= ~0x03;
 258         l |= data_type;
 259         dma_write(l, CSDP(lch));
 260
 261         if (cpu_class_is_omap1()) {
 262                 u16 ccr;
 263
 264                 ccr = dma_read(CCR(lch));
 265                 ccr &= ~(1 << 5);
 266                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 267                         ccr |= 1 << 5;
 268                 dma_write(ccr, CCR(lch));
 269
 270                 ccr = dma_read(CCR2(lch));
 271                 ccr &= ~(1 << 2);
 272                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 273                         ccr |= 1 << 2;
 274                 dma_write(ccr, CCR2(lch));
 275         }
 276
 277         if (cpu_class_is_omap2() && dma_trigger) {
 278                 u32 val;
 279
 280                 val = dma_read(CCR(lch));
 281                 val &= ~(3 << 19);
 282                 if (dma_trigger > 63)
 283                         val |= 1 << 20;
 284                 if (dma_trigger > 31)
 285                         val |= 1 << 19;
 286
 287                 val &= ~(0x1f);
 288                 val |= (dma_trigger & 0x1f);
 289
 290                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 291                         val |= 1 << 5;
 292                 else
 293                         val &= ~(1 << 5);
 294
 295                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 296                         val |= 1 << 18;
 297                 else
 298                         val &= ~(1 << 18);
 299
 300                 if (src_or_dst_synch)
 301                         val |= 1 << 24;         /* source synch */
 302                 else
 303                         val &= ~(1 << 24);      /* dest synch */
 304
 305                 dma_write(val, CCR(lch));
 306         }
 307
 308         dma_write(elem_count, CEN(lch));
 309         dma_write(frame_count, CFN(lch));
 310 }
 311 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 312
 313 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 314 {
 315         u16 w;
 316
 317         BUG_ON(omap_dma_in_1510_mode());
 318
 319         if (cpu_class_is_omap2()) {
 320                 REVISIT_24XX();
 321                 return;
 322         }
 323
 324         w = dma_read(CCR2(lch));
 325         w &= ~0x03;
 326
 327         switch (mode) {
 328         case OMAP_DMA_CONSTANT_FILL:
 329                 w |= 0x01;
 330                 break;
 331         case OMAP_DMA_TRANSPARENT_COPY:
 332                 w |= 0x02;
 333                 break;
 334         case OMAP_DMA_COLOR_DIS:
 335                 break;
 336         default:
 337                 BUG();
 338         }
 339         dma_write(w, CCR2(lch));
 340
 341         w = dma_read(LCH_CTRL(lch));
 342         w &= ~0x0f;
 343         /* Default is channel type 2D */
 344         if (mode) {
 345                 dma_write((u16)color, COLOR_L(lch));
 346                 dma_write((u16)(color >> 16), COLOR_U(lch));
 347                 w |= 1;         /* Channel type G */
 348         }
 349         dma_write(w, LCH_CTRL(lch));
 350 }
 351 EXPORT_SYMBOL(omap_set_dma_color_mode);
 352
 353 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 354 {
 355         if (cpu_class_is_omap2()) {
 356                 u32 csdp;
 357
 358                 csdp = dma_read(CSDP(lch));
 359                 csdp &= ~(0x3 << 16);
 360                 csdp |= (mode << 16);
 361                 dma_write(csdp, CSDP(lch));
 362         }
 363 }
 364 EXPORT_SYMBOL(omap_set_dma_write_mode);
 365
 366 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 367 {
 368         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 369                 u32 l;
 370
 371                 l = dma_read(LCH_CTRL(lch));
 372                 l &= ~0x7;
 373                 l |= mode;
 374                 dma_write(l, LCH_CTRL(lch));
 375         }
 376 }
 377 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 378
 379 /* Note that src_port is only for omap1 */
 380 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 381                              unsigned long src_start,
 382                              int src_ei, int src_fi)
 383 {
 384         u32 l;
 385
 386         if (cpu_class_is_omap1()) {
 387                 u16 w;
 388
 389                 w = dma_read(CSDP(lch));
 390                 w &= ~(0x1f << 2);
 391                 w |= src_port << 2;
 392                 dma_write(w, CSDP(lch));
 393         }
 394
 395         l = dma_read(CCR(lch));
 396         l &= ~(0x03 << 12);
 397         l |= src_amode << 12;
 398         dma_write(l, CCR(lch));
 399
 400         if (cpu_class_is_omap1()) {
 401                 dma_write(src_start >> 16, CSSA_U(lch));
 402                 dma_write((u16)src_start, CSSA_L(lch));
 403         }
 404
 405         if (cpu_class_is_omap2())
 406                 dma_write(src_start, CSSA(lch));
 407
 408         dma_write(src_ei, CSEI(lch));
 409         dma_write(src_fi, CSFI(lch));
 410 }
 411 EXPORT_SYMBOL(omap_set_dma_src_params);
 412
 413 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 414 {
 415         omap_set_dma_transfer_params(lch, params->data_type,
 416                                      params->elem_count, params->frame_count,
 417                                      params->sync_mode, params->trigger,
 418                                      params->src_or_dst_synch);
 419         omap_set_dma_src_params(lch, params->src_port,
 420                                 params->src_amode, params->src_start,
 421                                 params->src_ei, params->src_fi);
 422
 423         omap_set_dma_dest_params(lch, params->dst_port,
 424                                  params->dst_amode, params->dst_start,
 425                                  params->dst_ei, params->dst_fi);
 426         if (params->read_prio || params->write_prio)
 427                 omap_dma_set_prio_lch(lch, params->read_prio,
 428                                       params->write_prio);
 429 }
 430 EXPORT_SYMBOL(omap_set_dma_params);
 431
 432 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 433 {
 434         if (cpu_class_is_omap2())
 435                 return;
 436
 437         dma_write(eidx, CSEI(lch));
 438         dma_write(fidx, CSFI(lch));
 439 }
 440 EXPORT_SYMBOL(omap_set_dma_src_index);
 441
 442 void omap_set_dma_src_data_pack(int lch, int enable)
 443 {
 444         u32 l;
 445
 446         l = dma_read(CSDP(lch));
 447         l &= ~(1 << 6);
 448         if (enable)
 449                 l |= (1 << 6);
 450         dma_write(l, CSDP(lch));
 451 }
 452 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 453
 454 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 455 {
 456         unsigned int burst = 0;
 457         u32 l;
 458
 459         l = dma_read(CSDP(lch));
 460         l &= ~(0x03 << 7);
 461
 462         switch (burst_mode) {
 463         case OMAP_DMA_DATA_BURST_DIS:
 464                 break;
 465         case OMAP_DMA_DATA_BURST_4:
 466                 if (cpu_class_is_omap2())
 467                         burst = 0x1;
 468                 else
 469                         burst = 0x2;
 470                 break;
 471         case OMAP_DMA_DATA_BURST_8:
 472                 if (cpu_class_is_omap2()) {
 473                         burst = 0x2;
 474                         break;
 475                 }
 476                 /* not supported by current hardware on OMAP1
 477                  * w |= (0x03 << 7);
 478                  * fall through
 479                  */
 480         case OMAP_DMA_DATA_BURST_16:
 481                 if (cpu_class_is_omap2()) {
 482                         burst = 0x3;
 483                         break;
 484                 }
 485                 /* OMAP1 don't support burst 16
 486                  * fall through
 487                  */
 488         default:
 489                 BUG();
 490         }
 491
 492         l |= (burst << 7);
 493         dma_write(l, CSDP(lch));
 494 }
 495 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 496
 497 /* Note that dest_port is only for OMAP1 */
 498 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 499                               unsigned long dest_start,
 500                               int dst_ei, int dst_fi)
 501 {
 502         u32 l;
 503
 504         if (cpu_class_is_omap1()) {
 505                 l = dma_read(CSDP(lch));
 506                 l &= ~(0x1f << 9);
 507                 l |= dest_port << 9;
 508                 dma_write(l, CSDP(lch));
 509         }
 510
 511         l = dma_read(CCR(lch));
 512         l &= ~(0x03 << 14);
 513         l |= dest_amode << 14;
 514         dma_write(l, CCR(lch));
 515
 516         if (cpu_class_is_omap1()) {
 517                 dma_write(dest_start >> 16, CDSA_U(lch));
 518                 dma_write(dest_start, CDSA_L(lch));
 519         }
 520
 521         if (cpu_class_is_omap2())
 522                 dma_write(dest_start, CDSA(lch));
 523
 524         dma_write(dst_ei, CDEI(lch));
 525         dma_write(dst_fi, CDFI(lch));
 526 }
 527 EXPORT_SYMBOL(omap_set_dma_dest_params);
 528
 529 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 530 {
 531         if (cpu_class_is_omap2())
 532                 return;
 533
 534         dma_write(eidx, CDEI(lch));
 535         dma_write(fidx, CDFI(lch));
 536 }
 537 EXPORT_SYMBOL(omap_set_dma_dest_index);
 538
 539 void omap_set_dma_dest_data_pack(int lch, int enable)
 540 {
 541         u32 l;
 542
 543         l = dma_read(CSDP(lch));
 544         l &= ~(1 << 13);
 545         if (enable)
 546                 l |= 1 << 13;
 547         dma_write(l, CSDP(lch));
 548 }
 549 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 550
 551 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 552 {
 553         unsigned int burst = 0;
 554         u32 l;
 555
 556         l = dma_read(CSDP(lch));
 557         l &= ~(0x03 << 14);
 558
 559         switch (burst_mode) {
 560         case OMAP_DMA_DATA_BURST_DIS:
 561                 break;
 562         case OMAP_DMA_DATA_BURST_4:
 563                 if (cpu_class_is_omap2())
 564                         burst = 0x1;
 565                 else
 566                         burst = 0x2;
 567                 break;
 568         case OMAP_DMA_DATA_BURST_8:
 569                 if (cpu_class_is_omap2())
 570                         burst = 0x2;
 571                 else
 572                         burst = 0x3;
 573                 break;
 574         case OMAP_DMA_DATA_BURST_16:
 575                 if (cpu_class_is_omap2()) {
 576                         burst = 0x3;
 577                         break;
 578                 }
 579                 /* OMAP1 don't support burst 16
 580                  * fall through
 581                  */
 582         default:
 583                 printk(KERN_ERR "Invalid DMA burst mode\n");
 584                 BUG();
 585                 return;
 586         }
 587         l |= (burst << 14);
 588         dma_write(l, CSDP(lch));
 589 }
 590 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 591
 592 static inline void omap_enable_channel_irq(int lch)
 593 {
 594         u32 status;
 595
 596         /* Clear CSR */
 597         if (cpu_class_is_omap1())
 598                 status = dma_read(CSR(lch));
 599         else if (cpu_class_is_omap2())
 600                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 601
 602         /* Enable some nice interrupts. */
 603         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 604 }
 605
 606 static void omap_disable_channel_irq(int lch)
 607 {
 608         if (cpu_class_is_omap2())
 609                 dma_write(0, CICR(lch));
 610 }
 611
 612 void omap_enable_dma_irq(int lch, u16 bits)
 613 {
 614         dma_chan[lch].enabled_irqs |= bits;
 615 }
 616 EXPORT_SYMBOL(omap_enable_dma_irq);
 617
 618 void omap_disable_dma_irq(int lch, u16 bits)
 619 {
 620         dma_chan[lch].enabled_irqs &= ~bits;
 621 }
 622 EXPORT_SYMBOL(omap_disable_dma_irq);
 623
 624 static inline void enable_lnk(int lch)
 625 {
 626         u32 l;
 627
 628         l = dma_read(CLNK_CTRL(lch));
 629
 630         if (cpu_class_is_omap1())
 631                 l &= ~(1 << 14);
 632
 633         /* Set the ENABLE_LNK bits */
 634         if (dma_chan[lch].next_lch != -1)
 635                 l = dma_chan[lch].next_lch | (1 << 15);
 636
 637 #ifndef CONFIG_ARCH_OMAP1
 638         if (cpu_class_is_omap2())
 639                 if (dma_chan[lch].next_linked_ch != -1)
 640                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 641 #endif
 642
 643         dma_write(l, CLNK_CTRL(lch));
 644 }
 645
 646 static inline void disable_lnk(int lch)
 647 {
 648         u32 l;
 649
 650         l = dma_read(CLNK_CTRL(lch));
 651
 652         /* Disable interrupts */
 653         if (cpu_class_is_omap1()) {
 654                 dma_write(0, CICR(lch));
 655                 /* Set the STOP_LNK bit */
 656                 l |= 1 << 14;
 657         }
 658
 659         if (cpu_class_is_omap2()) {
 660                 omap_disable_channel_irq(lch);
 661                 /* Clear the ENABLE_LNK bit */
 662                 l &= ~(1 << 15);
 663         }
 664
 665         dma_write(l, CLNK_CTRL(lch));
 666         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 667 }
 668
 669 static inline void omap2_enable_irq_lch(int lch)
 670 {
 671         u32 val;
 672
 673         if (!cpu_class_is_omap2())
 674                 return;
 675
 676         val = dma_read(IRQENABLE_L0);
 677         val |= 1 << lch;
 678         dma_write(val, IRQENABLE_L0);
 679 }
 680
 681 int omap_request_dma(int dev_id, const char *dev_name,
 682                      void (*callback)(int lch, u16 ch_status, void *data),
 683                      void *data, int *dma_ch_out)
 684 {
 685         int ch, free_ch = -1;
 686         unsigned long flags;
 687         struct omap_dma_lch *chan;
 688
 689         spin_lock_irqsave(&dma_chan_lock, flags);
 690         for (ch = 0; ch < dma_chan_count; ch++) {
 691                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 692                         free_ch = ch;
 693                         if (dev_id == 0)
 694                                 break;
 695                 }
 696         }
 697         if (free_ch == -1) {
 698                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 699                 return -EBUSY;
 700         }
 701         chan = dma_chan + free_ch;
 702         chan->dev_id = dev_id;
 703
 704         if (cpu_class_is_omap1())
 705                 clear_lch_regs(free_ch);
 706
 707         if (cpu_class_is_omap2())
 708                 omap_clear_dma(free_ch);
 709
 710         spin_unlock_irqrestore(&dma_chan_lock, flags);
 711
 712         chan->dev_name = dev_name;
 713         chan->callback = callback;
 714         chan->data = data;
 715         chan->flags = 0;
 716
 717 #ifndef CONFIG_ARCH_OMAP1
 718         if (cpu_class_is_omap2()) {
 719                 chan->chain_id = -1;
 720                 chan->next_linked_ch = -1;
 721         }
 722 #endif
 723
 724         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 725
 726         if (cpu_class_is_omap1())
 727                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 728         else if (cpu_class_is_omap2())
 729                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 730                         OMAP2_DMA_TRANS_ERR_IRQ;
 731
 732         if (cpu_is_omap16xx()) {
 733                 /* If the sync device is set, configure it dynamically. */
 734                 if (dev_id != 0) {
 735                         set_gdma_dev(free_ch + 1, dev_id);
 736                         dev_id = free_ch + 1;
 737                 }
 738                 /*
 739                  * Disable the 1510 compatibility mode and set the sync device
 740                  * id.
 741                  */
 742                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 743         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 744                 dma_write(dev_id, CCR(free_ch));
 745         }
 746
 747         if (cpu_class_is_omap2()) {
 748                 omap2_enable_irq_lch(free_ch);
 749                 omap_enable_channel_irq(free_ch);
 750                 /* Clear the CSR register and IRQ status register */
 751                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 752                 dma_write(1 << free_ch, IRQSTATUS_L0);
 753         }
 754
 755         *dma_ch_out = free_ch;
 756
 757         return 0;
 758 }
 759 EXPORT_SYMBOL(omap_request_dma);
 760
 761 void omap_free_dma(int lch)
 762 {
 763         unsigned long flags;
 764
 765         spin_lock_irqsave(&dma_chan_lock, flags);
 766         if (dma_chan[lch].dev_id == -1) {
 767                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 768                        lch);
 769                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 770                 return;
 771         }
 772
 773         dma_chan[lch].dev_id = -1;
 774         dma_chan[lch].next_lch = -1;
 775         dma_chan[lch].callback = NULL;
 776         spin_unlock_irqrestore(&dma_chan_lock, flags);
 777
 778         if (cpu_class_is_omap1()) {
 779                 /* Disable all DMA interrupts for the channel. */
 780                 dma_write(0, CICR(lch));
 781                 /* Make sure the DMA transfer is stopped. */
 782                 dma_write(0, CCR(lch));
 783         }
 784
 785         if (cpu_class_is_omap2()) {
 786                 u32 val;
 787                 /* Disable interrupts */
 788                 val = dma_read(IRQENABLE_L0);
 789                 val &= ~(1 << lch);
 790                 dma_write(val, IRQENABLE_L0);
 791
 792                 /* Clear the CSR register and IRQ status register */
 793                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 794                 dma_write(1 << lch, IRQSTATUS_L0);
 795
 796                 /* Disable all DMA interrupts for the channel. */
 797                 dma_write(0, CICR(lch));
 798
 799                 /* Make sure the DMA transfer is stopped. */
 800                 dma_write(0, CCR(lch));
 801                 omap_clear_dma(lch);
 802         }
 803 }
 804 EXPORT_SYMBOL(omap_free_dma);
 805
 806 /**
 807  * @brief omap_dma_set_global_params : Set global priority settings for dma
 808  *
 809  * @param arb_rate
 810  * @param max_fifo_depth
 811  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 812  *                                                  DMA_THREAD_RESERVE_ONET
 813  *                                                  DMA_THREAD_RESERVE_TWOT
 814  *                                                  DMA_THREAD_RESERVE_THREET
 815  */
 816 void
 817 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 818 {
 819         u32 reg;
 820
 821         if (!cpu_class_is_omap2()) {
 822                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 823                 return;
 824         }
 825
 826         if (arb_rate == 0)
 827                 arb_rate = 1;
 828
 829         reg = (arb_rate & 0xff) << 16;
 830         reg |= (0xff & max_fifo_depth);
 831
 832         dma_write(reg, GCR);
 833 }
 834 EXPORT_SYMBOL(omap_dma_set_global_params);
 835
 836 /**
 837  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 838  *
 839  * @param lch
 840  * @param read_prio - Read priority
 841  * @param write_prio - Write priority
 842  * Both of the above can be set with one of the following values :
 843  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 844  */
 845 int
 846 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 847                       unsigned char write_prio)
 848 {
 849         u32 l;
 850
 851         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 852                 printk(KERN_ERR "Invalid channel id\n");
 853                 return -EINVAL;
 854         }
 855         l = dma_read(CCR(lch));
 856         l &= ~((1 << 6) | (1 << 26));
 857         if (cpu_is_omap2430() || cpu_is_omap34xx())
 858                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 859         else
 860                 l |= ((read_prio & 0x1) << 6);
 861
 862         dma_write(l, CCR(lch));
 863
 864         return 0;
 865 }
 866 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 867
 868 /*
 869  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 870  * through omap_start_dma(). Any buffers in flight are discarded.
 871  */
 872 void omap_clear_dma(int lch)
 873 {
 874         unsigned long flags;
 875
 876         local_irq_save(flags);
 877
 878         if (cpu_class_is_omap1()) {
 879                 u32 l;
 880
 881                 l = dma_read(CCR(lch));
 882                 l &= ~OMAP_DMA_CCR_EN;
 883                 dma_write(l, CCR(lch));
 884
 885                 /* Clear pending interrupts */
 886                 l = dma_read(CSR(lch));
 887         }
 888
 889         if (cpu_class_is_omap2()) {
 890                 int i;
 891                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 892                 for (i = 0; i < 0x44; i += 4)
 893                         __raw_writel(0, lch_base + i);
 894         }
 895
 896         local_irq_restore(flags);
 897 }
 898 EXPORT_SYMBOL(omap_clear_dma);
 899
 900 void omap_start_dma(int lch)
 901 {
 902         u32 l;
 903
 904         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 905                 int next_lch, cur_lch;
 906                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 907
 908                 dma_chan_link_map[lch] = 1;
 909                 /* Set the link register of the first channel */
 910                 enable_lnk(lch);
 911
 912                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 913                 cur_lch = dma_chan[lch].next_lch;
 914                 do {
 915                         next_lch = dma_chan[cur_lch].next_lch;
 916
 917                         /* The loop case: we've been here already */
 918                         if (dma_chan_link_map[cur_lch])
 919                                 break;
 920                         /* Mark the current channel */
 921                         dma_chan_link_map[cur_lch] = 1;
 922
 923                         enable_lnk(cur_lch);
 924                         omap_enable_channel_irq(cur_lch);
 925
 926                         cur_lch = next_lch;
 927                 } while (next_lch != -1);
 928         } else if (cpu_class_is_omap2()) {
 929                 /* Errata: Need to write lch even if not using chaining */
 930                 dma_write(lch, CLNK_CTRL(lch));
 931         }
 932
 933         omap_enable_channel_irq(lch);
 934
 935         l = dma_read(CCR(lch));
 936
 937         /*
 938          * Errata: On ES2.0 BUFFERING disable must be set.
 939          * This will always fail on ES1.0
 940          */
 941         if (cpu_is_omap24xx())
 942                 l |= OMAP_DMA_CCR_EN;
 943
 944         l |= OMAP_DMA_CCR_EN;
 945         dma_write(l, CCR(lch));
 946
 947         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 948 }
 949 EXPORT_SYMBOL(omap_start_dma);
 950
 951 void omap_stop_dma(int lch)
 952 {
 953         u32 l;
 954
 955         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 956                 int next_lch, cur_lch = lch;
 957                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 958
 959                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 960                 do {
 961                         /* The loop case: we've been here already */
 962                         if (dma_chan_link_map[cur_lch])
 963                                 break;
 964                         /* Mark the current channel */
 965                         dma_chan_link_map[cur_lch] = 1;
 966
 967                         disable_lnk(cur_lch);
 968
 969                         next_lch = dma_chan[cur_lch].next_lch;
 970                         cur_lch = next_lch;
 971                 } while (next_lch != -1);
 972
 973                 return;
 974         }
 975
 976         /* Disable all interrupts on the channel */
 977         if (cpu_class_is_omap1())
 978                 dma_write(0, CICR(lch));
 979
 980         l = dma_read(CCR(lch));
 981         l &= ~OMAP_DMA_CCR_EN;
 982         dma_write(l, CCR(lch));
 983
 984         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 985 }
 986 EXPORT_SYMBOL(omap_stop_dma);
 987
 988 /*
 989  * Allows changing the DMA callback function or data. This may be needed if
 990  * the driver shares a single DMA channel for multiple dma triggers.
 991  */
 992 int omap_set_dma_callback(int lch,
 993                           void (*callback)(int lch, u16 ch_status, void *data),
 994                           void *data)
 995 {
 996         unsigned long flags;
 997
 998         if (lch < 0)
 999                 return -ENODEV;
1000
1001         spin_lock_irqsave(&dma_chan_lock, flags);
1002         if (dma_chan[lch].dev_id == -1) {
1003                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1004                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1005                 return -EINVAL;
1006         }
1007         dma_chan[lch].callback = callback;
1008         dma_chan[lch].data = data;
1009         spin_unlock_irqrestore(&dma_chan_lock, flags);
1010
1011         return 0;
1012 }
1013 EXPORT_SYMBOL(omap_set_dma_callback);
1014
1015 /*
1016  * Returns current physical source address for the given DMA channel.
1017  * If the channel is running the caller must disable interrupts prior calling
1018  * this function and process the returned value before re-enabling interrupt to
1019  * prevent races with the interrupt handler. Note that in continuous mode there
1020  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1021  * in incorrect return value.
1022  */
1023 dma_addr_t omap_get_dma_src_pos(int lch)
1024 {
1025         dma_addr_t offset = 0;
1026
1027         if (cpu_is_omap15xx())
1028                 offset = dma_read(CPC(lch));
1029         else
1030                 offset = dma_read(CSAC(lch));
1031
1032         /*
1033          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1034          * read before the DMA controller finished disabling the channel.
1035          */
1036         if (!cpu_is_omap15xx() && offset == 0)
1037                 offset = dma_read(CSAC(lch));
1038
1039         if (cpu_class_is_omap1())
1040                 offset |= (dma_read(CSSA_U(lch)) << 16);
1041
1042         return offset;
1043 }
1044 EXPORT_SYMBOL(omap_get_dma_src_pos);
1045
1046 /*
1047  * Returns current physical destination address for the given DMA channel.
1048  * If the channel is running the caller must disable interrupts prior calling
1049  * this function and process the returned value before re-enabling interrupt to
1050  * prevent races with the interrupt handler. Note that in continuous mode there
1051  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1052  * in incorrect return value.
1053  */
1054 dma_addr_t omap_get_dma_dst_pos(int lch)
1055 {
1056         dma_addr_t offset = 0;
1057
1058         if (cpu_is_omap15xx())
1059                 offset = dma_read(CPC(lch));
1060         else
1061                 offset = dma_read(CDAC(lch));
1062
1063         /*
1064          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1065          * read before the DMA controller finished disabling the channel.
1066          */
1067         if (!cpu_is_omap15xx() && offset == 0)
1068                 offset = dma_read(CDAC(lch));
1069
1070         if (cpu_class_is_omap1())
1071                 offset |= (dma_read(CDSA_U(lch)) << 16);
1072
1073         return offset;
1074 }
1075 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1076
1077 int omap_get_dma_active_status(int lch)
1078 {
1079         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1080 }
1081 EXPORT_SYMBOL(omap_get_dma_active_status);
1082
1083 int omap_dma_running(void)
1084 {
1085         int lch;
1086
1087         /* Check if LCD DMA is running */
1088         if (cpu_is_omap16xx())
1089                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1090                         return 1;
1091
1092         for (lch = 0; lch < dma_chan_count; lch++)
1093                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1094                         return 1;
1095
1096         return 0;
1097 }
1098
1099 /*
1100  * lch_queue DMA will start right after lch_head one is finished.
1101  * For this DMA link to start, you still need to start (see omap_start_dma)
1102  * the first one. That will fire up the entire queue.
1103  */
1104 void omap_dma_link_lch(int lch_head, int lch_queue)
1105 {
1106         if (omap_dma_in_1510_mode()) {
1107                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1108                 BUG();
1109                 return;
1110         }
1111
1112         if ((dma_chan[lch_head].dev_id == -1) ||
1113             (dma_chan[lch_queue].dev_id == -1)) {
1114                 printk(KERN_ERR "omap_dma: trying to link "
1115                        "non requested channels\n");
1116                 dump_stack();
1117         }
1118
1119         dma_chan[lch_head].next_lch = lch_queue;
1120 }
1121 EXPORT_SYMBOL(omap_dma_link_lch);
1122
1123 /*
1124  * Once the DMA queue is stopped, we can destroy it.
1125  */
1126 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1127 {
1128         if (omap_dma_in_1510_mode()) {
1129                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1130                 BUG();
1131                 return;
1132         }
1133
1134         if (dma_chan[lch_head].next_lch != lch_queue ||
1135             dma_chan[lch_head].next_lch == -1) {
1136                 printk(KERN_ERR "omap_dma: trying to unlink "
1137                        "non linked channels\n");
1138                 dump_stack();
1139         }
1140
1141         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1142             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1143                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1144                        "before unlinking\n");
1145                 dump_stack();
1146         }
1147
1148         dma_chan[lch_head].next_lch = -1;
1149 }
1150 EXPORT_SYMBOL(omap_dma_unlink_lch);
1151
1152 /*----------------------------------------------------------------------------*/
1153
1154 #ifndef CONFIG_ARCH_OMAP1
1155 /* Create chain of DMA channesls */
1156 static void create_dma_lch_chain(int lch_head, int lch_queue)
1157 {
1158         u32 l;
1159
1160         /* Check if this is the first link in chain */
1161         if (dma_chan[lch_head].next_linked_ch == -1) {
1162                 dma_chan[lch_head].next_linked_ch = lch_queue;
1163                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1164                 dma_chan[lch_queue].next_linked_ch = lch_head;
1165                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1166         }
1167
1168         /* a link exists, link the new channel in circular chain */
1169         else {
1170                 dma_chan[lch_queue].next_linked_ch =
1171                                         dma_chan[lch_head].next_linked_ch;
1172                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1173                 dma_chan[lch_head].next_linked_ch = lch_queue;
1174                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1175                                         lch_queue;
1176         }
1177
1178         l = dma_read(CLNK_CTRL(lch_head));
1179         l &= ~(0x1f);
1180         l |= lch_queue;
1181         dma_write(l, CLNK_CTRL(lch_head));
1182
1183         l = dma_read(CLNK_CTRL(lch_queue));
1184         l &= ~(0x1f);
1185         l |= (dma_chan[lch_queue].next_linked_ch);
1186         dma_write(l, CLNK_CTRL(lch_queue));
1187 }
1188
1189 /**
1190  * @brief omap_request_dma_chain : Request a chain of DMA channels
1191  *
1192  * @param dev_id - Device id using the dma channel
1193  * @param dev_name - Device name
1194  * @param callback - Call back function
1195  * @chain_id -
1196  * @no_of_chans - Number of channels requested
1197  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1198  *                                            OMAP_DMA_DYNAMIC_CHAIN
1199  * @params - Channel parameters
1200  *
1201  * @return - Succes : 0
1202  *           Failure: -EINVAL/-ENOMEM
1203  */
1204 int omap_request_dma_chain(int dev_id, const char *dev_name,
1205                            void (*callback) (int chain_id, u16 ch_status,
1206                                              void *data),
1207                            int *chain_id, int no_of_chans, int chain_mode,
1208                            struct omap_dma_channel_params params)
1209 {
1210         int *channels;
1211         int i, err;
1212
1213         /* Is the chain mode valid ? */
1214         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1215                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1216                 printk(KERN_ERR "Invalid chain mode requested\n");
1217                 return -EINVAL;
1218         }
1219
1220         if (unlikely((no_of_chans < 1
1221                         || no_of_chans > dma_lch_count))) {
1222                 printk(KERN_ERR "Invalid Number of channels requested\n");
1223                 return -EINVAL;
1224         }
1225
1226         /* Allocate a queue to maintain the status of the channels
1227          * in the chain */
1228         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1229         if (channels == NULL) {
1230                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1231                 return -ENOMEM;
1232         }
1233
1234         /* request and reserve DMA channels for the chain */
1235         for (i = 0; i < no_of_chans; i++) {
1236                 err = omap_request_dma(dev_id, dev_name,
1237                                         callback, NULL, &channels[i]);
1238                 if (err < 0) {
1239                         int j;
1240                         for (j = 0; j < i; j++)
1241                                 omap_free_dma(channels[j]);
1242                         kfree(channels);
1243                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1244                         return err;
1245                 }
1246                 dma_chan[channels[i]].prev_linked_ch = -1;
1247                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1248
1249                 /*
1250                  * Allowing client drivers to set common parameters now,
1251                  * so that later only relevant (src_start, dest_start
1252                  * and element count) can be set
1253                  */
1254                 omap_set_dma_params(channels[i], &params);
1255         }
1256
1257         *chain_id = channels[0];
1258         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1259         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1260         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1261         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1262
1263         for (i = 0; i < no_of_chans; i++)
1264                 dma_chan[channels[i]].chain_id = *chain_id;
1265
1266         /* Reset the Queue pointers */
1267         OMAP_DMA_CHAIN_QINIT(*chain_id);
1268
1269         /* Set up the chain */
1270         if (no_of_chans == 1)
1271                 create_dma_lch_chain(channels[0], channels[0]);
1272         else {
1273                 for (i = 0; i < (no_of_chans - 1); i++)
1274                         create_dma_lch_chain(channels[i], channels[i + 1]);
1275         }
1276
1277         return 0;
1278 }
1279 EXPORT_SYMBOL(omap_request_dma_chain);
1280
1281 /**
1282  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1283  * params after setting it. Dont do this while dma is running!!
1284  *
1285  * @param chain_id - Chained logical channel id.
1286  * @param params
1287  *
1288  * @return - Success : 0
1289  *           Failure : -EINVAL
1290  */
1291 int omap_modify_dma_chain_params(int chain_id,
1292                                 struct omap_dma_channel_params params)
1293 {
1294         int *channels;
1295         u32 i;
1296
1297         /* Check for input params */
1298         if (unlikely((chain_id < 0
1299                         || chain_id >= dma_lch_count))) {
1300                 printk(KERN_ERR "Invalid chain id\n");
1301                 return -EINVAL;
1302         }
1303
1304         /* Check if the chain exists */
1305         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1306                 printk(KERN_ERR "Chain doesn't exists\n");
1307                 return -EINVAL;
1308         }
1309         channels = dma_linked_lch[chain_id].linked_dmach_q;
1310
1311         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1312                 /*
1313                  * Allowing client drivers to set common parameters now,
1314                  * so that later only relevant (src_start, dest_start
1315                  * and element count) can be set
1316                  */
1317                 omap_set_dma_params(channels[i], &params);
1318         }
1319
1320         return 0;
1321 }
1322 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1323
1324 /**
1325  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1326  *
1327  * @param chain_id
1328  *
1329  * @return - Success : 0
1330  *           Failure : -EINVAL
1331  */
1332 int omap_free_dma_chain(int chain_id)
1333 {
1334         int *channels;
1335         u32 i;
1336
1337         /* Check for input params */
1338         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1339                 printk(KERN_ERR "Invalid chain id\n");
1340                 return -EINVAL;
1341         }
1342
1343         /* Check if the chain exists */
1344         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1345                 printk(KERN_ERR "Chain doesn't exists\n");
1346                 return -EINVAL;
1347         }
1348
1349         channels = dma_linked_lch[chain_id].linked_dmach_q;
1350         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1351                 dma_chan[channels[i]].next_linked_ch = -1;
1352                 dma_chan[channels[i]].prev_linked_ch = -1;
1353                 dma_chan[channels[i]].chain_id = -1;
1354                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1355                 omap_free_dma(channels[i]);
1356         }
1357
1358         kfree(channels);
1359
1360         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1361         dma_linked_lch[chain_id].chain_mode = -1;
1362         dma_linked_lch[chain_id].chain_state = -1;
1363
1364         return (0);
1365 }
1366 EXPORT_SYMBOL(omap_free_dma_chain);
1367
1368 /**
1369  * @brief omap_dma_chain_status - Check if the chain is in
1370  * active / inactive state.
1371  * @param chain_id
1372  *
1373  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1374  *           Failure : -EINVAL
1375  */
1376 int omap_dma_chain_status(int chain_id)
1377 {
1378         /* Check for input params */
1379         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1380                 printk(KERN_ERR "Invalid chain id\n");
1381                 return -EINVAL;
1382         }
1383
1384         /* Check if the chain exists */
1385         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1386                 printk(KERN_ERR "Chain doesn't exists\n");
1387                 return -EINVAL;
1388         }
1389         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1390                         dma_linked_lch[chain_id].q_count);
1391
1392         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1393                 return OMAP_DMA_CHAIN_INACTIVE;
1394
1395         return OMAP_DMA_CHAIN_ACTIVE;
1396 }
1397 EXPORT_SYMBOL(omap_dma_chain_status);
1398
1399 /**
1400  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1401  * set the params and start the transfer.
1402  *
1403  * @param chain_id
1404  * @param src_start - buffer start address
1405  * @param dest_start - Dest address
1406  * @param elem_count
1407  * @param frame_count
1408  * @param callbk_data - channel callback parameter data.
1409  *
1410  * @return  - Success : 0
1411  *            Failure: -EINVAL/-EBUSY
1412  */
1413 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1414                         int elem_count, int frame_count, void *callbk_data)
1415 {
1416         int *channels;
1417         u32 l, lch;
1418         int start_dma = 0;
1419
1420         /*
1421          * if buffer size is less than 1 then there is
1422          * no use of starting the chain
1423          */
1424         if (elem_count < 1) {
1425                 printk(KERN_ERR "Invalid buffer size\n");
1426                 return -EINVAL;
1427         }
1428
1429         /* Check for input params */
1430         if (unlikely((chain_id < 0
1431                         || chain_id >= dma_lch_count))) {
1432                 printk(KERN_ERR "Invalid chain id\n");
1433                 return -EINVAL;
1434         }
1435
1436         /* Check if the chain exists */
1437         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1438                 printk(KERN_ERR "Chain doesn't exist\n");
1439                 return -EINVAL;
1440         }
1441
1442         /* Check if all the channels in chain are in use */
1443         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1444                 return -EBUSY;
1445
1446         /* Frame count may be negative in case of indexed transfers */
1447         channels = dma_linked_lch[chain_id].linked_dmach_q;
1448
1449         /* Get a free channel */
1450         lch = channels[dma_linked_lch[chain_id].q_tail];
1451
1452         /* Store the callback data */
1453         dma_chan[lch].data = callbk_data;
1454
1455         /* Increment the q_tail */
1456         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1457
1458         /* Set the params to the free channel */
1459         if (src_start != 0)
1460                 dma_write(src_start, CSSA(lch));
1461         if (dest_start != 0)
1462                 dma_write(dest_start, CDSA(lch));
1463
1464         /* Write the buffer size */
1465         dma_write(elem_count, CEN(lch));
1466         dma_write(frame_count, CFN(lch));
1467
1468         /*
1469          * If the chain is dynamically linked,
1470          * then we may have to start the chain if its not active
1471          */
1472         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1473
1474                 /*
1475                  * In Dynamic chain, if the chain is not started,
1476                  * queue the channel
1477                  */
1478                 if (dma_linked_lch[chain_id].chain_state ==
1479                                                 DMA_CHAIN_NOTSTARTED) {
1480                         /* Enable the link in previous channel */
1481                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1482                                                                 DMA_CH_QUEUED)
1483                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1484                         dma_chan[lch].state = DMA_CH_QUEUED;
1485                 }
1486
1487                 /*
1488                  * Chain is already started, make sure its active,
1489                  * if not then start the chain
1490                  */
1491                 else {
1492                         start_dma = 1;
1493
1494                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1495                                                         DMA_CH_STARTED) {
1496                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1497                                 dma_chan[lch].state = DMA_CH_QUEUED;
1498                                 start_dma = 0;
1499                                 if (0 == ((1 << 7) & dma_read(
1500                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1501                                         disable_lnk(dma_chan[lch].
1502                                                     prev_linked_ch);
1503                                         pr_debug("\n prev ch is stopped\n");
1504                                         start_dma = 1;
1505                                 }
1506                         }
1507
1508                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1509                                                         == DMA_CH_QUEUED) {
1510                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1511                                 dma_chan[lch].state = DMA_CH_QUEUED;
1512                                 start_dma = 0;
1513                         }
1514                         omap_enable_channel_irq(lch);
1515
1516                         l = dma_read(CCR(lch));
1517
1518                         if ((0 == (l & (1 << 24))))
1519                                 l &= ~(1 << 25);
1520                         else
1521                                 l |= (1 << 25);
1522                         if (start_dma == 1) {
1523                                 if (0 == (l & (1 << 7))) {
1524                                         l |= (1 << 7);
1525                                         dma_chan[lch].state = DMA_CH_STARTED;
1526                                         pr_debug("starting %d\n", lch);
1527                                         dma_write(l, CCR(lch));
1528                                 } else
1529                                         start_dma = 0;
1530                         } else {
1531                                 if (0 == (l & (1 << 7)))
1532                                         dma_write(l, CCR(lch));
1533                         }
1534                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1535                 }
1536         }
1537
1538         return 0;
1539 }
1540 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1541
1542 /**
1543  * @brief omap_start_dma_chain_transfers - Start the chain
1544  *
1545  * @param chain_id
1546  *
1547  * @return - Success : 0
1548  *           Failure : -EINVAL/-EBUSY
1549  */
1550 int omap_start_dma_chain_transfers(int chain_id)
1551 {
1552         int *channels;
1553         u32 l, i;
1554
1555         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1556                 printk(KERN_ERR "Invalid chain id\n");
1557                 return -EINVAL;
1558         }
1559
1560         channels = dma_linked_lch[chain_id].linked_dmach_q;
1561
1562         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1563                 printk(KERN_ERR "Chain is already started\n");
1564                 return -EBUSY;
1565         }
1566
1567         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1568                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1569                                                                         i++) {
1570                         enable_lnk(channels[i]);
1571                         omap_enable_channel_irq(channels[i]);
1572                 }
1573         } else {
1574                 omap_enable_channel_irq(channels[0]);
1575         }
1576
1577         l = dma_read(CCR(channels[0]));
1578         l |= (1 << 7);
1579         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1580         dma_chan[channels[0]].state = DMA_CH_STARTED;
1581
1582         if ((0 == (l & (1 << 24))))
1583                 l &= ~(1 << 25);
1584         else
1585                 l |= (1 << 25);
1586         dma_write(l, CCR(channels[0]));
1587
1588         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1589
1590         return 0;
1591 }
1592 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1593
1594 /**
1595  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1596  *
1597  * @param chain_id
1598  *
1599  * @return - Success : 0
1600  *           Failure : EINVAL
1601  */
1602 int omap_stop_dma_chain_transfers(int chain_id)
1603 {
1604         int *channels;
1605         u32 l, i;
1606         u32 sys_cf;
1607
1608         /* Check for input params */
1609         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1610                 printk(KERN_ERR "Invalid chain id\n");
1611                 return -EINVAL;
1612         }
1613
1614         /* Check if the chain exists */
1615         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1616                 printk(KERN_ERR "Chain doesn't exists\n");
1617                 return -EINVAL;
1618         }
1619         channels = dma_linked_lch[chain_id].linked_dmach_q;
1620
1621         /*
1622          * DMA Errata:
1623          * Special programming model needed to disable DMA before end of block
1624          */
1625         sys_cf = dma_read(OCP_SYSCONFIG);
1626         l = sys_cf;
1627         /* Middle mode reg set no Standby */
1628         l &= ~((1 << 12)|(1 << 13));
1629         dma_write(l, OCP_SYSCONFIG);
1630
1631         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1632
1633                 /* Stop the Channel transmission */
1634                 l = dma_read(CCR(channels[i]));
1635                 l &= ~(1 << 7);
1636                 dma_write(l, CCR(channels[i]));
1637
1638                 /* Disable the link in all the channels */
1639                 disable_lnk(channels[i]);
1640                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1641
1642         }
1643         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1644
1645         /* Reset the Queue pointers */
1646         OMAP_DMA_CHAIN_QINIT(chain_id);
1647
1648         /* Errata - put in the old value */
1649         dma_write(sys_cf, OCP_SYSCONFIG);
1650
1651         return 0;
1652 }
1653 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1654
1655 /* Get the index of the ongoing DMA in chain */
1656 /**
1657  * @brief omap_get_dma_chain_index - Get the element and frame index
1658  * of the ongoing DMA in chain
1659  *
1660  * @param chain_id
1661  * @param ei - Element index
1662  * @param fi - Frame index
1663  *
1664  * @return - Success : 0
1665  *           Failure : -EINVAL
1666  */
1667 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1668 {
1669         int lch;
1670         int *channels;
1671
1672         /* Check for input params */
1673         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1674                 printk(KERN_ERR "Invalid chain id\n");
1675                 return -EINVAL;
1676         }
1677
1678         /* Check if the chain exists */
1679         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1680                 printk(KERN_ERR "Chain doesn't exists\n");
1681                 return -EINVAL;
1682         }
1683         if ((!ei) || (!fi))
1684                 return -EINVAL;
1685
1686         channels = dma_linked_lch[chain_id].linked_dmach_q;
1687
1688         /* Get the current channel */
1689         lch = channels[dma_linked_lch[chain_id].q_head];
1690
1691         *ei = dma_read(CCEN(lch));
1692         *fi = dma_read(CCFN(lch));
1693
1694         return 0;
1695 }
1696 EXPORT_SYMBOL(omap_get_dma_chain_index);
1697
1698 /**
1699  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1700  * ongoing DMA in chain
1701  *
1702  * @param chain_id
1703  *
1704  * @return - Success : Destination position
1705  *           Failure : -EINVAL
1706  */
1707 int omap_get_dma_chain_dst_pos(int chain_id)
1708 {
1709         int lch;
1710         int *channels;
1711
1712         /* Check for input params */
1713         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1714                 printk(KERN_ERR "Invalid chain id\n");
1715                 return -EINVAL;
1716         }
1717
1718         /* Check if the chain exists */
1719         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1720                 printk(KERN_ERR "Chain doesn't exists\n");
1721                 return -EINVAL;
1722         }
1723
1724         channels = dma_linked_lch[chain_id].linked_dmach_q;
1725
1726         /* Get the current channel */
1727         lch = channels[dma_linked_lch[chain_id].q_head];
1728
1729         return dma_read(CDAC(lch));
1730 }
1731 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1732
1733 /**
1734  * @brief omap_get_dma_chain_src_pos - Get the source position
1735  * of the ongoing DMA in chain
1736  * @param chain_id
1737  *
1738  * @return - Success : Destination position
1739  *           Failure : -EINVAL
1740  */
1741 int omap_get_dma_chain_src_pos(int chain_id)
1742 {
1743         int lch;
1744         int *channels;
1745
1746         /* Check for input params */
1747         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1748                 printk(KERN_ERR "Invalid chain id\n");
1749                 return -EINVAL;
1750         }
1751
1752         /* Check if the chain exists */
1753         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1754                 printk(KERN_ERR "Chain doesn't exists\n");
1755                 return -EINVAL;
1756         }
1757
1758         channels = dma_linked_lch[chain_id].linked_dmach_q;
1759
1760         /* Get the current channel */
1761         lch = channels[dma_linked_lch[chain_id].q_head];
1762
1763         return dma_read(CSAC(lch));
1764 }
1765 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1766 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1767
1768 /*----------------------------------------------------------------------------*/
1769
1770 #ifdef CONFIG_ARCH_OMAP1
1771
1772 static int omap1_dma_handle_ch(int ch)
1773 {
1774         u32 csr;
1775
1776         if (enable_1510_mode && ch >= 6) {
1777                 csr = dma_chan[ch].saved_csr;
1778                 dma_chan[ch].saved_csr = 0;
1779         } else
1780                 csr = dma_read(CSR(ch));
1781         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1782                 dma_chan[ch + 6].saved_csr = csr >> 7;
1783                 csr &= 0x7f;
1784         }
1785         if ((csr & 0x3f) == 0)
1786                 return 0;
1787         if (unlikely(dma_chan[ch].dev_id == -1)) {
1788                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1789                        "%d (CSR %04x)\n", ch, csr);
1790                 return 0;
1791         }
1792         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1793                 printk(KERN_WARNING "DMA timeout with device %d\n",
1794                        dma_chan[ch].dev_id);
1795         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1796                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1797                        "with device %d\n", dma_chan[ch].dev_id);
1798         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1799                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1800         if (likely(dma_chan[ch].callback != NULL))
1801                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1802
1803         return 1;
1804 }
1805
1806 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1807 {
1808         int ch = ((int) dev_id) - 1;
1809         int handled = 0;
1810
1811         for (;;) {
1812                 int handled_now = 0;
1813
1814                 handled_now += omap1_dma_handle_ch(ch);
1815                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1816                         handled_now += omap1_dma_handle_ch(ch + 6);
1817                 if (!handled_now)
1818                         break;
1819                 handled += handled_now;
1820         }
1821
1822         return handled ? IRQ_HANDLED : IRQ_NONE;
1823 }
1824
1825 #else
1826 #define omap1_dma_irq_handler   NULL
1827 #endif
1828
1829 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1830
1831 static int omap2_dma_handle_ch(int ch)
1832 {
1833         u32 status = dma_read(CSR(ch));
1834
1835         if (!status) {
1836                 if (printk_ratelimit())
1837                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1838                                 ch);
1839                 dma_write(1 << ch, IRQSTATUS_L0);
1840                 return 0;
1841         }
1842         if (unlikely(dma_chan[ch].dev_id == -1)) {
1843                 if (printk_ratelimit())
1844                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1845                                         "channel %d\n", status, ch);
1846                 return 0;
1847         }
1848         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1849                 printk(KERN_INFO
1850                        "DMA synchronization event drop occurred with device "
1851                        "%d\n", dma_chan[ch].dev_id);
1852         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1853                 printk(KERN_INFO "DMA transaction error with device %d\n",
1854                        dma_chan[ch].dev_id);
1855                 if (cpu_class_is_omap2()) {
1856                         /* Errata: sDMA Channel is not disabled
1857                          * after a transaction error. So we explicitely
1858                          * disable the channel
1859                          */
1860                         u32 ccr;
1861
1862                         ccr = dma_read(CCR(ch));
1863                         ccr &= ~OMAP_DMA_CCR_EN;
1864                         dma_write(ccr, CCR(ch));
1865                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1866                 }
1867         }
1868         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1869                 printk(KERN_INFO "DMA secure error with device %d\n",
1870                        dma_chan[ch].dev_id);
1871         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1872                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1873                        dma_chan[ch].dev_id);
1874
1875         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1876         dma_write(1 << ch, IRQSTATUS_L0);
1877
1878         /* If the ch is not chained then chain_id will be -1 */
1879         if (dma_chan[ch].chain_id != -1) {
1880                 int chain_id = dma_chan[ch].chain_id;
1881                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1882                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1883                         dma_chan[dma_chan[ch].next_linked_ch].state =
1884                                                         DMA_CH_STARTED;
1885                 if (dma_linked_lch[chain_id].chain_mode ==
1886                                                 OMAP_DMA_DYNAMIC_CHAIN)
1887                         disable_lnk(ch);
1888
1889                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1890                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1891
1892                 status = dma_read(CSR(ch));
1893         }
1894
1895         if (likely(dma_chan[ch].callback != NULL))
1896                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1897
1898         dma_write(status, CSR(ch));
1899
1900         return 0;
1901 }
1902
1903 /* STATUS register count is from 1-32 while our is 0-31 */
1904 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1905 {
1906         u32 val;
1907         int i;
1908
1909         val = dma_read(IRQSTATUS_L0);
1910         if (val == 0) {
1911                 if (printk_ratelimit())
1912                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1913                 return IRQ_HANDLED;
1914         }
1915         for (i = 0; i < dma_lch_count && val != 0; i++) {
1916                 if (val & 1)
1917                         omap2_dma_handle_ch(i);
1918                 val >>= 1;
1919         }
1920
1921         return IRQ_HANDLED;
1922 }
1923
1924 static struct irqaction omap24xx_dma_irq = {
1925         .name = "DMA",
1926         .handler = omap2_dma_irq_handler,
1927         .flags = IRQF_DISABLED
1928 };
1929
1930 #else
1931 static struct irqaction omap24xx_dma_irq;
1932 #endif
1933
1934 /*----------------------------------------------------------------------------*/
1935
1936 static struct lcd_dma_info {
1937         spinlock_t lock;
1938         int reserved;
1939         void (*callback)(u16 status, void *data);
1940         void *cb_data;
1941
1942         int active;
1943         unsigned long addr, size;
1944         int rotate, data_type, xres, yres;
1945         int vxres;
1946         int mirror;
1947         int xscale, yscale;
1948         int ext_ctrl;
1949         int src_port;
1950         int single_transfer;
1951 } lcd_dma;
1952
1953 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1954                          int data_type)
1955 {
1956         lcd_dma.addr = addr;
1957         lcd_dma.data_type = data_type;
1958         lcd_dma.xres = fb_xres;
1959         lcd_dma.yres = fb_yres;
1960 }
1961 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1962
1963 void omap_set_lcd_dma_src_port(int port)
1964 {
1965         lcd_dma.src_port = port;
1966 }
1967
1968 void omap_set_lcd_dma_ext_controller(int external)
1969 {
1970         lcd_dma.ext_ctrl = external;
1971 }
1972 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1973
1974 void omap_set_lcd_dma_single_transfer(int single)
1975 {
1976         lcd_dma.single_transfer = single;
1977 }
1978 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1979
1980 void omap_set_lcd_dma_b1_rotation(int rotate)
1981 {
1982         if (omap_dma_in_1510_mode()) {
1983                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1984                 BUG();
1985                 return;
1986         }
1987         lcd_dma.rotate = rotate;
1988 }
1989 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1990
1991 void omap_set_lcd_dma_b1_mirror(int mirror)
1992 {
1993         if (omap_dma_in_1510_mode()) {
1994                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1995                 BUG();
1996         }
1997         lcd_dma.mirror = mirror;
1998 }
1999 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2000
2001 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2002 {
2003         if (omap_dma_in_1510_mode()) {
2004                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2005                                 "in 1510 mode\n");
2006                 BUG();
2007         }
2008         lcd_dma.vxres = vxres;
2009 }
2010 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2011
2012 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2013 {
2014         if (omap_dma_in_1510_mode()) {
2015                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2016                 BUG();
2017         }
2018         lcd_dma.xscale = xscale;
2019         lcd_dma.yscale = yscale;
2020 }
2021 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2022
2023 static void set_b1_regs(void)
2024 {
2025         unsigned long top, bottom;
2026         int es;
2027         u16 w;
2028         unsigned long en, fn;
2029         long ei, fi;
2030         unsigned long vxres;
2031         unsigned int xscale, yscale;
2032
2033         switch (lcd_dma.data_type) {
2034         case OMAP_DMA_DATA_TYPE_S8:
2035                 es = 1;
2036                 break;
2037         case OMAP_DMA_DATA_TYPE_S16:
2038                 es = 2;
2039                 break;
2040         case OMAP_DMA_DATA_TYPE_S32:
2041                 es = 4;
2042                 break;
2043         default:
2044                 BUG();
2045                 return;
2046         }
2047
2048         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2049         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2050         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2051         BUG_ON(vxres < lcd_dma.xres);
2052
2053 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2054                 ((y) * vxres * yscale + (x) * xscale) * es)
2055 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2056
2057         switch (lcd_dma.rotate) {
2058         case 0:
2059                 if (!lcd_dma.mirror) {
2060                         top = PIXADDR(0, 0);
2061                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2062                         /* 1510 DMA requires the bottom address to be 2 more
2063                          * than the actual last memory access location. */
2064                         if (omap_dma_in_1510_mode() &&
2065                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2066                                         bottom += 2;
2067                         ei = PIXSTEP(0, 0, 1, 0);
2068                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2069                 } else {
2070                         top = PIXADDR(lcd_dma.xres - 1, 0);
2071                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2072                         ei = PIXSTEP(1, 0, 0, 0);
2073                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2074                 }
2075                 en = lcd_dma.xres;
2076                 fn = lcd_dma.yres;
2077                 break;
2078         case 90:
2079                 if (!lcd_dma.mirror) {
2080                         top = PIXADDR(0, lcd_dma.yres - 1);
2081                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2082                         ei = PIXSTEP(0, 1, 0, 0);
2083                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2084                 } else {
2085                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2086                         bottom = PIXADDR(0, 0);
2087                         ei = PIXSTEP(0, 1, 0, 0);
2088                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2089                 }
2090                 en = lcd_dma.yres;
2091                 fn = lcd_dma.xres;
2092                 break;
2093         case 180:
2094                 if (!lcd_dma.mirror) {
2095                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2096                         bottom = PIXADDR(0, 0);
2097                         ei = PIXSTEP(1, 0, 0, 0);
2098                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2099                 } else {
2100                         top = PIXADDR(0, lcd_dma.yres - 1);
2101                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2102                         ei = PIXSTEP(0, 0, 1, 0);
2103                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2104                 }
2105                 en = lcd_dma.xres;
2106                 fn = lcd_dma.yres;
2107                 break;
2108         case 270:
2109                 if (!lcd_dma.mirror) {
2110                         top = PIXADDR(lcd_dma.xres - 1, 0);
2111                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2112                         ei = PIXSTEP(0, 0, 0, 1);
2113                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2114                 } else {
2115                         top = PIXADDR(0, 0);
2116                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2117                         ei = PIXSTEP(0, 0, 0, 1);
2118                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2119                 }
2120                 en = lcd_dma.yres;
2121                 fn = lcd_dma.xres;
2122                 break;
2123         default:
2124                 BUG();
2125                 return; /* Suppress warning about uninitialized vars */
2126         }
2127
2128         if (omap_dma_in_1510_mode()) {
2129                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2130                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2131                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2132                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2133
2134                 return;
2135         }
2136
2137         /* 1610 regs */
2138         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2139         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2140         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2141         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2142
2143         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2144         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2145
2146         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2147         w &= ~0x03;
2148         w |= lcd_dma.data_type;
2149         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2150
2151         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2152         /* Always set the source port as SDRAM for now*/
2153         w &= ~(0x03 << 6);
2154         if (lcd_dma.callback != NULL)
2155                 w |= 1 << 1;            /* Block interrupt enable */
2156         else
2157                 w &= ~(1 << 1);
2158         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2159
2160         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2161               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2162                 return;
2163
2164         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2165         /* Set the double-indexed addressing mode */
2166         w |= (0x03 << 12);
2167         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2168
2169         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2170         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2171         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2172 }
2173
2174 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2175 {
2176         u16 w;
2177
2178         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2179         if (unlikely(!(w & (1 << 3)))) {
2180                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2181                 return IRQ_NONE;
2182         }
2183         /* Ack the IRQ */
2184         w |= (1 << 3);
2185         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2186         lcd_dma.active = 0;
2187         if (lcd_dma.callback != NULL)
2188                 lcd_dma.callback(w, lcd_dma.cb_data);
2189
2190         return IRQ_HANDLED;
2191 }
2192
2193 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2194                          void *data)
2195 {
2196         spin_lock_irq(&lcd_dma.lock);
2197         if (lcd_dma.reserved) {
2198                 spin_unlock_irq(&lcd_dma.lock);
2199                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2200                 BUG();
2201                 return -EBUSY;
2202         }
2203         lcd_dma.reserved = 1;
2204         spin_unlock_irq(&lcd_dma.lock);
2205         lcd_dma.callback = callback;
2206         lcd_dma.cb_data = data;
2207         lcd_dma.active = 0;
2208         lcd_dma.single_transfer = 0;
2209         lcd_dma.rotate = 0;
2210         lcd_dma.vxres = 0;
2211         lcd_dma.mirror = 0;
2212         lcd_dma.xscale = 0;
2213         lcd_dma.yscale = 0;
2214         lcd_dma.ext_ctrl = 0;
2215         lcd_dma.src_port = 0;
2216
2217         return 0;
2218 }
2219 EXPORT_SYMBOL(omap_request_lcd_dma);
2220
2221 void omap_free_lcd_dma(void)
2222 {
2223         spin_lock(&lcd_dma.lock);
2224         if (!lcd_dma.reserved) {
2225                 spin_unlock(&lcd_dma.lock);
2226                 printk(KERN_ERR "LCD DMA is not reserved\n");
2227                 BUG();
2228                 return;
2229         }
2230         if (!enable_1510_mode)
2231                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2232                             OMAP1610_DMA_LCD_CCR);
2233         lcd_dma.reserved = 0;
2234         spin_unlock(&lcd_dma.lock);
2235 }
2236 EXPORT_SYMBOL(omap_free_lcd_dma);
2237
2238 void omap_enable_lcd_dma(void)
2239 {
2240         u16 w;
2241
2242         /*
2243          * Set the Enable bit only if an external controller is
2244          * connected. Otherwise the OMAP internal controller will
2245          * start the transfer when it gets enabled.
2246          */
2247         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2248                 return;
2249
2250         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2251         w |= 1 << 8;
2252         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2253
2254         lcd_dma.active = 1;
2255
2256         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2257         w |= 1 << 7;
2258         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2259 }
2260 EXPORT_SYMBOL(omap_enable_lcd_dma);
2261
2262 void omap_setup_lcd_dma(void)
2263 {
2264         BUG_ON(lcd_dma.active);
2265         if (!enable_1510_mode) {
2266                 /* Set some reasonable defaults */
2267                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2268                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2269                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2270         }
2271         set_b1_regs();
2272         if (!enable_1510_mode) {
2273                 u16 w;
2274
2275                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2276                 /*
2277                  * If DMA was already active set the end_prog bit to have
2278                  * the programmed register set loaded into the active
2279                  * register set.
2280                  */
2281                 w |= 1 << 11;           /* End_prog */
2282                 if (!lcd_dma.single_transfer)
2283                         w |= (3 << 8);  /* Auto_init, repeat */
2284                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2285         }
2286 }
2287 EXPORT_SYMBOL(omap_setup_lcd_dma);
2288
2289 void omap_stop_lcd_dma(void)
2290 {
2291         u16 w;
2292
2293         lcd_dma.active = 0;
2294         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2295                 return;
2296
2297         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2298         w &= ~(1 << 7);
2299         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2300
2301         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2302         w &= ~(1 << 8);
2303         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2304 }
2305 EXPORT_SYMBOL(omap_stop_lcd_dma);
2306
2307 /*----------------------------------------------------------------------------*/
2308
2309 static int __init omap_init_dma(void)
2310 {
2311         int ch, r;
2312
2313         if (cpu_class_is_omap1()) {
2314                 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2315                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2316         } else if (cpu_is_omap24xx()) {
2317                 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2318                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2319         } else if (cpu_is_omap34xx()) {
2320                 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2321                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2322         } else {
2323                 pr_err("DMA init failed for unsupported omap\n");
2324                 return -ENODEV;
2325         }
2326
2327         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2328                                 GFP_KERNEL);
2329         if (!dma_chan)
2330                 return -ENOMEM;
2331
2332         if (cpu_class_is_omap2()) {
2333                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2334                                                 dma_lch_count, GFP_KERNEL);
2335                 if (!dma_linked_lch) {
2336                         kfree(dma_chan);
2337                         return -ENOMEM;
2338                 }
2339         }
2340
2341         if (cpu_is_omap15xx()) {
2342                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2343                 dma_chan_count = 9;
2344                 enable_1510_mode = 1;
2345         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2346                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2347                        dma_read(HW_ID));
2348                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2349                        (dma_read(CAPS_0_U) << 16) |
2350                        dma_read(CAPS_0_L),
2351                        (dma_read(CAPS_1_U) << 16) |
2352                        dma_read(CAPS_1_L),
2353                        dma_read(CAPS_2), dma_read(CAPS_3),
2354                        dma_read(CAPS_4));
2355                 if (!enable_1510_mode) {
2356                         u16 w;
2357
2358                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2359                         w = dma_read(GSCR);
2360                         w |= 1 << 3;
2361                         dma_write(w, GSCR);
2362                         dma_chan_count = 16;
2363                 } else
2364                         dma_chan_count = 9;
2365                 if (cpu_is_omap16xx()) {
2366                         u16 w;
2367
2368                         /* this would prevent OMAP sleep */
2369                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2370                         w &= ~(1 << 8);
2371                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2372                 }
2373         } else if (cpu_class_is_omap2()) {
2374                 u8 revision = dma_read(REVISION) & 0xff;
2375                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2376                        revision >> 4, revision & 0xf);
2377                 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2378         } else {
2379                 dma_chan_count = 0;
2380                 return 0;
2381         }
2382
2383         spin_lock_init(&lcd_dma.lock);
2384         spin_lock_init(&dma_chan_lock);
2385
2386         for (ch = 0; ch < dma_chan_count; ch++) {
2387                 omap_clear_dma(ch);
2388                 dma_chan[ch].dev_id = -1;
2389                 dma_chan[ch].next_lch = -1;
2390
2391                 if (ch >= 6 && enable_1510_mode)
2392                         continue;
2393
2394                 if (cpu_class_is_omap1()) {
2395                         /*
2396                          * request_irq() doesn't like dev_id (ie. ch) being
2397                          * zero, so we have to kludge around this.
2398                          */
2399                         r = request_irq(omap1_dma_irq[ch],
2400                                         omap1_dma_irq_handler, 0, "DMA",
2401                                         (void *) (ch + 1));
2402                         if (r != 0) {
2403                                 int i;
2404
2405                                 printk(KERN_ERR "unable to request IRQ %d "
2406                                        "for DMA (error %d)\n",
2407                                        omap1_dma_irq[ch], r);
2408                                 for (i = 0; i < ch; i++)
2409                                         free_irq(omap1_dma_irq[i],
2410                                                  (void *) (i + 1));
2411                                 return r;
2412                         }
2413                 }
2414         }
2415
2416         if (cpu_is_omap2430() || cpu_is_omap34xx())
2417                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2418                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2419
2420         if (cpu_class_is_omap2())
2421                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2422
2423         /* FIXME: Update LCD DMA to work on 24xx */
2424         if (cpu_class_is_omap1()) {
2425                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2426                                 "LCD DMA", NULL);
2427                 if (r != 0) {
2428                         int i;
2429
2430                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2431                                "(error %d)\n", r);
2432                         for (i = 0; i < dma_chan_count; i++)
2433                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2434                         return r;
2435                 }
2436         }
2437
2438         return 0;
2439 }
2440
2441 arch_initcall(omap_init_dma);
2442
2443